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1. 发明专利

JP2011220578A Guidance system 有权
标题翻译：指导制度
公开(公告)号：JP2011220578A
公开(公告)日：2011-11-04
申请号：JP2010088477
申请日：2010-04-07
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： KAWASAKI HIROBUMI , NAKANE MASABUMI , SHIMIZU SETSUNDO
IPC分类号： F41G7/22 , G01S3/42 , G01S13/88
摘要： PROBLEM TO BE SOLVED: To obtain a guidance system which is mounted on a flying body such as a missile and does not incur fluctuation in an induction signal and response aggravation of angle tracking.SOLUTION: Temperature sensors are attached to an oscillator and a front end mounted on an antenna gimbal and temperatures of the oscillator and the front end are varied in the range of actual usage to construct a database of fluctuation in temperature of the oscillator and temperature of a DIF or SUM system signal phase. A database of a front end temperature mounted on the front end and the other system IF signal phase difference is similarly constructed. Using the constructed database, temperature fluctuation in IF signal phases of the DIF system and the SUM system are predicted from temperatures of each part by linear interpolation. The IF signal phase difference of the DIF system and the SUM system can be reduced by correcting the predicted phase difference of IF signals of the DIF system and the SUM system by using a phase shifter and fluctuation in the induction signal caused by temperature can be prevented. Thereby, response reduction of angle tracking can be prevented.
摘要翻译：要解决的问题：获得安装在诸如导弹的飞行体上的引导系统，并且不会引起感应信号的波动和角度跟踪的响应加剧。
解决方案：温度传感器连接到振荡器，前端安装在天线万向节上，振荡器和前端的温度在实际使用范围内变化，构成振荡器温度波动数据库， DIF或SUM系统信号相位的温度。类似地，安装在前端的前端温度的数据库和另一个系统的IF信号相位差。使用构建的数据库，通过线性插值从每个部分的温度预测DIF系统和SUM系统的IF信号相位的温度波动。通过使用移相器校正DIF系统和SUM系统的IF信号的预测相位差，可以降低DIF系统和SUM系统的IF信号相位差，并且可以防止由温度引起的感应信号的波动。从而可以防止角度跟踪的响应减小。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2007274081A Phase locked loop type frequency synthesizer 审中-公开
标题翻译：相位锁定型频率合成器
公开(公告)号：JP2007274081A
公开(公告)日：2007-10-18
申请号：JP2006094272
申请日：2006-03-30
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： TAJIMA KENICHI , HAYASHI RYOJI , NAKANE MASABUMI
IPC分类号： H03L7/197 , H03L7/085 , H03L7/089
摘要： PROBLEM TO BE SOLVED: To obtain a phase locked loop type frequency synthesizer in which spurious caused by error between flipflops of a phase comparator can be suppressed. SOLUTION: A subtraction circuit 33 performs voltage amplification of a phase comparison signal D nu (t) outputted from a phase comparator 33 with a first gain value α nu , performs voltage amplification of a phase comparison signal D nd (t) outputted from that phase comparator 33 with a second gain value α nd different from the first gain value α nu , and outputs the difference signal of the voltage amplified phase comparison signal D nu (t) and the voltage amplified second phase comparison signal D nd (t). COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：获得锁相环型频率合成器，其中可以抑制由相位比较器的触发器之间的误差引起的杂散。解决方案：减法电路33对相位比较器33输出的具有第一增益值α nu 的相位比较信号D nu（SB）进行电压放大，对与该第一增益值α不同的第二增益值α nd 从该相位比较器33输出的相位比较信号D nd （t）进行电压放大，输出电压放大相位比较信号D nu（s）和电压放大第二相位比较信号D nd （t）的差分信号，。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2010210263A Guide apparatus 有权
标题翻译：指导装置
公开(公告)号：JP2010210263A
公开(公告)日：2010-09-24
申请号：JP2009053658
申请日：2009-03-06
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： NAKANE MASABUMI
IPC分类号： G01S13/88 , F41G7/22 , F42B15/01 , G01S13/60
摘要： PROBLEM TO BE SOLVED: To provide a guide apparatus capable of being mounted on a flying object by suppressing an increase in size of a transceiver when improving coping performance with a small RCS target by transmitting a radio wave of a plurality of band frequencies. SOLUTION: The guide apparatus includes: a common excitation part exciting a local signal and an IF signal and generating a high-band transmission signal of a frequency obtained by adding a frequency of the IF signal to a frequency of the local signal and a low-band transmission signal having a frequency the same as that of the IF signal; a high-band front end down converting a high-band reception signal obtained by receiving a high-band transmission signal returned by the reflection at the target by the local signal; and a common reception part to which the high-band reception signal output from and down converted by the high-band front end and a low-band reception signal obtained by receiving the low-band transmission signal returned by the reflection at the target are input. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种能够通过抑制收发器的尺寸的增加而安装在飞行物体上的引导装置，通过发射多个频带频率的无线电波来改善小的RCS目标的应对性能。导向装置包括：激励本地信号和IF信号的公共激励部分，并产生通过将IF信号的频率与本地信号的频率相加而获得的频率的高频带传输信号，以及具有与IF信号相同频率的低频带传输信号; 高频带前端向下转换通过由本地信号接收由目标的反射返回的高频带发送信号而获得的高频带接收信号; 以及公共接收部分，由高频带前端输出的高频带接收信号和从其转换的高频带接收信号和通过接收由目标反射返回的低频带传输信号而获得的低频带接收信号被输入。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2008079104A Phase-locked loop type frequency synthesizer 审中-公开
标题翻译：相位锁定型频率合成器
公开(公告)号：JP2008079104A
公开(公告)日：2008-04-03
申请号：JP2006257420
申请日：2006-09-22
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： TAJIMA KENICHI , HAYASHI RYOJI , NAKANE MASABUMI
IPC分类号： H03L7/18
摘要： PROBLEM TO BE SOLVED: To attain phase synchronization in a desired frequency regardless of whether an output frequency range of a voltage controlled oscillator is a narrow band or a wide band. SOLUTION: A frequency mixing means is provided which mixes frequencies of a high frequency signal D o (t) and a local oscillation signal D p (t) and outputs a first low-frequency feedback signal D v1 (t) and a second low-frequency feedback signal D v2 (t) mutually having a phase difference of 90°, and phase comparators 9, 10 compares phases of the first and second low-frequency feedback signals D v1 (t), D v2 (t) with phases of first and second reference signals D r1 (t), D r2 (t) and output first and second phase comparison signals D e1 (t), D e2 (t) indicating a result of the phase comparison. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：无论压控振荡器的输出频率范围是窄带还是宽带，都能以期望的频率获得相位同步。解决方案：提供混频高频信号D o （t）和本地振荡信号D p （t）的频率混频装置，并输出相位差为90°的第一低频反馈信号D （t）和第二低频反馈信号D v2（S），相位差为90° 比较器9,10将第一和第二低频反馈信号D v1（t），D v2（SB）的相位与第一和第二参考信号D的相位进行比较（t），D r2（t），并输出第一和第二相位比较信号D e1（t），D e2 （t）表示相位比较的结果。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2005086297A Frequency synthesizer 审中-公开
标题翻译：频率合成器
公开(公告)号：JP2005086297A
公开(公告)日：2005-03-31
申请号：JP2003313592
申请日：2003-09-05
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： MIYAMOTO KAZUHIRO , NAKANE MASABUMI , TAJIMA KENICHI , TSURU MASAOMI
IPC分类号： H03L7/197 , H03L7/183
摘要： PROBLEM TO BE SOLVED: To attain a circuit for establishing a fractional operation in a state of stable phase synchronism in a high frequency/wide band F-PLL synthesizer employing an analog phase comparator. SOLUTION: A plurality of prescalers 9, 10 having different frequency division numbers are selectably arranged in a phase-locked loop, and a changeover switch 8 selects the prescalers 9, 10 having the optimum frequency division numbers according to an output frequency, so that fractional operation can be established in a state of stable phase synchronism even if an output frequency is set in a wide band. This configuration can solve the problem that phase synchronization becomes unstable during the fractional operation if an analog phase comparator having low noise performance for low noise and wide band and a prescaler are used to set an ouptput frequency low, in a wide-band frequency synthesizer of phase-locked loop of a fractional-N system. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：在采用模拟相位比较器的高频/宽带F-PLL合成器中，获得在稳定相位同步状态下建立分数运算的电路。解决方案：具有不同分频数的多个预分频器9,10可选地布置在锁相环中，转换开关8根据输出频率选择具有最佳分频数的预分频器9,10，使得即使输出频率设置在宽带中，也可以在稳定的相位同步的状态下建立分数运算。该配置可以解决在分数操作期间相位同步变得不稳定的问题，如果在低频和宽带的低噪声性能的模拟相位比较器和预分频器被用于在低频的频带频率合成器中设置低频频率合成器分数N系统的锁相环。版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JP2004253902A Fractional-n type phase locked loop frequency synthesizer 审中-公开
公开(公告)号：JP2004253902A
公开(公告)日：2004-09-09
申请号：JP2003040014
申请日：2003-02-18
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： TAJIMA KENICHI , TSURU MASAOMI , NAKANE MASABUMI , MIYAMOTO KAZUHIRO , TAKAGI SUNAO
IPC分类号： H03L7/197 , H03L7/10 , H03L7/183 , H03L7/187
摘要： PROBLEM TO BE SOLVED: To provide an F-PLL synthesizer which employs an analog phase comparator for a phase comparator and stably establishes phase locking at a high speed. SOLUTION: The F-PLL synthesizer includes a converging voltage setting section 21 for outputting a converging voltage signal to a loop filter 4 in order to establish phase locking of an external output oscillation signal in response to a control signal from a PLL control circuit 8. Outputting a DC output voltage V a from the converging voltage setting section 21 can set an oscillated frequency of a voltage-controlled oscillator 5 in a free-running state to the vicinity of a desired output frequency when no phase locking is established. As a result, the oscillated frequency from the voltage-controlled oscillator 5 reaches within a lock-in range of the PLL synthesizer, which stably establishes the phase locking. COPYRIGHT: (C)2004,JPO&NCIPI

7. 发明专利

JP2004241960A Frequency synthesizer 审中-公开
标题翻译：频率合成器
公开(公告)号：JP2004241960A
公开(公告)日：2004-08-26
申请号：JP2003027957
申请日：2003-02-05
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： NAKANE MASABUMI , TAJIMA KENICHI
IPC分类号： H03L7/22 , H03L7/087 , H03L7/197
摘要： PROBLEM TO BE SOLVED: To solve a problem in which a phase-locked loop type frequency synthesizer of a fractional-N system can not stably and quickly establish phase synchronism when using an analog phase comparator with low-noise property. SOLUTION: In a phase-lock loop, a digital phase comparator 5 and an analog phase comparator 4 are selectably arranged, and the digital phase comparator is used in a transient state of phase synchronism to perform converging operation; and presetting operation when an input voltage to a voltage-controlled oscillator 10 at the time is latched to perform switching to the analog phase comparator is carried out and while low-noise property is maintained, phase synchronism is stably established at a high speed. COPYRIGHT: (C)2004,JPO&NCIPI
摘要翻译：要解决的问题：为了解决当使用具有低噪声特性的模拟相位比较器时，分数N系统的锁相环型频率合成器不能稳定且快速地建立相位同步的问题。解锁方案：在锁相环路中，数字相位比较器5和模拟相位比较器4可选择地布置，并且数字相位比较器用于相位同步的瞬态状态以进行收敛操作; 并且当对该时刻的压控振荡器10的输入电压进行锁存以进行到模拟相位比较器的切换时，执行预置操作，并且在保持低噪声特性的同时，以高速稳定地建立相位同步。版权所有（C）2004，JPO＆NCIPI

8. 发明专利

JP2006005769A Negative capacitor circuit 有权
标题翻译：负电容电路
公开(公告)号：JP2006005769A
公开(公告)日：2006-01-05
申请号：JP2004181542
申请日：2004-06-18
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： TSURU MASAOMI , KAWAKAMI KENJI , TAJIMA KENICHI , MIYAZAKI MORIYASU , MIYAMOTO KAZUHIRO , NAKANE MASABUMI
IPC分类号： H03H11/48
摘要： PROBLEM TO BE SOLVED: To obtain a negative capacitor circuit that does not satisfy an unneeded oscillation condition by reducing loop gain in the negative capacitor circuit.
SOLUTION: An attenuator 4a is inserted and connected serially between the gate terminal of a first FET 1a and the drain terminal of a second FET 1b of the two FETS whose sources are grounded, an attenuator 4b is inserted and connected serially between the drain terminal of the first FET 1a and the gate terminal of the second FET 1b, an inductor one end of which is grounded is connected to the drain terminal of the first FET 1a, and a load one end of which is grounded is connected to the drain terminal of the second FET 1b.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过减小负电容电路中的环路增益来获得不满足不需要的振荡条件的负电容器电路。解决方案：衰减器4a串联连接在第一FET 1a的栅极端子和源极接地的两个FET的第二FET 1b的漏极端子之间，衰减器4b插入并串联连接第一FET 1a的漏极端子和第二FET 1b的栅极端子，其一端接地的电感器连接到第一FET 1a的漏极端子，并且其一端接地的负载连接到漏极端子。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2005151444A Frequency synthesizer 审中-公开
标题翻译：频率合成器
公开(公告)号：JP2005151444A
公开(公告)日：2005-06-09
申请号：JP2003389514
申请日：2003-11-19
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： NAKANE MASABUMI
IPC分类号： H03L7/18
摘要： PROBLEM TO BE SOLVED: To solve such a problem that a periodic noise occurs since a control for temporally changing a frequency division of a variable frequency divider is required at a ratio according to a setting in a frequency synthesizer of a fractional-N mode phase synchronous circuit type used for a radar and a wireless communication device. SOLUTION: A fractional-N mode phase synchronous circuit is provided with, between a loop filter and a voltage control oscillator 6, a low-pass filter 9 with a cutoff frequency which is fully higher than a loop bandwidth frequency of the phase synchronous circuit and which determines a fractional frequency division ratio of a PLL control circuit 8, and which is fully lower than a periodic frequency. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了解决出现周期性噪声的问题，因为需要根据频率合成器中的分数N的设置的比例来对可变分频器的分频进行时间上改变的控制模式相位同步电路类型用于雷达和无线通信设备。解决方案：分数N模式相位同步电路在环路滤波器和压控振荡器6之间提供低通滤波器9，其截止频率完全高于相位的环路带宽频率同步电路，其确定PLL控制电路8的分数分频比，其完全低于周期性频率。版权所有（C）2005，JPO＆NCIPI

10. 发明专利

JP2005033581A Phase synchronization loop type frequency synthesizer of fractional-n method 审中-公开
$Phase synchronization loop type frequency synthesizer of fractional-n method$
标题翻译：分类方法的相位同步环类型频率合成器
公开(公告)号：JP2005033581A
公开(公告)日：2005-02-03
申请号：JP2003271394
申请日：2003-07-07
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： TAJIMA KENICHI , TSURU MASAOMI , NAKANE MASABUMI , TAKAGI SUNAO
IPC分类号： H03L7/183 , H03L7/197 , H04B14/06
CPC分类号： H03L7/1976
摘要： PROBLEM TO BE SOLVED: To provide a phase synchronization loop type frequency synthesizer of a fractional-N method operating with a high speed and stability. SOLUTION: There is provided the phase synchronization loop type frequency synthesizer of a fractional-N method comprising a reference oscillating source 101 for producing reference signals, a voltage control oscillator 5 for generating high-frequency signals, a feedback circuit 102 for producing synchronous signals from the high-frequency signals, a phase comparator 3 for inputting the reference signals and the synchronous signals, and a loop filter 4 for inputting the output of the phase comparator to output control signals of the voltage control oscillator. In the phase synchronization loop type frequency synthesizer, the feedback circuit 102 is equipped with variable dividers 6a, 6b which divides the high-frequency signals and outputs the synchronous signals and further two or more of which are series-connected, and modulation circuits 7a, 7b that are provided for each of these variable dividers and output the control signals of each variable divider depending on set data from an outside according to clock signals. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供以高速度和稳定的方式操作的分数N方法的相位同步环路型频率合成器。提供了一种分数N方法的相位同步环型频率合成器，包括用于产生参考信号的参考振荡源101，用于产生高频信号的电压控制振荡器5，用于产生高频信号的反馈电路102 来自高频信号的同步信号，用于输入参考信号和同步信号的相位比较器3，以及用于输入相位比较器的输出以输出电压控制振荡器的控制信号的环路滤波器4。在相位同步环型频率合成器中，反馈电路102配备有可变分频器6a，6b，其分频高频信号并输出同步信号，并且其中两个或更多个是串联连接的，并且调制电路7a， 7b，其被设置用于这些可变分频器中的每一个，并且根据来自外部的设置数据根据时钟信号输出每个可变分频器的控制信号。版权所有（C）2005，JPO＆NCIPI

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