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1. 发明申请

US20030008463A1 Circuit protecting against electrostatic discharge 失效
标题翻译：电路防静电放电
公开(公告)号：US20030008463A1
公开(公告)日：2003-01-09
申请号：US10066608
申请日：2002-02-06
申请人： Mitsubishi Denki Kabushiki Kaisha
发明人： Takahiro Ohnakado , Tatsuo Oomori
IPC分类号： H01L021/336
CPC分类号： H01L27/0266 , H01L27/0251
摘要： A quarter wavelength transmission line is provided between a signal transmission line for transmitting a high frequency signal and a ground node. The quarter wavelength transmission line has a length equal to a quarter of an effective wavelength of an operation frequency of a semiconductor device. A surge absorbing element is connected between the quarter wavelength transmission line and an internal circuit. The signal transmission line is coupled to the internal circuit through a capacitor. A clamp circuit is provided between a power supply line and a ground line. The clamp circuit clamps the voltage difference between the power supply line and the ground line to a prescribed voltage level or less. A high frequency semiconductor device is thus implemented which is capable of preventing breakdown of an internal circuit element due to an electrostatic discharge phenomenon (ESD) without degrading high frequency characteristics.
摘要翻译：在用于发送高频信号的信号传输线和接地节点之间提供四分之一波长的传输线。四分之一波长传输线具有等于半导体器件的工作频率的有效波长的四分之一的长度。浪涌吸收元件连接在四分之一波长传输线和内部电路之间。信号传输线通过电容耦合到内部电路。在电源线和接地线之间设置钳位电路。钳位电路将电源线和接地线之间的电压差钳位到规定的电压电平以下。因此，可以实现能够防止由于静电放电现象（ESD）而导致的内部电路元件的破坏而不降低高频特性的高频半导体器件。

2. 发明申请

US20020146878A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20020146878A1
公开(公告)日：2002-10-10
申请号：US09946492
申请日：2001-09-06
申请人： Mitsubishi Denki Kabushiki Kaisha
发明人： Takahiro Ohnakado , Satoshi Yamakawa
IPC分类号： H01L021/8238 , H01L021/336
CPC分类号： H01L21/82385 , H01L21/823871 , H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device causing no malfunction and having high ESD resistance against all cases of surges as well as a method of manufacturing the same are obtained. The semiconductor device includes an internal circuit, an I/O pad, a division circuit connected to a lead-in line connecting the internal circuit and the I/O pad for outputting an electric signal from first and second terminals corresponding to an electric signal applied to the lead-in line and a clamp circuit formed of an MOS transistor for cutting off conduction when a difference in voltage between the electric signals sent from one and the other terminal sides is smaller in absolute value than a threshold voltage of said MOS transistor, and producing the conduction when the absolute value is equal to or larger than the threshold voltage.
摘要翻译：获得了对所有情况下的不产生故障并且具有高耐ESD性的半导体器件及其制造方法。半导体器件包括内部电路，I / O焊盘，连接到连接内部电路和I / O焊盘的引入线的分割电路，用于输出来自第一和第二端子的电信号，所述电信号对应于施加的电信号以及由MOS晶体管形成的钳位电路，当从一个端子侧发送的电信号的电压差与绝缘值小于所述MOS晶体管的阈值电压时，用于截断导通的钳位电路，并且当绝对值等于或大于阈值电压时产生导通。

3. 发明申请

US20030117206A1 High-frequency semiconductor device 审中-公开
标题翻译：高频半导体器件
公开(公告)号：US20030117206A1
公开(公告)日：2003-06-26
申请号：US10145152
申请日：2002-05-15
申请人： Mitsubishi Denki Kabushiki Kaisha
发明人： Takahiro Ohnakado
IPC分类号： H03L005/00
CPC分类号： H01L27/0251
摘要： An ESD (electrostatic discharge) protective circuit is connected to a node which is branching a high frequency signal input/output line connected to a high frequency input/output pad. A high frequency internal circuit is connected as a succeeding stage via a DC blocking capacitor such as a PIP (Polysilicon Insulator Polysilicon) capacitor, MIM (Metal Insulator Metal) capacitor, or comb capacitor to implement high ESD tolerability without significantly degrading high frequency characteristics.
摘要翻译： ESD（静电放电）保护电路连接到分支连接到高频输入/输出板的高频信号输入/输出线的节点。高频内部电路通过诸如PIP（多晶硅绝缘体多晶硅）电容器，MIM（金属绝缘体金属）电容器或梳状电容器的隔直电容器作为后续级连接，以实现高ESD耐受性而不会显着降低高频特性。

4. 发明申请

US20030075765A1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US20030075765A1
公开(公告)日：2003-04-24
申请号：US10274451
申请日：2002-10-21
申请人： Mitsubishi Denki Kabushiki Kaisha
发明人： Takahiro Ohnakado , Akihiko Furukawa
IPC分类号： H01L029/76
CPC分类号： H01L21/823807 , H01L21/823892 , H01L27/0921 , H03K17/693
摘要： A semiconductor integrated circuit device includes a silicon substrate having a first region and a second region identical in conductivity to said first region and having a lower dopant concentration than said first region, a second MOS transistor formed on a main surface of said second region and configuring a radio frequency switch circuit switching on/off an input and output of a radio frequency signal, and a first MOS transistor formed on a main surface of said first region and configuring a radio frequency circuit other than said radio frequency switch circuit. There can be provided a high performance, highly reliable semiconductor integrated circuit with an RF switch circuit provided on a silicon substrate by SOPing.
摘要翻译：半导体集成电路器件包括具有第一区域和与所述第一区域的导电性相同的第二区域并具有比所述第一区域低的掺杂剂浓度的硅衬底，形成在所述第二区域的主表面上的第二MOS晶体管和配置开关射频信号的输入和输出的射频开关电路和形成在所述第一区域的主表面上的第一MOS晶体管，并且配置除了所述射频开关电路之外的射频电路。可以通过SOPing在硅衬底上提供具有RF开关电路的高性能，高可靠性的半导体集成电路。

5. 发明申请

US20020033504A1 Si-MOS high-frequency semiconductor device and the manufacturing method of the same 失效
标题翻译： Si-MOS高频半导体器件及其制造方法
公开(公告)号：US20020033504A1
公开(公告)日：2002-03-21
申请号：US09911581
申请日：2001-07-25
申请人： Mitsubishi Denki Kabushiki Kaisha
发明人： Takahiro Ohnakado
IPC分类号： H01L027/148
CPC分类号： H01L27/0255 , H01L27/0629 , H01L2924/0002 , H01L2924/00
摘要： An object of the present invention is to provide a sophisticated and highly reliable high-frequency Si-MOS semiconductor device having high ESD resistance. In the semiconductor device according to the present invention, lateral polysilicon diodes are formed and connected between high-frequency I/O signal line and the external supply voltage VDD, and between the ground GND and the high-frequency I/O signal line respectively. The forward direction of the diodes is the direction from the high-frequency I/O signal line to the VDD and the direction from the ground GND to the high-frequency I/O signal line respectively.
摘要翻译：本发明的目的是提供一种具有高耐ESD性的复杂且高可靠性的高频Si-MOS半导体器件。在根据本发明的半导体器件中，横向多晶硅二极管分别形成并连接在高频I / O信号线和外部电源电压VDD之间，并分别连接在地GND和高频I / O信号线之间。二极管的正向是分别从高频I / O信号线到VDD的方向以及从地GND到高频I / O信号线的方向。

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