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1. 发明授权

US06781412B2 Logic circuit for fast carry/borrow 失效
标题翻译：用于快速携带/借位的逻辑电路
公开(公告)号：US06781412B2
公开(公告)日：2004-08-24
申请号：US10073132
申请日：2002-02-13
申请人： Shuji Yoshida , Daisuke Miura , Toshio Arakawa , Mitsuaki Nagasaka , Kenji Yoshida , Hiroyuki Honda , Kenji Kobayashi , Masayuki Okamoto
发明人： Shuji Yoshida , Daisuke Miura , Toshio Arakawa , Mitsuaki Nagasaka , Kenji Yoshida , Hiroyuki Honda , Kenji Kobayashi , Masayuki Okamoto
IPC分类号： H03K1921
CPC分类号： G06F7/5055 , G06F7/503
摘要： Each binary carry logic circuit 20 of half adder circuits other than that for the least significant digit comprises a transfer gate 212 turned on when an input bit A2 is active and receiving a carry-in bit *C2 at its data input, and a transistor 23, turned on when the input bit A2 is inactive, connected between a power supply potential VDD and the data output of the transfer gate 212 a signal on which is a carry-out bit *C3. Transfer gates 212 to 214 of binary carry logic circuits other than that for the least significant digit are connected in chain, and are simultaneously on/off controlled by input bits A2 to A4, letting the carry-in bit *C2 from the least significant digit propagate through the transfer gate chain at a high speed.
摘要翻译：除了最低有效位之外的半加法器电路的每个二进制进位逻辑电路20包括当输入位A2有效并在其数据输入端接收进位位* C2的传输门212导通，并且晶体管23 ，当输入位A2不活动时，在电源电位VDD和传输门212的数据输出之间连接作为进位位* C3的信号。二进制逻辑电路以外的二进制进位逻辑电路的转移门212至214串联连接，同时由输入位A2至A4进行开/关控制，使来自最低有效位的进位位* C2 通过传输门链高速传播。

2. 发明授权

US06760897B2 Method and apparatus for automatic wiring design between block circuits of integrated circuit 失效
标题翻译：集成电路块电路之间的自动布线设计方法和装置
公开(公告)号：US06760897B2
公开(公告)日：2004-07-06
申请号：US10209927
申请日：2002-08-02
申请人： Toshio Arakawa , Daisuke Miura , Masayuki Okamoto , Mitsuaki Nagasaka , Hiroyuki Honda , Shuji Yoshida , Kenji Kobayashi , Kenji Yoshida
发明人： Toshio Arakawa , Daisuke Miura , Masayuki Okamoto , Mitsuaki Nagasaka , Hiroyuki Honda , Shuji Yoshida , Kenji Kobayashi , Kenji Yoshida
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： Disclosed is a method for automatic wiring design between block circuits of an integrated circuit, which performs an automatic connection between an inter-block wire disposed between a first circuit block and a second circuit block, and terminals formed along sides of the first and second blocks, the sides facing each other. The method comprises the steps of (S2) sorting the terminals according to the width thereof; and (S3˜S11) selecting a terminal from the terminals in descending order of the width, and connecting between the selected terminal and an inter-block wire belonging to a same net as the terminal. In another embodiment, the method comprises the steps of (a) sorting the terminals, connected to a power supply wire, according to the value of electric current passing through the terminals; and (b) selecting a terminal from the terminals in descending order of the value of electric current and connecting between the selected terminal and an inter-block wire belonging to a same net as the selected terminal.
摘要翻译：公开了一种在集成电路的块电路之间进行自动布线设计的方法，该集成电路在布置在第一电路块和第二电路块之间的块间电线之间执行自动连接，以及沿着第一和第二块的侧面形成的端子，双方面对面。该方法包括以下步骤：（S2）根据其宽度对终端进行分类; 和（S3〜S11）从所述端子以宽度的降序选择端子，以及连接所选择的端子与属于与所述端子相同的网的块间线。在另一个实施例中，该方法包括以下步骤：（a）根据通过端子的电流值对连接到电源线的端子进行排序; 以及（b）从电流值的降序中选择终端，并且连接所选择的终端与属于与所选终端相同的网的块间线。

3. 发明授权

US06857107B2 LSI layout method and apparatus for cell arrangement in which timing is prioritized 有权
标题翻译：用于小区布置的LSI布局方法和装置，其中优先考虑定时
公开(公告)号：US06857107B2
公开(公告)日：2005-02-15
申请号：US10079545
申请日：2002-02-22
申请人： Mitsuaki Nagasaka , Daisuke Miura , Masayuki Okamoto , Hiroyuki Honda , Toshio Arakawa , Shuji Yoshida , Kenji Yoshida , Kenji Kobayashi
发明人： Mitsuaki Nagasaka , Daisuke Miura , Masayuki Okamoto , Hiroyuki Honda , Toshio Arakawa , Shuji Yoshida , Kenji Yoshida , Kenji Kobayashi
IPC分类号： G06F17/50 , H01L21/82
CPC分类号： G06F17/5068
摘要： In a layout method for an LSI having a plurality of cells, automated arrangement of cells is performed on the basis of a netlist, which has cells and connection data therefor, and timing conditions, and, once a timing optimization processing is performed so that a plurality of cells are arranged on a chip, global wiring processing is implemented and the wiring congestion rate is analyzed. In addition, in small regions where a wiring congestion rate is so high that detailed wiring processing is judged to be difficult, cell rearrangement processing is implemented. Next, detailed wiring processing is performed with respect to the cells which have been rearranged. The rearrangement of cells is performed only in small regions with a high congestion rate, with the result that the overall cell arrangement in which timing is optimized is not changed markedly, whereby it is possible to reduce the probability of wiring being impossible in the course of the detailed wiring processing.
摘要翻译：在具有多个单元的LSI的布局方法中，基于具有单元和连接数据的网表以及定时条件来执行单元的自动布置，并且一旦进行了定时优化处理，多个单元被布置在芯片上，实现全局布线处理并分析布线拥塞率。此外，在布线堵塞率如此高的小区域中，判断为难以进行详细布线处理，实现了单元重排处理。接下来，对已经重新排列的单元执行详细的布线处理。单元的重新排列仅在具有高拥塞率的小区域中进行，结果是定时优化的整体单元布置没有明显变化，从而可以降低布线过程中不可能的布线概率详细的布线处理。

4. 发明申请

US20060053399A1 Semiconductor device, designing device, layout designing method, program and storage medium 审中-公开
标题翻译：半导体器件，设计器件，布局设计方法，程序和存储介质
公开(公告)号：US20060053399A1
公开(公告)日：2006-03-09
申请号：US11014843
申请日：2004-12-20
申请人： Hiroyuki Honda , Toshio Arakawa , Hiroshi Mawatari , Norito Hibino , Kouji Arai , Keigo Tada , Fukuji Kihara
发明人： Hiroyuki Honda , Toshio Arakawa , Hiroshi Mawatari , Norito Hibino , Kouji Arai , Keigo Tada , Fukuji Kihara
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5068
摘要： A designing device for designing a layout of a semiconductor device includes a layout position candidate extracting unit for obtaining layout position candidates of a regulator, a tentatively wiring unit for tentatively arranging the regulator at the layout position candidates and tentatively laying out a power line, and a regulator layout position deciding unit for deciding a position of a tentative layout at which an area of the power line that is tentatively laid out is the smallest as the layout position of the regulator.
摘要翻译：用于设计半导体器件的布局的设计装置包括：布局位置候选提取单元，用于获得调节器的布局位置候选;暂时布线单元，用于暂时地将调节器布置在布局位置候选位置并暂时布置电力线;以及调节器布置位置决定单元，用于决定暂时布置的电力线的区域最小的暂定布局的位置作为调节器的布局位置。

5. 发明授权

US06990642B2 Design method for integrated circuit having scan function 失效
标题翻译：具有扫描功能的集成电路设计方法
公开(公告)号：US06990642B2
公开(公告)日：2006-01-24
申请号：US10634857
申请日：2003-08-06
申请人： Toshio Arakawa
发明人： Toshio Arakawa
IPC分类号： G06F17/50
CPC分类号： G01R31/318583 , G01R31/3016 , G01R31/31858 , G06F17/5045
摘要： The present invention provides a method for designing LSI including a logic circuit equipped with a scan circuit without generating a hard-macro library for the scan flip flops constituting the scan circuit. According to the method, first netlist NL1 is converted into second netlist NL2 by adding scan circuit including scan flip-flops. Order data for connecting scan chain of the scan circuit is extracted from the second netlist NL2. Such second netlist NL2 is converted into third netlist NL3 including only hard-macros, and the third netlist NL3 is laid-out by re-ordering the scan chain so that the newly generated order data for is stored temporally. Fourth netlist NL4 including scan circuit formed by scan flip-flops of soft-macros is generated on the basis of the stored order data, then the fourth netlist NL4 is converted into fifth netlist NL5 by substituting the scan flip-flops of soft-macros for standard cells of hard-macros. Finally the generated fifth netlist is laid-out without re-ordering the scan chain.
摘要翻译：本发明提供了一种用于设计LSI的方法，其包括具有扫描电路的逻辑电路，而不产生构成扫描电路的扫描触发器的硬宏库。根据该方法，通过添加包括扫描触发器的扫描电路，将第一网表NL 1转换为第二网表NL2。从第二个网表NL2提取连接扫描电路的扫描链的订单数据。这样的第二网表NL2被转换成仅包括硬宏的第三网表NL 3，并且通过重新排序扫描链来布置第三网表NL3，使得新产生的订单数据被暂时存储。基于存储的顺序数据生成包括由软宏的扫描触发器形成的扫描电路的第四网表NL4，然后通过将扫描触发器替换为软的第四网表NL5而被转换成第五网表NL5 - 宏的标准单元格的宏。最后，生成的第五个网表被布局，而不重新排序扫描链。

6. 发明授权

US5166486A Turntable support for heating cooking appliances 失效
标题翻译：用于加热烹饪器具的可靠支持
公开(公告)号：US5166486A
公开(公告)日：1992-11-24
申请号：US595384
申请日：1990-10-10
申请人： Morimasa Komatsu , Toshio Arakawa , Keizo Shimeno
发明人： Morimasa Komatsu , Toshio Arakawa , Keizo Shimeno
IPC分类号： H05B6/80
CPC分类号： H05B6/6411
摘要： A microwave oven includes a casing defining a heating chamber, a track member disposed in the heating chamber and having an undulate surface circumferentially extended, an electric motor mounted in the casing, a plurality of rolling members each moved along the undulate surface of the track member by the motor, rolling about respective axes thereof in contact with the undulate surface of the track member, and a turntable on which food to be cooked is placed, the turntable having a traveling face and placed on the rolling members so that the traveling face thereof is in contact with the rolling members, whereby the turntable is rotated with a vertical movement.

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