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1. 发明授权

US07411806B2 Memory module and memory system 有权
标题翻译：内存模块和内存系统
公开(公告)号：US07411806B2
公开(公告)日：2008-08-12
申请号：US11634405
申请日：2006-12-06
申请人： Seiji Funaba , Yoji Nishio , Kayoko Shibata
发明人： Seiji Funaba , Yoji Nishio , Kayoko Shibata
IPC分类号： G11C5/06 , G11C5/02
CPC分类号： G11C5/04 , G11C5/063 , G11C7/1048 , G11C11/4093 , G11C2207/105 , H01L2224/16225 , H01L2924/15192 , H01L2924/15311 , H01L2924/19107
摘要： A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.
摘要翻译：存储器模块具有在板的前表面和后表面上共享总线的多个DRAM（115）。总线通过通孔（113）从端子（111）连接到带状线（112）的一端，并且带状线的另一端通过通孔（113）连接到另一层中的带状线孔（119）用于使线路循环。设置在终端电压端子（VTT）附近的终端电阻器（120）通过通孔连接到另一层中的环形带状线。 DRAM端子通过通孔连接到带状线。该存储器模块通过连接器安装在其上提供存储器控制器的母板上。母线的有效特性阻抗与母板线路特性阻抗匹配。

2. 发明申请

US20060006516A1 Stacked semiconductor device and semiconductor memory module 有权
标题翻译：堆叠半导体器件和半导体存储器模块
公开(公告)号：US20060006516A1
公开(公告)日：2006-01-12
申请号：US11176292
申请日：2005-07-08
申请人： Seiji Funaba , Yoji Nishio
发明人： Seiji Funaba , Yoji Nishio
IPC分类号： H01L23/02
CPC分类号： H01L23/66 , G11C5/04 , G11C5/063 , H01L24/06 , H01L24/49 , H01L25/0657 , H01L2224/0401 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/0603 , H01L2224/06136 , H01L2224/49171 , H01L2225/06527 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/15311 , H01L2924/15331 , H01L2924/19041 , H01L2924/19105 , H01L2924/19106 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device module includes a wiring substrate, a plurality of stacked semiconductor devices and a damping impedance circuit. The plurality of stacked semiconductor devices are provided on the wiring substrate and connected with a signal in a stubless manner, and each of the plurality of stacked semiconductor devices comprises a plurality of semiconductor chips which are stacked. The damping impedance circuit is provided for a transmission path of the signal for an uppermost semiconductor chip as the furthest one, from the wiring substrate, of the plurality of semiconductor chips of a first stacked semiconductor device as one of the plurality of stacked semiconductor devices which is first supplied with the signal.
摘要翻译：半导体器件模块包括布线基板，多个堆叠半导体器件和阻尼阻抗电路。多个堆叠的半导体器件设置在布线基板上，并且以简单的方式与信号连接，并且多个堆叠的半导体器件中的每一个包括堆叠的多个半导体芯片。阻尼阻抗电路被设置为用于作为多个半导体器件中的一个堆叠半导体器件的第一堆叠半导体器件的多个半导体芯片中的最上半个半导体芯片的信号的距离布线基板的最远的信号的传输路径，首先提供信号。

3. 发明申请

US20050139977A1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US20050139977A1
公开(公告)日：2005-06-30
申请号：US11019553
申请日：2004-12-23
申请人： Yoji Nishio , Seiji Funaba
发明人： Yoji Nishio , Seiji Funaba
IPC分类号： H01L23/14 , G06F1/18 , G06F13/00 , G11C5/02 , G11C7/00 , G11C11/407 , H01L21/68 , H01L23/02 , H01L23/498 , H01L23/50 , H01L23/66 , H01L25/065 , H01L25/07 , H01L27/108 , H05K1/14
CPC分类号： H01L23/66 , G06F1/184 , G06F1/185 , G06F1/186 , G11C5/025 , H01L21/6835 , H01L23/49822 , H01L23/49833 , H01L23/50 , H01L2221/6834 , H01L2221/68368 , H01L2224/16 , H01L2924/01004 , H01L2924/0102 , H01L2924/01068 , H01L2924/13091 , H01L2924/15311 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H05K1/141 , H01L2924/00
摘要： A COC DRAM including a plurality of stacked DRAM chips is mounted on a motherboard by using an interposer. The interposer includes a Si unit and a PCB. The Si unit includes a Si substrate and an insulating-layer unit in which wiring is installed. The PCB includes a reference plane for the wiring in the Si unit. The wiring topology between a chip set and the COC DRAM is the same for every signal. Accordingly, a memory system enabling a high-speed operation, low power consumption, and large capacity is provided.
摘要翻译：包括多个堆叠的DRAM芯片的COC DRAM通过使用插入件安装在母板上。插入器包括Si单元和PCB。 Si单元包括Si基板和布置布线的绝缘层单元。 PCB包括用于Si单元中布线的参考平面。芯片组和COC DRAM之间的布线结构对于每个信号是相同的。因此，提供了能够进行高速运转，低功耗，大容量的存储器系统。

4. 发明授权

US06628538B2 Memory module including module data wirings available as a memory access data bus 有权
标题翻译：存储器模块包括可用作存储器访问数据总线的模块数据配线
公开(公告)号：US06628538B2
公开(公告)日：2003-09-30
申请号：US10105249
申请日：2002-03-26
申请人： Seiji Funaba , Yoshinobu Nakagome , Masashi Horiguchi , Yoji Nishio
发明人： Seiji Funaba , Yoshinobu Nakagome , Masashi Horiguchi , Yoji Nishio
IPC分类号： G11C506
CPC分类号： G11C5/06 , G11C5/04 , G11C5/063 , H01L23/5387 , H01L25/065 , H01L25/0655 , H01L25/0657 , H01L2224/16 , H01L2225/06517 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06579 , H01L2924/01055 , H01L2924/15312 , H01L2924/1532 , H01L2924/3011
摘要： A module substrate has a plurality of module data terminal pairs individually provided in association with respective chip data terminals in a plurality of memory chips, and a plurality of module data wirings which respectively connect between the plurality of module data terminal pairs. The plurality of module data wirings are connected to their corresponding chip data terminals and are configured so as to be available as a memory access data bus. In a memory system in which a plurality of memory modules are arranged in parallel, module data wirings of each individual memory modules are connected in serial form, and each individual module data wirings do not constitute branch wirings with respect to a data bus on a motherboard of the memory system. In the memory modules, parallel access for the number of bits corresponding to the width of the memory access data bus is assured.
摘要翻译：模块基板具有与多个存储器芯片中的各个芯片数据端子相关联地分别设置的多个模块数据端子对以及分别连接在多个模块数据端子对之间的多个模块数据布线。多个模块数据布线连接到它们对应的芯片数据终端，并被配置为可用作存储器访问数据总线。在并行布置多个存储器模块的存储器系统中，各个存储器模块的模块数据布线以串行形式连接，并且每个单独的模块数据布线不构成相对于主板上的数据总线的分支布线的内存系统。在存储器模块中，确保与存储器访问数据总线的宽度相对应的位数的并行访问。

5. 发明授权

US07656744B2 Memory module with load capacitance added to clock signal input 失效
标题翻译：负载电容加到时钟信号输入的存储模块
公开(公告)号：US07656744B2
公开(公告)日：2010-02-02
申请号：US11611036
申请日：2006-12-14
申请人： Yurika Aoki , Seiji Funaba , Yoji Nishio
发明人： Yurika Aoki , Seiji Funaba , Yoji Nishio
IPC分类号： G11C8/00
CPC分类号： G11C5/063 , G11C5/04
摘要： A novel memory module with a multiple-rank configuration is provided to solve the problem that high-speed operation is impossible due to the fact that timing of a data strobe signal input to a memory is deviated from timing of a clock signal input thereto. In the memory module, a load capacity is provided at the vicinity of a clock signal input pin of a phase-locked loop circuit where the clock signal is input to match a time constant of a data strobe signal line with a time constant of a clock signal line. The matching of the input timings of the clock signal and the data strobe signal input to the memory enables the memory module to operate at a high speed.
摘要翻译：提供了具有多级配置的新型存储器模块，以解决由于输入到存储器的数据选通信号的定时偏离输入到其的时钟信号的定时的事实而无法进行高速操作的问题。在存储器模块中，在锁存环路电路的时钟信号输入引脚附近提供负载能力，其中输入时钟信号以使数据选通信号线的时间常数与时钟的时间常数相匹配信号线。时钟信号的输入定时和输入到存储器的数据选通信号的匹配使得存储器模块能够以高速运行。

6. 发明申请

US20090115442A1 Semiconductor integrated circuit and electronic device 有权
公开(公告)号：US20090115442A1
公开(公告)日：2009-05-07
申请号：US12314291
申请日：2008-12-08
申请人： Seiji Funaba , Yoji Nishio
发明人： Seiji Funaba , Yoji Nishio
IPC分类号： G01R31/02
CPC分类号： G11C7/22 , G11C5/04 , G11C7/1045 , G11C7/222 , G11C11/4076 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/50012 , H05K1/0248 , H05K1/0268 , H05K1/14 , H05K2201/044 , H05K2201/09781
摘要： A dummy wiring 25 is provided for simulating an actual wiring 26 connecting semiconductor integrated circuits 2 and 6 on a circuit board. The semiconductor integrated circuit comprises a data output circuit 28 capable of variably setting the slew rate and a circuit 29 for measuring signal delay time between a signal sending point and a signal reflection point (characteristic impedance mismatching point) using the dummy wiring 25, and the delay time so obtained by the measuring circuit is used for the determination of the signal transition time of the output circuit. The transition time of the signal is set at least twice of the signal delay time between the signal sending point and the wiring branch at the nearest end. In this way, signal transmission with alleviated reflection by the reflection point at the nearest end is realized.

7. 发明授权

US07385281B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07385281B2
公开(公告)日：2008-06-10
申请号：US11019553
申请日：2004-12-23
申请人： Yoji Nishio , Seiji Funaba
发明人： Yoji Nishio , Seiji Funaba
IPC分类号： H01L23/02 , H01L23/12 , G11C7/00 , G06F13/00 , H01I23/14
CPC分类号： H01L23/66 , G06F1/184 , G06F1/185 , G06F1/186 , G11C5/025 , H01L21/6835 , H01L23/49822 , H01L23/49833 , H01L23/50 , H01L2221/6834 , H01L2221/68368 , H01L2224/16 , H01L2924/01004 , H01L2924/0102 , H01L2924/01068 , H01L2924/13091 , H01L2924/15311 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H05K1/141 , H01L2924/00
摘要： A COC DRAM including a plurality of stacked DRAM chips is mounted on a motherboard by using an interposer. The interposer includes a Si unit and a PCB. The Si unit includes a Si substrate and an insulating-layer unit in which wiring is installed. The PCB includes a reference plane for the wiring in the Si unit. The wiring topology between a chip set and the COC DRAM is the same for every signal. Accordingly, a memory system enabling a high-speed operation, low power consumption, and large capacity is provided.
摘要翻译：包括多个堆叠的DRAM芯片的COC DRAM通过使用插入件安装在母板上。插入器包括Si单元和PCB。 Si单元包括Si基板和布置布线的绝缘层单元。 PCB包括用于Si单元中布线的参考平面。芯片组和COC DRAM之间的布线结构对于每个信号是相同的。因此，提供了能够进行高速运转，低功耗，大容量的存储器系统。

8. 发明授权

US07282791B2 Stacked semiconductor device and semiconductor memory module 有权
标题翻译：堆叠半导体器件和半导体存储器模块
公开(公告)号：US07282791B2
公开(公告)日：2007-10-16
申请号：US11176292
申请日：2005-07-08
申请人： Seiji Funaba , Yoji Nishio
发明人： Seiji Funaba , Yoji Nishio
IPC分类号： H01L23/02
CPC分类号： H01L23/66 , G11C5/04 , G11C5/063 , H01L24/06 , H01L24/49 , H01L25/0657 , H01L2224/0401 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/0603 , H01L2224/06136 , H01L2224/49171 , H01L2225/06527 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/15311 , H01L2924/15331 , H01L2924/19041 , H01L2924/19105 , H01L2924/19106 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device module includes a wiring substrate, a plurality of stacked semiconductor devices and a damping impedance circuit. The plurality of stacked semiconductor devices are provided on the wiring substrate and connected with a signal in a stubless manner, and each of the plurality of stacked semiconductor devices comprises a plurality of semiconductor chips which are stacked. The damping impedance circuit is provided for a transmission path of the signal for an uppermost semiconductor chip as the furthest one, from the wiring substrate, of the plurality of semiconductor chips of a first stacked semiconductor device as one of the plurality of stacked semiconductor devices which is first supplied with the signal.
摘要翻译：半导体器件模块包括布线基板，多个堆叠半导体器件和阻尼阻抗电路。多个堆叠的半导体器件设置在布线基板上，并且以简单的方式与信号连接，并且多个堆叠的半导体器件中的每一个包括堆叠的多个半导体芯片。阻尼阻抗电路被设置为用于作为多个半导体器件中的一个堆叠半导体器件的第一堆叠半导体器件的多个半导体芯片中的最上半个半导体芯片的信号的距离布线基板的最远的信号的传输路径，首先提供信号。

9. 发明申请

US20070085601A1 Semiconductor memory device and memory module 有权
标题翻译：半导体存储器件和存储器模块
公开(公告)号：US20070085601A1
公开(公告)日：2007-04-19
申请号：US11580275
申请日：2006-10-13
申请人： Yoji Idei , Susumu Hatano , Yoji Nishio , Seiji Funaba , Yutaka Uematsu
发明人： Yoji Idei , Susumu Hatano , Yoji Nishio , Seiji Funaba , Yutaka Uematsu
IPC分类号： H03B1/00
CPC分类号： G11C11/4074 , G11C5/147
摘要： A semiconductor memory device of the present invention determines a logic level of a signal based on a predetermined reference voltage. And the memory device has an input terminal to which a reference signal having the reference voltage is input, a low-pass filter connected to the input terminal for passing a component of the reference voltage of the reference signal and eliminating undesired high frequency components, and one or more input first-stage circuits to each of which an output of the low-pass filter and a signal having the logic level to be determined are connected. In the memory device, the low-pass filter has predetermined attenuation at least at a frequency of an operating clock.
摘要翻译：本发明的半导体存储器件基于预定的参考电压确定信号的逻辑电平。并且存储器件具有输入具有参考电压的参考信号的输入端子，连接到输入端子的低通滤波器，用于通过参考信号的参考电压的分量并消除不期望的高频分量，以及一个或多个输入第一级电路分别连接低通滤波器的输出和具有待确定逻辑电平的信号。在存储器件中，低通滤波器至少在工作时钟的频率上具有预定的衰减。

10. 发明授权

US07161820B2 Memory module and memory system having an expandable signal transmission, increased signal transmission and/or high capacity memory 有权
标题翻译：具有可扩展信号传输，增加的信号传输和/或高容量存储器的存储器模块和存储器系统
公开(公告)号：US07161820B2
公开(公告)日：2007-01-09
申请号：US10628517
申请日：2003-07-28
申请人： Seiji Funaba , Yoji Nishio , Kayoko Shibata
发明人： Seiji Funaba , Yoji Nishio , Kayoko Shibata
IPC分类号： G11C5/00 , G11C5/06
CPC分类号： G11C5/04 , G11C5/063 , G11C7/1048 , G11C11/4093 , G11C2207/105 , H01L2224/16225 , H01L2924/15192 , H01L2924/15311 , H01L2924/19107
摘要： A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.
摘要翻译：存储器模块具有在板的前表面和后表面上共享总线的多个DRAM（115）。总线通过通孔（113）从端子（111）连接到带状线（112）的一端，并且带状线的另一端通过通孔（113）连接到另一层中的带状线孔（119）用于使线路循环。设置在终端电压端子（VTT）附近的终端电阻器（120）通过通孔连接到另一层中的环形带状线。 DRAM端子通过通孔连接到带状线。该存储器模块通过连接器安装在其上提供存储器控制器的母板上。母线的有效特性阻抗与母板线路特性阻抗匹配。

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