专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08362614B2 Fine pitch grid array type semiconductor device 有权
标题翻译：细间距阵列型半导体器件
公开(公告)号：US08362614B2
公开(公告)日：2013-01-29
申请号：US11247215
申请日：2005-10-12
申请人： Mitsuaki Katagiri , Hiroya Shimizu , Fumiyuki Osanai , Yasushi Takahashi , Seiji Narui
发明人： Mitsuaki Katagiri , Hiroya Shimizu , Fumiyuki Osanai , Yasushi Takahashi , Seiji Narui
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/50 , H01L23/49838 , H01L2224/4824 , H01L2924/13091 , H01L2924/15173 , H01L2924/15311 , H01L2924/30107 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device has a semiconductor chip in which a plurality of semiconductor components and a plurality of pads are arranged, a plurality of external connection contacts arranged in grids, and a plurality of wires for electrically connecting the pads and the external connection contacts. The pads include a plurality of pad groups including a pair of electrode pads connected to the plurality of semiconductor components in common and a plurality of signal pads respectively connected to the semiconductor components connected to the electrode pads. In each pad group, each signal pad is arranged adjacently to one of the electrode pads; and each wire extending from each signal pad is extended along a wire extended from the electrode pad adjacent to each signal pad.
摘要翻译：半导体器件具有其中布置有多个半导体部件和多个焊盘的半导体芯片，布置在栅格中的多个外部连接触点，以及用于电连接焊盘和外部连接触点的多条引线。焊盘包括多个焊盘组，其包括连接到共同的多个半导体部件的一对电极焊盘和分别连接到连接到电极焊盘的半导体部件的多个信号焊盘。在每个焊盘组中，每个信号焊盘被布置成与电极焊盘之一相邻; 并且从每个信号焊盘延伸的每条焊丝沿着与每个信号焊盘相邻的电极焊盘延伸的焊丝延伸。

2. 发明申请

US20060081972A1 Fine pitch grid array type semiconductor device 有权
公开(公告)号：US20060081972A1
公开(公告)日：2006-04-20
申请号：US11247215
申请日：2005-10-12
申请人： Mitsuaki Katagiri , Hiroya Shimizu , Fumiyuki Osanai , Yasushi Takahashi , Seiji Narui
发明人： Mitsuaki Katagiri , Hiroya Shimizu , Fumiyuki Osanai , Yasushi Takahashi , Seiji Narui
IPC分类号： H01L23/48
CPC分类号： H01L23/50 , H01L23/49838 , H01L2224/4824 , H01L2924/13091 , H01L2924/15173 , H01L2924/15311 , H01L2924/30107 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device has a semiconductor chip in which a plurality of semiconductor components and a plurality of pads are arranged, a plurality of external connection contacts arranged in grids, and a plurality of wires for electrically connecting the pads and the external connection contacts. The pads include a plurality of pad groups including a pair of electrode pads connected to the plurality of semiconductor components in common and a plurality of signal pads respectively connected to the semiconductor components connected to the electrode pads. In each pad group, each signal pad is arranged adjacently to one of the electrode pads; and each wire extending from each signal pad is extended along a wire extended from the electrode pad adjacent to each signal pad.

3. 发明申请

US20080012107A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20080012107A1
公开(公告)日：2008-01-17
申请号：US11822265
申请日：2007-07-03
申请人： Satoshi Isa , Mitsuaki Katagiri , Kyoichi Nagata , Seiji Narui
发明人： Satoshi Isa , Mitsuaki Katagiri , Kyoichi Nagata , Seiji Narui
IPC分类号： H01L23/02
CPC分类号： H01L23/50 , H01L23/49838 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01033 , H01L2924/01056 , H01L2924/01082 , H01L2924/014 , H01L2924/12041 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： Disclosed is a semiconductor memory device in which pads on a chip which are wire-bonded to lands for solder-balls of a package, respectively, are arranged on first and second sides of the chip facing to each other and are disposed on a third side of the chip as well. Four sets of the pads for data signals are respectively disposed on four regions obtained by dividing the first and second sides into the four regions. Pads for command/address signals are arranged on the third side, thereby increasing layout space for bond fingers for the data signals and achieving uniformity in wiring for data signals.
摘要翻译：公开了一种半导体存储器件，其中芯片上的焊盘分别焊接到封装的焊球的焊盘上，所述焊盘分别布置在芯片的彼此面对的第一和第二侧上，并且设置在第三侧的芯片以及。四组用于数据信号的焊盘分别设置在通过将第一和第二侧划分成四个区域而获得的四个区域上。用于命令/地址信号的板被布置在第三侧上，从而增加了用于数据信号的接合点的布局空间，并实现了数据信号的布线的均匀性。

4. 发明授权

US07875986B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07875986B2
公开(公告)日：2011-01-25
申请号：US11822265
申请日：2007-07-03
申请人： Satoshi Isa , Mitsuaki Katagiri , Kyoichi Nagata , Seiji Narui
发明人： Satoshi Isa , Mitsuaki Katagiri , Kyoichi Nagata , Seiji Narui
IPC分类号： H01L29/40
CPC分类号： H01L23/50 , H01L23/49838 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01033 , H01L2924/01056 , H01L2924/01082 , H01L2924/014 , H01L2924/12041 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： Disclosed is a semiconductor memory device in which pads on a chip which are wire-bonded to lands for solder-balls of a package, respectively, are arranged on first and second sides of the chip facing to each other and are disposed on a third side of the chip as well. Four sets of the pads for data signals are respectively disposed on four regions obtained by dividing the first and second sides into the four regions. Pads for command/address signals are arranged on the third side, thereby increasing layout space for bond fingers for the data signals and achieving uniformity in wiring for data signals.
摘要翻译：公开了一种半导体存储器件，其中芯片上的焊盘分别焊接到封装的焊球的焊盘上，所述焊盘分别布置在芯片的彼此面对的第一和第二侧上，并且设置在第三侧的芯片以及。四组用于数据信号的焊盘分别设置在通过将第一和第二侧划分成四个区域而获得的四个区域上。用于命令/地址信号的板被布置在第三侧上，从而增加了用于数据信号的接合点的布局空间，并实现了数据信号的布线的均匀性。

5. 发明授权

US08508969B2 Semiconductor device having hierarchically structured bit lines and system including the same 有权
标题翻译：具有分层结构的位线的半导体器件和包括该位线的系统
公开(公告)号：US08508969B2
公开(公告)日：2013-08-13
申请号：US13533896
申请日：2012-06-26
申请人： Seiji Narui
发明人： Seiji Narui
IPC分类号： G11C5/06
CPC分类号： G11C11/401 , G11C5/025 , G11C5/06 , G11C8/18 , G11C11/4097
摘要： A device includes a first sense amplifier array including a plurality of first sense amplifiers arranged in a first direction, each of the first sense amplifiers including first and second nodes, a plurality of first global bit lines extending in a second direction crossing the first direction, the first global bit lines being arranged in the first direction on a left side of the first sense amplifier array so that the first global bit lines being operatively connected to the first node of an associated one of the first sense amplifiers, and a plurality of second global bit lines extending in the second direction, the second global bit lines being arranged in the first direction on a right side of the first sense amplifier array so that the second global bit lines being operatively connected to the second node of the associated one of the first sense amplifiers.
摘要翻译：一种器件包括：第一读出放大器阵列，包括以第一方向布置的多个第一读出放大器，每个第一读出放大器包括第一和第二节点;沿与第一方向交叉的第二方向延伸的多个第一全局位线; 所述第一全局位线沿所述第一方向布置在所述第一读出放大器阵列的左侧，使得所述第一全局位线可操作地连接到所述第一读出放大器中的相关联的第一读出放大器的第一节点，以及多个第二全局位线沿第二方向延伸，第二全局位线沿第一方向排列在第一读出放大器阵列的右侧，使得第二全局位线可操作地连接到相关联的一个的第二节点第一感测放大器。

6. 发明申请

US20120300529A1 SEMICONDUCTOR DEVICE HAVING HIERARCHICALLY STRUCTURED BIT LINES AND SYSTEM INCLUDING THE SAME 有权
标题翻译：具有层次结构的层次结构的半导体器件及其系统
公开(公告)号：US20120300529A1
公开(公告)日：2012-11-29
申请号：US13533896
申请日：2012-06-26
申请人： Seiji Narui
发明人： Seiji Narui
IPC分类号： G11C5/06
CPC分类号： G11C11/401 , G11C5/025 , G11C5/06 , G11C8/18 , G11C11/4097
摘要： A device includes a first sense amplifier array including a plurality of first sense amplifiers arranged in a first direction, each of the first sense amplifiers including first and second nodes, a plurality of first global bit lines extending in a second direction crossing the first direction, the first global bit lines being arranged in the first direction on a left side of the first sense amplifier array so that the first global bit lines being operatively connected to the first node of an associated one of the first sense amplifiers, and a plurality of second global bit lines extending in the second direction, the second global bit lines being arranged in the first direction on a right side of the first sense amplifier array so that the second global bit lines being operatively connected to the second node of the associated one of the first sense amplifiers.
摘要翻译：一种器件包括：第一读出放大器阵列，包括以第一方向布置的多个第一读出放大器，每个第一读出放大器包括第一和第二节点;沿与第一方向交叉的第二方向延伸的多个第一全局位线; 所述第一全局位线沿所述第一方向布置在所述第一读出放大器阵列的左侧，使得所述第一全局位线可操作地连接到所述第一读出放大器中的相关联的第一读出放大器的第一节点，以及多个第二全局位线沿第二方向延伸，第二全局位线沿第一方向排列在第一读出放大器阵列的右侧，使得第二全局位线可操作地连接到相关联的一个的第二节点第一感测放大器。

7. 发明授权

US07903489B2 Semiconductor device having a sense amplifier 有权
标题翻译：具有读出放大器的半导体器件
公开(公告)号：US07903489B2
公开(公告)日：2011-03-08
申请号：US11763772
申请日：2007-06-15
申请人： Takeshi Ohgami , Seiji Narui
发明人： Takeshi Ohgami , Seiji Narui
IPC分类号： G11C7/02
CPC分类号： H01L27/10897 , H01L27/0207
摘要： A semiconductor device in the present invention comprises pair transistors composed of a first transistor and a second transistor. The pair transistors are arrayed in a repeating pattern in the row direction. The first transistor and the second transistor are mutually related to each other so that the drain of one transistor is connected to the gate of the other transistor. The gate of the first transistor and the gate of the second transistor are offset in the row direction. The first transistor and the second transistor are in a diagonal positional relationship.
摘要翻译：本发明的半导体器件包括由第一晶体管和第二晶体管组成的对晶体管。该对晶体管以行方向排列成重复图案。第一晶体管和第二晶体管彼此相互关联，使得一个晶体管的漏极连接到另一个晶体管的栅极。第一晶体管的栅极和第二晶体管的栅极在行方向上偏移。第一晶体管和第二晶体管处于对角位置关系。

8. 发明申请

US20110026292A1 Semiconductor device having hierarchically structured bit lines and system including the same 有权
标题翻译：具有分层结构的位线的半导体器件和包括该位线的系统
公开(公告)号：US20110026292A1
公开(公告)日：2011-02-03
申请号：US12805015
申请日：2010-07-07
申请人： Seiji Narui
发明人： Seiji Narui
IPC分类号： G11C5/06
CPC分类号： G11C11/401 , G11C5/025 , G11C5/06 , G11C8/18 , G11C11/4097
摘要： To include memory mats each including a sense amplifier that amplifies a potential difference between global bit lines, a plurality of hierarchy switches connected to the global bit lines, and a plurality of local bit lines connected to the global bit lines via the hierarchy switches, and a control circuit that activates the hierarchy switches. The control circuit activates hierarchy switches that are located in the same distance from the sense amplifier along the global bit lines. According to the present invention, because there is no difference in the parasitic CR distributed constant regardless of a local bit line to be selected, it is possible to prevent the sensing sensitivity from being degraded.
摘要翻译：包括存储器垫，每个存储器堆包括放大全局位线之间的电位差的读出放大器，连接到全局位线的多个分层开关以及经由分层开关连接到全局位线的多个局部位线，以及激活层级交换机的控制电路。控制电路激活位于沿着全局位线与读出放大器相同距离的分层开关。根据本发明，由于无论选择的局部位线如何，寄生CR分布常数均无差异，可以防止感测灵敏度下降。

9. 发明申请

US20100164607A1 SEMICONDUCTOR DEVICE THAT CAN ADJUST SUBSTRATE VOLTAGE 有权
标题翻译：可调节基极电压的半导体器件
公开(公告)号：US20100164607A1
公开(公告)日：2010-07-01
申请号：US12647259
申请日：2009-12-24
申请人： Shinichi Miyatake , Seiji Narui , Hitoshi Tanaka
发明人： Shinichi Miyatake , Seiji Narui , Hitoshi Tanaka
IPC分类号： G05F1/10
CPC分类号： G05F3/205 , G05F1/46
摘要： To provide a semiconductor device including: a MOS transistor formed in a semiconductor substrate and have a threshold voltage to be adjusted, a replica transistor of the MOS transistor, a monitoring circuit monitors a gate/source voltage needed when the replica transistor flows a current having a given designed value, a negative voltage pumping circuit generates a substrate voltage of the MOS transistor, based on an output from the monitoring circuit, and a limiting circuit defines the operation of the negative voltage pumping circuit, regardless of a monitoring result of the monitoring circuit, in response to an excess of the substrate voltage with respect to a predetermined value.
摘要翻译：为了提供一种半导体器件，包括：形成在半导体衬底中并具有要调节的阈值电压的MOS晶体管，MOS晶体管的复制晶体管，监视电路监视当复制晶体管流过具有给定的设计值，负电压泵浦电路基于监控电路的输出产生MOS晶体管的衬底电压，并且限制电路定义负电压抽运电路的操作，而不管监视的监视结果如何电路，响应于相对于预定值的衬底电压的过量。

10. 发明申请

US20090034353A1 Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20090034353A1
公开(公告)日：2009-02-05
申请号：US12222105
申请日：2008-08-01
申请人： Seiji Narui , Takeshi Ohgami
发明人： Seiji Narui , Takeshi Ohgami
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C5/063
摘要： A semiconductor memory device includes multiple mats arranged in an array, each including multiple memory cells storing a charge as information, and multiple power-supply lines, one end of each line of the lines being connected in common to an internal power supply which decreases or increases a voltage which is supplied from an external power source. The power-supply lines extend in a given direction in an area in which the multiple mats are formed and the other end of each line of the multiple power-supply lines is connected in common on the edge mat.
摘要翻译：一种半导体存储器件包括多个阵列排列的阵列，每个阵列包括存储电荷作为信息的多个存储单元和多个电源线，每条线的一端共同连接到内部电源，增加从外部电源供给的电压。电源线在形成多个垫的区域中沿给定的方向延伸，并且多个电源线的每条线的另一端在边缘垫上共同连接。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式