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1. 发明授权

US07903489B2 Semiconductor device having a sense amplifier 有权
标题翻译：具有读出放大器的半导体器件
公开(公告)号：US07903489B2
公开(公告)日：2011-03-08
申请号：US11763772
申请日：2007-06-15
申请人： Takeshi Ohgami , Seiji Narui
发明人： Takeshi Ohgami , Seiji Narui
IPC分类号： G11C7/02
CPC分类号： H01L27/10897 , H01L27/0207
摘要： A semiconductor device in the present invention comprises pair transistors composed of a first transistor and a second transistor. The pair transistors are arrayed in a repeating pattern in the row direction. The first transistor and the second transistor are mutually related to each other so that the drain of one transistor is connected to the gate of the other transistor. The gate of the first transistor and the gate of the second transistor are offset in the row direction. The first transistor and the second transistor are in a diagonal positional relationship.
摘要翻译：本发明的半导体器件包括由第一晶体管和第二晶体管组成的对晶体管。该对晶体管以行方向排列成重复图案。第一晶体管和第二晶体管彼此相互关联，使得一个晶体管的漏极连接到另一个晶体管的栅极。第一晶体管的栅极和第二晶体管的栅极在行方向上偏移。第一晶体管和第二晶体管处于对角位置关系。

2. 发明申请

US20090034353A1 Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20090034353A1
公开(公告)日：2009-02-05
申请号：US12222105
申请日：2008-08-01
申请人： Seiji Narui , Takeshi Ohgami
发明人： Seiji Narui , Takeshi Ohgami
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C5/063
摘要： A semiconductor memory device includes multiple mats arranged in an array, each including multiple memory cells storing a charge as information, and multiple power-supply lines, one end of each line of the lines being connected in common to an internal power supply which decreases or increases a voltage which is supplied from an external power source. The power-supply lines extend in a given direction in an area in which the multiple mats are formed and the other end of each line of the multiple power-supply lines is connected in common on the edge mat.
摘要翻译：一种半导体存储器件包括多个阵列排列的阵列，每个阵列包括存储电荷作为信息的多个存储单元和多个电源线，每条线的一端共同连接到内部电源，增加从外部电源供给的电压。电源线在形成多个垫的区域中沿给定的方向延伸，并且多个电源线的每条线的另一端在边缘垫上共同连接。

3. 发明申请

US20110292717A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20110292717A1
公开(公告)日：2011-12-01
申请号：US13067193
申请日：2011-05-16
申请人： Takeshi Ohgami
发明人： Takeshi Ohgami
IPC分类号： G11C11/24 , H01L27/108
CPC分类号： H01L27/10814 , G11C7/02 , G11C11/404 , G11C11/4074 , H01L27/105 , H01L27/10855 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L27/10897 , H01L28/90
摘要： A semiconductor device may include, but is not limited to: a first memory cell; a first line; a second line; and a first capacitor. The first line is coupled to the first memory cell. The first line supplies a first voltage to the first memory cell. The second line is supplied with a fixed voltage. The first capacitor is coupled between the first and second lines.
摘要翻译：半导体器件可以包括但不限于：第一存储器单元; 第一行第二行和第一电容器。第一行耦合到第一个存储单元。第一行向第一存储单元提供第一电压。第二行提供固定电压。第一电容器耦合在第一和第二线之间。

4. 发明授权

US07768855B2 Semiconductor memory device and sense amplifier 有权
标题翻译：半导体存储器件和读出放大器
公开(公告)号：US07768855B2
公开(公告)日：2010-08-03
申请号：US12506631
申请日：2009-07-21
申请人： Takeshi Ohgami
发明人： Takeshi Ohgami
IPC分类号： G11C7/00
CPC分类号： G11C11/4091 , G11C11/4094 , G11C11/412 , G11C11/413 , H01L27/10897
摘要： In a sense amplifier circuit having a plurality of sense amplifier portions arranged in order, each of the sense amplifier portions includes a transistor that supplies a bit line potential to a bit line pair in a corresponding column of a memory cell array and a gate electrode for supplying a precharge signal to a gate of the transistor. The gate electrode of the plurality of sense amplifier portions is provided as one piece as a whole and extends in a direction parallel to a row direction in the memory cell array. A gate electrode portion which is a connected portion between the gate electrode in a k-th sense amplifier portion and the gate electrode in a (k+1)-th sense amplifier portion is ring-shaped, where k is an odd number.
摘要翻译：在具有顺序布置的多个读出放大器部分的读出放大器电路中，每个读出放大器部分包括一个晶体管，其将位线电位提供给存储单元阵列的相应列中的位线对和用于向晶体管的栅极提供预充电信号。多个读出放大器部分的栅电极作为整体设置为一体，并且在与存储单元阵列中的行方向平行的方向上延伸。作为第k读出放大器部分中的栅电极与第（k + 1）读出放大器部分中的栅电极之间的连接部分的栅电极部分是环形的，其中k是奇数。

5. 发明授权

US08130546B2 Semiconductor memory device and manufacturing method of semiconductor memory device 有权
标题翻译：半导体存储器件及半导体存储器件的制造方法
公开(公告)号：US08130546B2
公开(公告)日：2012-03-06
申请号：US12696627
申请日：2010-01-29
申请人： Takeshi Ohgami
发明人： Takeshi Ohgami
IPC分类号： G11C16/04
CPC分类号： H01L27/0207 , G11C5/063 , H01L27/10882 , H01L27/10891 , H01L27/10894 , H01L27/10897
摘要： A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed.
摘要翻译：通过使用选择性蚀刻绝缘层的SAC线技术，形成要连接到构成驱动子字线的子字线驱动器的晶体管的漏极区域或源极区域的多个接触插塞，通过使用设置在要形成每个晶体管的接触插塞的部分的线形开口的掩模覆盖每个晶体管。

6. 发明授权

US06775198B2 Semiconductor storage unit 失效
标题翻译：半导体存储单元
公开(公告)号：US06775198B2
公开(公告)日：2004-08-10
申请号：US10253512
申请日：2002-09-25
申请人： Kozo Ishida , Hideki Yonetani , Takeshi Ohgami
发明人： Kozo Ishida , Hideki Yonetani , Takeshi Ohgami
IPC分类号： G11C700
CPC分类号： G11C5/14
摘要： Power to operates memory bank of DRAM stably is supplied with reduced power consumption. A semiconductor storage unit includes multiple arrays forming memory banks on a substrate, first and second power supplies. Multiple arrays are arranged like a matrix and surround the central region of the substrate. Each memory bank consists of two of the multiple arrays. Each first power supply supplies driving power to a peripheral circuit which drives each multiple array. Second power supplies are arranged at four corners of the central region, each supply provides access power to word lines which access the multiple arrays. The first power supplies are mounted to a central and the opposite side for predetermined arrays, serve as a main and an auxiliary power supply to provide main and auxiliary power (smaller than the main power), and provide distantly arranged two of the multiple arrays forming a memory bank with power.
摘要翻译：稳定地操作DRAM的存储体的功率被提供降低的功耗。半导体存储单元包括在基板上形成存储体的多个阵列，第一和第二电源。多个阵列被布置成像矩阵并且围绕衬底的中心区域。每个存储体由多个阵列中的两个组成。每个第一电源为驱动每个多阵列的外围电路提供驱动电力。第二电源设置在中央区域的四个角处，每个电源为访问多个阵列的字线提供访问电力。第一电源被安装到中央和相对侧用于预定的阵列，用作主电源和辅助电源，以提供主功率和辅助功率（小于主功率），并且提供形成的多个阵列中的远距离布置的两个一个有权力的记忆库。

7. 发明授权

US08477536B2 Method for manufacturing a semiconductor memory device 有权
标题翻译：半导体存储器件的制造方法
公开(公告)号：US08477536B2
公开(公告)日：2013-07-02
申请号：US13570716
申请日：2012-08-09
申请人： Takeshi Ohgami
发明人： Takeshi Ohgami
IPC分类号： G11C16/04
CPC分类号： H01L27/0207 , G11C5/063 , H01L27/10882 , H01L27/10891 , H01L27/10894 , H01L27/10897
摘要： A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed.
摘要翻译：通过使用选择性蚀刻绝缘层的SAC线技术，形成要连接到构成驱动子字线的子字线驱动器的晶体管的漏极区域或源极区域的多个接触插塞，通过使用设置在要形成每个晶体管的接触插塞的部分的线形开口的掩模覆盖每个晶体管。

8. 发明授权

US08797778B2 Semiconductor memory device having open bit line structure 有权
标题翻译：具有开放位线结构的半导体存储器件
公开(公告)号：US08797778B2
公开(公告)日：2014-08-05
申请号：US12646579
申请日：2009-12-23
申请人： Takeshi Ohgami
发明人： Takeshi Ohgami
IPC分类号： G11C5/06
CPC分类号： G11C11/4091 , G11C5/025 , G11C7/1045 , G11C7/14 , G11C7/18 , G11C11/4085 , G11C11/4097 , G11C11/4099
摘要： A semiconductor memory device has an array structure of an open bit line structure and comprises a plurality of normal memory mats, two dummy mats and a plurality of rows of sense amplifiers. The normal memory mat includes a plurality of memory cells and arranged in a bit line extending direction, while the dummy mat includes a plurality of dummy cells and arranged in a bit line extending direction at both ends of the plurality of normal memory mats. The rows of sense amplifiers are arranged between the normal memory mats and between each of the normal memory mats and each of the dummy mats. A first predetermined number of the dummy cells, the number of which is smaller than a number of the memory cells arranged along each bit line of the normal memory mats, are arranged along each bit line of the dummy mats.
摘要翻译：半导体存储器件具有开放位线结构的阵列结构，并且包括多个正常存储器垫，两个哑垫和多行读出放大器。正常存储器垫包括多个存储单元并且以位线延伸方向布置，而虚拟垫包括多个虚设单元并且布置在多个正常存储垫的两端的位线延伸方向上。读出放大器的行布置在正常存储器垫之间以及每个正常存储器垫和每个虚拟垫之间。沿着虚拟垫的每个位线布置第一预定数量的虚拟单元，其数量小于沿着常规存储器垫的每个位线布置的存储单元的数量。

9. 发明授权

US08508982B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08508982B2
公开(公告)日：2013-08-13
申请号：US13067193
申请日：2011-05-16
申请人： Takeshi Ohgami
发明人： Takeshi Ohgami
IPC分类号： G11C11/24
CPC分类号： H01L27/10814 , G11C7/02 , G11C11/404 , G11C11/4074 , H01L27/105 , H01L27/10855 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L27/10897 , H01L28/90
摘要： A semiconductor device includes a first memory cell, a first line, a second line and a first capacitor. The first line is coupled to the first memory cell. The first line supplies a first voltage to the first memory cell. The second line is supplied with a fixed voltage. The first capacitor is coupled between the first and second lines.
摘要翻译：半导体器件包括第一存储单元，第一线，第二线和第一电容器。第一行耦合到第一个存储单元。第一行向第一存储单元提供第一电压。第二行提供固定电压。第一电容器耦合在第一和第二线之间。

10. 发明授权

US08259496B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08259496B2
公开(公告)日：2012-09-04
申请号：US13358928
申请日：2012-01-26
申请人： Takeshi Ohgami
发明人： Takeshi Ohgami
IPC分类号： G11C16/04
CPC分类号： H01L27/0207 , G11C5/063 , H01L27/10882 , H01L27/10891 , H01L27/10894 , H01L27/10897
摘要： A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed.
摘要翻译：通过使用选择性蚀刻绝缘层的SAC线技术，形成要连接到构成驱动子字线的子字线驱动器的晶体管的漏极区域或源极区域的多个接触插塞，通过使用设置在要形成每个晶体管的接触插塞的部分的线形开口的掩模覆盖每个晶体管。

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