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1. 发明授权

US07872910B2 Non-volatile semiconductor storage system 有权
标题翻译：非易失性半导体存储系统
公开(公告)号：US07872910B2
公开(公告)日：2011-01-18
申请号：US12397369
申请日：2009-03-04
申请人： Mitsuaki Honma , Noboru Shibata , Hironori Uchikawa
发明人： Mitsuaki Honma , Noboru Shibata , Hironori Uchikawa
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G06F11/1072 , G11C2211/5646
摘要： In a memory cell array, memory cells enabled to store plural-bit data are arranged in matrix. The bit-line control circuit is connected to bit-lines to control the bit-lines. A word line control circuit applies a plural-bit data read voltage as a word line voltage to the word line. The plural-bit data read voltage is larger than an upper limit of one of plural threshold voltage distributions and smaller than a lower limit of another threshold voltage distribution. Furthermore, it applies a soft-value read voltage as a word line voltage to the word line. The soft-value read voltage is smaller than an upper limit of a threshold voltage distribution and larger than a lower limit thereof. The likelihood calculation circuit calculates likelihood of the plural-bit data stores in the memory cells based on the soft-value.
摘要翻译：在存储单元阵列中，能够存储多位数据的存储单元被排列成矩阵。位线控制电路连接到位线以控制位线。字线控制电路将多位数据读取电压作为字线电压施加到字线。多位数据读取电压大于多个阈值电压分布中的一个的上限，并且小于另一个阈值电压分布的下限。此外，它将软值读取电压作为字线电压施加到字线。软值读取电压小于阈值电压分布的上限并且大于其下限。似然度计算电路基于软值来计算存储单元中的多位数据存储的可能性。

2. 发明授权

US07508704B2 Non-volatile semiconductor storage system 有权
标题翻译：非易失性半导体存储系统
公开(公告)号：US07508704B2
公开(公告)日：2009-03-24
申请号：US11772563
申请日：2007-07-02
申请人： Mitsuaki Honma , Noboru Shibata , Hironori Uchikawa
发明人： Mitsuaki Honma , Noboru Shibata , Hironori Uchikawa
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G06F11/1072 , G11C2211/5646
摘要： In a memory cell array, memory cells enabled to store plural-bit data are arranged in matrix. The bit-line control circuit is connected to bit-lines to control the bit-lines. A word line control circuit applies a plural-bit data read voltage as a word line voltage to the word line. The plural-bit data read voltage is larger than an upper limit of one of plural threshold voltage distributions and smaller than a lower limit of another threshold voltage distribution. Furthermore, it applies a soft-value read voltage as a word line voltage to the word line. The soft-value read voltage is smaller than an upper limit of a threshold voltage distribution and larger than a lower limit thereof. The likelihood calculation circuit calculates likelihood of the plural-bit data stores in the memory cells based on the soft-value.
摘要翻译：在存储单元阵列中，能够存储多位数据的存储单元被排列成矩阵。位线控制电路连接到位线以控制位线。字线控制电路将多位数据读取电压作为字线电压施加到字线。多位数据读取电压大于多个阈值电压分布中的一个的上限，并且小于另一个阈值电压分布的下限。此外，它将软值读取电压作为字线电压施加到字线。软值读取电压小于阈值电压分布的上限并且大于其下限。似然度计算电路基于软值来计算存储单元中的多位数据存储的可能性。

3. 发明申请

US20080123408A1 NON-VOLATILE SEMICONDUCTOR STORAGE SYSTEM 有权
标题翻译：非挥发性半导体存储系统
公开(公告)号：US20080123408A1
公开(公告)日：2008-05-29
申请号：US11772563
申请日：2007-07-02
申请人： Mitsuaki Honma , Noboru Shibata , Hironori Uchikawa
发明人： Mitsuaki Honma , Noboru Shibata , Hironori Uchikawa
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G06F11/1072 , G11C2211/5646
摘要： In a memory cell array, memory cells enabled to store plural-bit data are arranged in matrix. The bit-line control circuit is connected to bit-lines to control the bit-lines. A word line control circuit applies a plural-bit data read voltage as a word line voltage to the word line. The plural-bit data read voltage is larger than an upper limit of one of plural threshold voltage distributions and smaller than a lower limit of another threshold voltage distribution. Furthermore, it applies a soft-value read voltage as a word line voltage to the word line. The soft-value read voltage is smaller than an upper limit of a threshold voltage distribution and larger than a lower limit thereof. The likelihood calculation circuit calculates likelihood of the plural-bit data stores in the memory cells based on the soft-value.
摘要翻译：在存储单元阵列中，能够存储多位数据的存储单元被排列成矩阵。位线控制电路连接到位线以控制位线。字线控制电路将多位数据读取电压作为字线电压施加到字线。多位数据读取电压大于多个阈值电压分布中的一个的上限，并且小于另一个阈值电压分布的下限。此外，它将软值读取电压作为字线电压施加到字线。软值读取电压小于阈值电压分布的上限并且大于其下限。似然度计算电路基于软值来计算存储单元中的多位数据存储的可能性。

4. 发明申请

US20080301532A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20080301532A1
公开(公告)日：2008-12-04
申请号：US11860015
申请日：2007-09-24
申请人： Hironori UCHIKAWA , Tatsuyuki Ishikawa , Mitsuaki Honma
发明人： Hironori UCHIKAWA , Tatsuyuki Ishikawa , Mitsuaki Honma
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G11C29/52 , G06F11/1072 , G11C16/04 , G11C16/0483 , G11C29/00 , G11C2029/0411 , G11C2211/5641 , G11C2211/5643
摘要： A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information of N bits (N≧2) in accordance with variations in threshold voltage. A parity data adder circuit adds parity data for error correction to every certain data bits to be stored in the memory cell array. A frame converter circuit uniformly divides frame data containing the data bits and the parity data into N pieces of subframe data. A programming circuit stores the subframe data divided into N pieces in respective N sub-pages formed corresponding to the information of N bits.
摘要翻译：非易失性半导体存储器件包括存储单元阵列，该存储单元阵列包括能够根据阈值电压的变化存储N位（N> = 2）的信息而排列的多个存储单元。奇偶校验数据加法器电路将用于纠错的奇偶校验数据添加到要存储在存储单元阵列中的每个特定数据位。帧转换器电路将包含数据位和奇偶校验数据的帧数据均匀地分割成N个子帧数据。编程电路将分割成N个的子帧数据存储在对应于N位信息的N个子页中。

5. 发明申请

US20080104459A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20080104459A1
公开(公告)日：2008-05-01
申请号：US11877287
申请日：2007-10-23
申请人： Hironori Uchikawa , Tatsuyuki Ishikawa , Mitsuaki Honma
发明人： Hironori Uchikawa , Tatsuyuki Ishikawa , Mitsuaki Honma
IPC分类号： G06F11/26
CPC分类号： G06F11/1068 , G11C2029/0411
摘要： A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information in accordance with variations in threshold voltage. A likelihood calculator has a plurality of likelihood calculation algorithms for deriving a likelihood value about a stored data bit from a threshold value read out of the memory cell. An error correction unit executes error correction through iterative processing using the likelihood value obtained at the likelihood calculator. A likelihood calculator controller changes among the likelihood calculation algorithms in the likelihood calculator based on a certain value of the number of iterations in the iterative processing obtained from the error correction unit.
摘要翻译：非易失性半导体存储器件包括存储单元阵列，该存储单元阵列包括能够根据阈值电压的变化存储信息的多个存储单元。似然度计算器具有多个似然计算算法，用于从从存储单元读出的阈值中导出关于存储的数据位的似然值。错误校正单元通过使用在似然度计算器获得的似然值的迭代处理执行纠错。似然度计算器控制器根据从误差校正单元获得的迭代处理中的迭代次数的一定值，在似然度计算器中的似然计算算法中进行变化。

6. 发明授权

US08136014B2 Non-volatile semiconductor memory device 有权
公开(公告)号：US08136014B2
公开(公告)日：2012-03-13
申请号：US11860015
申请日：2007-09-24
申请人： Hironori Uchikawa , Tatsuyuki Ishikawa , Mitsuaki Honma
发明人： Hironori Uchikawa , Tatsuyuki Ishikawa , Mitsuaki Honma
IPC分类号： G11C29/00
CPC分类号： G11C29/52 , G06F11/1072 , G11C16/04 , G11C16/0483 , G11C29/00 , G11C2029/0411 , G11C2211/5641 , G11C2211/5643
摘要： A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information of N bits (N≧2) in accordance with variations in threshold voltage. A parity data adder circuit adds parity data for error correction to every certain data bits to be stored in the memory cell array. A frame converter circuit uniformly divides frame data containing the data bits and the parity data into N pieces of subframe data. A programming circuit stores the subframe data divided into N pieces in respective N sub-pages formed corresponding to the information of N bits.

7. 发明申请

US20080055990A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND NON-VOLATILE STORAGE SYSTEM 有权
标题翻译：非易失性半导体存储器件和非易失性存储系统
公开(公告)号：US20080055990A1
公开(公告)日：2008-03-06
申请号：US11839222
申请日：2007-08-15
申请人： Tatsuyuki Ishikawa , Mitsuaki Honma , Hironori Uchikawa
发明人： Tatsuyuki Ishikawa , Mitsuaki Honma , Hironori Uchikawa
IPC分类号： G11C11/34
CPC分类号： G11C11/5642 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3431 , G11C29/00
摘要： This memory device comprises a word-line control circuit applying a read voltage and a soft-value read voltage as a word line voltage to a word line to generate soft-values. The soft-value read voltage is between an upper limit and a lower limit of each of plural threshold voltage distributions. A likelihood calculation circuit calculates a likelihood value of data stored in a memory cell based on the soft-value. An error correction circuit executes data error correction for the data read from the memory cell based on the likelihood value. A refresh control circuit controls a timing of a refresh operation for the memory cell based on the soft-value or the likelihood value.
摘要翻译：该存储装置包括将读取电压和软值读取电压作为字线电压施加到字线以产生软值的字线控制电路。软值读取电压在多个阈值电压分布中的上限和下限之间。似然度计算电路基于软值来计算存储在存储单元中的数据的似然值。误差校正电路根据似然值对存储单元读出的数据进行数据纠错。刷新控制电路基于软值或似然值来控制存储单元的刷新操作的定时。

8. 发明授权

US08332726B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08332726B2
公开(公告)日：2012-12-11
申请号：US13310003
申请日：2011-12-02
申请人： Hironori Uchikawa , Tatsuyuki Ishikawa , Mitsuaki Honma
发明人： Hironori Uchikawa , Tatsuyuki Ishikawa , Mitsuaki Honma
IPC分类号： G11C29/00
CPC分类号： G06F11/1068 , G11C2029/0411
摘要： A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information in accordance with variations in threshold voltage. A likelihood calculator has a plurality of likelihood calculation algorithms for deriving a likelihood value about a stored data bit from a threshold value read out of the memory cell. An error correction unit executes error correction through iterative processing using the likelihood value obtained at the likelihood calculator. A likelihood calculator controller changes among the likelihood calculation algorithms in the likelihood calculator based on a certain value of the number of iterations in the iterative processing obtained from the error correction unit.
摘要翻译：非易失性半导体存储器件包括存储单元阵列，该存储单元阵列包括能够根据阈值电压的变化存储信息的多个存储单元。似然度计算器具有多个似然计算算法，用于从从存储单元读出的阈值中导出关于存储的数据位的似然值。错误校正单元通过使用在似然度计算器获得的似然值的迭代处理执行纠错。似然度计算器控制器根据从误差校正单元获得的迭代处理中的迭代次数的一定值，在似然度计算器中的似然计算算法中进行变化。

9. 发明授权

US08078940B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08078940B2
公开(公告)日：2011-12-13
申请号：US11877287
申请日：2007-10-23
申请人： Hironori Uchikawa , Tatsuyuki Ishikawa , Mitsuaki Honma
发明人： Hironori Uchikawa , Tatsuyuki Ishikawa , Mitsuaki Honma
IPC分类号： G11C29/00
CPC分类号： G06F11/1068 , G11C2029/0411
摘要： A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information in accordance with variations in threshold voltage. A likelihood calculator has a plurality of likelihood calculation algorithms for deriving a likelihood value about a stored data bit from a threshold value read out of the memory cell. An error correction unit executes error correction through iterative processing using the likelihood value obtained at the likelihood calculator. A likelihood calculator controller changes among the likelihood calculation algorithms in the likelihood calculator based on a certain value of the number of iterations in the iterative processing obtained from the error correction unit.
摘要翻译：非易失性半导体存储器件包括存储单元阵列，该存储单元阵列包括能够根据阈值电压的变化存储信息的多个存储单元。似然度计算器具有多个似然计算算法，用于从从存储单元读出的阈值中导出关于存储的数据位的似然值。错误校正单元通过使用在似然度计算器获得的似然值的迭代处理执行纠错。似然度计算器控制器根据从误差校正单元获得的迭代处理中的迭代次数的一定值，在似然度计算器中的似然计算算法中进行变化。

10. 发明授权

US08239730B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08239730B2
公开(公告)日：2012-08-07
申请号：US13372095
申请日：2012-02-13
申请人： Hironori Uchikawa , Tatsuyuki Ishikawa , Mitsuaki Honma
发明人： Hironori Uchikawa , Tatsuyuki Ishikawa , Mitsuaki Honma
IPC分类号： G11C29/00
CPC分类号： G11C29/52 , G06F11/1072 , G11C16/04 , G11C16/0483 , G11C29/00 , G11C2029/0411 , G11C2211/5641 , G11C2211/5643
摘要： A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information of N bits (N≧2) in accordance with variations in threshold voltage. A parity data adder circuit adds parity data for error correction to every certain data bits to be stored in the memory cell array. A frame converter circuit uniformly divides frame data containing the data bits and the parity data into N pieces of subframe data. A programming circuit stores the subframe data divided into N pieces in respective N sub-pages formed corresponding to the information of N bits.
摘要翻译：非易失性半导体存储器件包括存储单元阵列，该存储单元阵列包括能够根据阈值电压的变化存储N位（N≥2）的信息的多个存储单元。奇偶校验数据加法器电路将用于纠错的奇偶校验数据添加到要存储在存储单元阵列中的每个特定数据位。帧转换器电路将包含数据位和奇偶校验数据的帧数据均匀地分割成N个子帧数据。编程电路将分割成N个的子帧数据存储在对应于N位信息的N个子页中。

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