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1. 发明申请

US20120144273A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120144273A1
公开(公告)日：2012-06-07
申请号：US13372095
申请日：2012-02-13
申请人： Hironori UCHIKAWA , Tatsuyuki Ishikawa , Mitsuaki Honma
发明人： Hironori UCHIKAWA , Tatsuyuki Ishikawa , Mitsuaki Honma
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G11C29/52 , G06F11/1072 , G11C16/04 , G11C16/0483 , G11C29/00 , G11C2029/0411 , G11C2211/5641 , G11C2211/5643
摘要： A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information of N bits (N≧2) in accordance with variations in threshold voltage. A parity data adder circuit adds parity data for error correction to every certain data bits to be stored in the memory cell array. A frame converter circuit uniformly divides frame data containing the data bits and the parity data into N pieces of subframe data. A programming circuit stores the subframe data divided into N pieces in respective N sub-pages formed corresponding to the information of N bits.
摘要翻译：非易失性半导体存储器件包括存储单元阵列，该存储单元阵列包括能够根据阈值电压的变化存储N位（N≥2）的信息的多个存储单元。奇偶校验数据加法器电路将用于纠错的奇偶校验数据添加到要存储在存储单元阵列中的每个特定数据位。帧转换器电路将包含数据位和奇偶校验数据的帧数据均匀地分割成N个子帧数据。编程电路将分割成N个的子帧数据存储在对应于N位信息的N个子页中。

2. 发明申请

US20080301532A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20080301532A1
公开(公告)日：2008-12-04
申请号：US11860015
申请日：2007-09-24
申请人： Hironori UCHIKAWA , Tatsuyuki Ishikawa , Mitsuaki Honma
发明人： Hironori UCHIKAWA , Tatsuyuki Ishikawa , Mitsuaki Honma
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G11C29/52 , G06F11/1072 , G11C16/04 , G11C16/0483 , G11C29/00 , G11C2029/0411 , G11C2211/5641 , G11C2211/5643
摘要： A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information of N bits (N≧2) in accordance with variations in threshold voltage. A parity data adder circuit adds parity data for error correction to every certain data bits to be stored in the memory cell array. A frame converter circuit uniformly divides frame data containing the data bits and the parity data into N pieces of subframe data. A programming circuit stores the subframe data divided into N pieces in respective N sub-pages formed corresponding to the information of N bits.
摘要翻译：非易失性半导体存储器件包括存储单元阵列，该存储单元阵列包括能够根据阈值电压的变化存储N位（N> = 2）的信息而排列的多个存储单元。奇偶校验数据加法器电路将用于纠错的奇偶校验数据添加到要存储在存储单元阵列中的每个特定数据位。帧转换器电路将包含数据位和奇偶校验数据的帧数据均匀地分割成N个子帧数据。编程电路将分割成N个的子帧数据存储在对应于N位信息的N个子页中。

3. 发明申请

US20120079354A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120079354A1
公开(公告)日：2012-03-29
申请号：US13310003
申请日：2011-12-02
申请人： Hironori UCHIKAWA , Tatsuyuki ISHIKAWA , Mitsuaki HONMA
发明人： Hironori UCHIKAWA , Tatsuyuki ISHIKAWA , Mitsuaki HONMA
IPC分类号： G06F11/00
CPC分类号： G06F11/1068 , G11C2029/0411
摘要： A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information in accordance with variations in threshold voltage. A likelihood calculator has a plurality of likelihood calculation algorithms for deriving a likelihood value about a stored data bit from a threshold value read out of the memory cell. An error correction unit executes error correction through iterative processing using the likelihood value obtained at the likelihood calculator. A likelihood calculator controller changes among the likelihood calculation algorithms in the likelihood calculator based on a certain value of the number of iterations in the iterative processing obtained from the error correction unit.
摘要翻译：非易失性半导体存储器件包括存储单元阵列，该存储单元阵列包括能够根据阈值电压的变化存储信息的多个存储单元。似然度计算器具有多个似然计算算法，用于从从存储单元读出的阈值中导出关于存储的数据位的似然值。错误校正单元通过使用在似然度计算器获得的似然值的迭代处理执行纠错。似然度计算器控制器根据从误差校正单元获得的迭代处理中的迭代次数的一定值，在似然度计算器中的似然计算算法中进行变化。

4. 发明申请

US20130111292A1 SEMICONDUCTOR MEMORY DEVICE AND DECODING METHOD 有权
标题翻译：半导体存储器件和解码方法
公开(公告)号：US20130111292A1
公开(公告)日：2013-05-02
申请号：US13569492
申请日：2012-08-08
申请人： Haruka OBATA , Tatsuyuki ISHIKAWA , Hironori UCHIKAWA , Kenji SAKURADA
发明人： Haruka OBATA , Tatsuyuki ISHIKAWA , Hironori UCHIKAWA , Kenji SAKURADA
IPC分类号： H03M13/05
CPC分类号： H03M13/112 , H03M13/1128 , H03M13/6583
摘要： A semiconductor memory device includes a semiconductor memory unit which stores LDPC encoded data, and a decoding unit which decodes the encoded data, wherein the decoding unit performs serial decoding using the posterior likelihood ratio as it is for a column element likelihood ratio when the absolute value of the posterior likelihood ratio is not smaller than a threshold and using the column element likelihood ratio as it is for the posterior likelihood ratio when the absolute value of the column element likelihood ratio is not smaller than the threshold, and if the decoding does not succeed even after a predetermined first cycle count of iterative processing is performed or if the number of syndrome errors becomes smaller than a predetermined first syndrome error count, the decoding unit shrinks the absolute values of at least some of posterior likelihood ratios and resets all prior likelihood ratios to “0.”
摘要翻译：半导体存储器件包括存储LDPC编码数据的半导体存储器单元和对编码数据进行解码的解码单元，其中，当绝对值为0时，解码单元使用后验似然比原理进行串行解码，作为列元素似然比的后验似率比不小于阈值，并且当列元素似然比的绝对值不小于阈值时，使用列元素似然比作为后验似然比，并且如果解码不成功即使在执行了预定的第一循环计数的迭代处理之后，或者如果校正子错误的数量变得小于预定的第一校正子错误计数，则解码单元收缩至少一些后验似然比的绝对值并且重置所有先验似然比到“0”

5. 发明申请

US20110239080A1 ERROR DETECTION/CORRECTION CIRCUIT, MEMORY CONTROLLER AND SEMICONDUCTOR MEMORY APPARATUS 失效
标题翻译：错误检测/校正电路，存储器控制器和半导体存储器
公开(公告)号：US20110239080A1
公开(公告)日：2011-09-29
申请号：US13039961
申请日：2011-03-03
申请人： Kenji SAKAUE , Tatsuyuki ISHIKAWA , Yukio ISHIKAWA , Kazuhiro ICHIKAWA , Hironori UCHIKAWA
发明人： Kenji SAKAUE , Tatsuyuki ISHIKAWA , Yukio ISHIKAWA , Kazuhiro ICHIKAWA , Hironori UCHIKAWA
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1048 , H03M13/1117 , H03M13/1137 , H03M13/116 , H03M13/1188
摘要： An LDPC error detection/correction circuit according to an embodiment includes a selector that divides data into p groups based on a check matrix H including blocks made up of unit matrixes having a size p and shift blocks, a selector that divides a group into Y subgroups, a bit node storage section that stores LMEM variables to calculate a probability β in association with each first address, a check node storage section that stores TMEM variables to calculate an external value α in association with each second address, a rotator that performs rotation processing on the TMEM with a rotation value based on a shift value, and an operation circuit made up of (p/Y) operation units that perform parallel processing in subgroup units.
摘要翻译：根据实施例的LDPC错误检测/校正电路包括：选择器，其基于包括具有大小为p和移位块的单位矩阵组成的块的校验矩阵H将数据划分为p组;选择器，将组划分成Y个子组，存储LMEM变量以计算概率＆bgr的位节点存储部分; 与每个第一地址相关联的校验节点存储部分，其存储TMEM变量以计算与每个第二地址相关联的外部值α;旋转器，其基于移位值以旋转值对TMEM进行旋转处理;以及（p / Y）操作单元组成的运行电路，以子组为单位执行并行处理。

6. 发明申请

US20190259458A1 SEMICONDUCTOR MEMORY 审中-公开
公开(公告)号：US20190259458A1
公开(公告)日：2019-08-22
申请号：US16123162
申请日：2018-09-06
申请人： Noboru SHIBATA , Hironori UCHIKAWA
发明人： Noboru SHIBATA , Hironori UCHIKAWA
IPC分类号： G11C16/26 , H01L27/11582 , H01L27/1157 , G11C7/08 , G11C8/14 , G11C16/08 , G11C16/10 , G11C16/04
摘要： According to one embodiment, a semiconductor memory includes a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells. Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.

7. 发明申请

US20130151921A1 ENCODING APPARATUS, ENCODING METHOD AND SEMICONDUCTOR MEMORY SYSTEM 有权
标题翻译：编码设备，编码方法和半导体存储器系统
公开(公告)号：US20130151921A1
公开(公告)日：2013-06-13
申请号：US13706663
申请日：2012-12-06
申请人： Hironori UCHIKAWA , Haruka OBATA
发明人： Hironori UCHIKAWA , Haruka OBATA
IPC分类号： H03M13/13
CPC分类号： H03M13/13 , H03M13/116 , H03M13/118 , H03M13/611
摘要： According to one embodiment, an encoding apparatus includes an input unit and a generation unit. The input unit inputs a data symbol sequence containing q(N−J) symbols (q, J, and N are integers, N>J). The generation unit generates a codeword containing qN symbols by adding a parity symbol sequence containing qJ symbols to the data symbol sequence. The codeword satisfies parity check equations of a parity check matrix of qJ rows×qN columns. A first submatrix of qJ rows×qJ columns that corresponds to the parity symbol sequence in the parity check matrix includes a second submatrix. The second submatrix includes a first identity matrix of qL rows×qL columns (L is an integer, J>L) and a first non-zero matrix of q(J−L) rows×qL columns.
摘要翻译：根据一个实施例，编码装置包括输入单元和生成单元。输入单元输入包含q（N-J）个符号（q，J和N是整数N> J）的数据符号序列。生成单元通过将包含qJ个符号的奇偶校验符号序列添加到数据符号序列来生成包含qN符号的码字。码字满足qJ行×qN列的奇偶校验矩阵的奇偶校验方程。对应于奇偶校验矩阵中的奇偶校验符号序列的qJ行×qJ列的第一子矩阵包括第二子矩阵。第二子矩阵包括qL行×qL列（L是整数J> L）和q（J-L）行×qL列的第一非零矩阵的第一单位矩阵。

8. 发明申请

US20080205540A1 WIRELESS COMMUNICATION APPARATUS 审中-公开
标题翻译：无线通信设备
公开(公告)号：US20080205540A1
公开(公告)日：2008-08-28
申请号：US12106101
申请日：2008-04-18
申请人： Daisuke TAKEDA , Yoshimasa EGASHIRA , Tsuguhide AOKI , Yasuhiko TANABE , Kohsuke HARADA , Hironori UCHIKAWA
发明人： Daisuke TAKEDA , Yoshimasa EGASHIRA , Tsuguhide AOKI , Yasuhiko TANABE , Kohsuke HARADA , Hironori UCHIKAWA
IPC分类号： H04L1/02
CPC分类号： H04B7/04 , H04L5/0023 , H04L5/0048 , H04L25/0204 , H04L25/0226
摘要： Before data is transmitted from a plurality of antennas, a plurality of known symbol sequences are transmitted from these antennas. Each known symbol sequence contains a plurality of known symbols having different subcarrier arrangements. Known symbols transmitted from different antennas have different subcarrier arrangements.
摘要翻译：在从多个天线发送数据之前，从这些天线发送多个已知符号序列。每个已知符号序列包含具有不同副载波布置的多个已知符号。从不同天线发送的已知符号具有不同的子载波布置。

9. 发明申请

US20130055050A1 ERROR CORRECTION ENCODING APPARATUS, ERROR CORRECTION DECODING APPARATUS, NONVOLATILE SEMICONDUCTOR MEMORY SYSTEM, AND PARITY CHECK MATRIX GENERATION METHOD 有权
标题翻译：错误校正编码设备，错误校正解码设备，非易失性半导体存储器系统和奇偶校验矩阵生成方法
公开(公告)号：US20130055050A1
公开(公告)日：2013-02-28
申请号：US13406808
申请日：2012-02-28
申请人： Hironori UCHIKAWA
发明人： Hironori UCHIKAWA
IPC分类号： H03M13/07 , G06F11/10
CPC分类号： H03M13/033 , G06F11/1012 , H03M13/09 , H03M13/116 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/2906
摘要： According to one embodiment, an error correction encoding apparatus includes a linear encoder and a low-density parity check (LDPC) encoder. The linear encoder supports a linear coding scheme enabling a parity check to be carried out by a division using a generating polynomial and applies the generating polynomial to input data to obtain linear coded data. The LDPC encoder applies a generator matrix corresponding to a parity check matrix for an LDPC code to the linear coded data to obtain output data. The parity check matrix satisfies Expression (1) shown in the specification.
摘要翻译：根据一个实施例，纠错编码装置包括线性编码器和低密度奇偶校验（LDPC）编码器。线性编码器支持通过使用生成多项式的分割来执行奇偶校验的线性编码方案，并将生成多项式应用于输入数据以获得线性编码数据。 LDPC编码器将对应于LDPC码的奇偶校验矩阵的生成矩阵应用于线性编码数据以获得输出数据。奇偶校验矩阵满足说明书中所示的表达式（1）。

10. 发明申请

US20120221918A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20120221918A1
公开(公告)日：2012-08-30
申请号：US13465624
申请日：2012-05-07
申请人： Shinichi KANNO , Hironori UCHIKAWA
发明人： Shinichi KANNO , Hironori UCHIKAWA
IPC分类号： H03M13/29 , G06F11/10
CPC分类号： H03M13/2906 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1068 , G06F13/1673 , G06F13/4068 , G11C29/52 , H03M13/03 , H03M13/29 , H03M13/35 , H03M13/6561 , Y02D10/14 , Y02D10/151
摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
摘要翻译：半导体存储器件包括多个检测码发生器，其被配置为分别产生多个检测码以分别检测多个数据项中的错误;多个第一校正码发生器，被配置为产生多个第一校正码以校正错误在多个第一数据块中，分别包含数据项之一和相应检测码的第一数据块，被配置为生成用于校正第二数据块中的错误的第二校正码的第二校正码发生器，包含第一数据块的第二数据块，以及被配置为非易失性地存储第二数据块，第一校正码和第二校正码的半导体存储器。

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