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    • 2. 发明授权
    • Buffer storage control system
    • 缓冲存储控制系统
    • US5510973A
    • 1996-04-23
    • US39008
    • 1993-04-09
    • Tetsuya Morioka
    • Tetsuya Morioka
    • G06F12/08G06F12/10G05B15/00G06F13/24
    • G06F12/0822G06F12/1054
    • In a buffer storage control system for controlling a buffer storage based on a part of a page address of a logical address and a part of a byte index of the logical address which is used as a line address, the system includes: a tag portion TAG1 (13, 17) provided in a plurality of pipe lines (IF, OP) of a central processing unit CPU (1) to retrieve a hit/mis-hit of data based on a part of the page address of the logical address and a part of the byte address of the logical address which is used as the basic line address; a data portion DATA (14, 18) for holding data when retrieving the tag portion TAG1 by the basic line address and when the data is hit; and a tag portion TAG2 (21, 22) provided in a MCU, when the data is mis-hit by using the basic line address, to retrieve the hit/mis-hit of data by using a synonymic line address which is obtained by changing a variable portion of the basic line address; wherein, in a data access, the tag portion TAG1 is retrieved by using only the basic line address, when the data is hit using the tag portion TAG1, the data portion DATA is accessed, on the other hand, when the data is mis-hit using tap portion TAG1, the tag TAG2 is retrieved by using the basic line address and the synonymic line address, further, when the data is hit using tap portion TAG2, the data portion DATA is invalidated, a move-out operation is invalidated, and a move-in operation is validated.
    • PCT No.PCT / JP92 / 01035 Sec。 371日期:1993年4月9日 102(e)日期1993年4月9日PCT提交1992年8月13日PCT公布。 出版物WO93 / 04431 日期:1992年4月3日。在基于逻辑地址的页面地址的一部分和逻辑地址的字节索引的一部分来控制缓冲存储器的缓冲存储控制系统中,该逻辑地址被用作行地址, 系统包括:设置在中央处理单元CPU(1)的多个管线(IF,OP)中的标签部分TAG1(13,17),用于基于页面的一部分来检索数据的命中/错误命中 逻辑地址的地址和用作基本行地址的逻辑地址的字节地址的一部分; 数据部分DATA(14,18),用于在通过基本行地址检索标签部分TAG1时以及当数据被命中时保存数据; 以及设置在MCU中的标签部分TAG2(21,22),当通过使用基本行地址对数据进行错误打击时,通过使用通过改变获得的同义词地址来检索数据的命中/错误命中 基本行地址的可变部分; 其中,在数据访问中,通过仅使用基本行地址来检索标签部分TAG 1,当使用标签部分TAG1命中数据时,访问数据部分DATA,另一方面,当数据为错误时 - 使用抽头部分TAG1,通过使用基本行地址和同步行地址检索标签TAG2,此外,当使用抽头部分TAG2命中数据时,数据部分DATA无效,移出操作无效 ,并且验证了移入操作。
    • 5. 发明授权
    • Buffer control system using synonymic line address to retrieve second
tag portion for fetch and store accesses while first tag portion is
invalidated
    • 缓冲器控制系统使用同步线地址来检索第二标签部分,用于在第一标签部分无效时进行获取和存储访问
    • US5426749A
    • 1995-06-20
    • US39007
    • 1993-04-09
    • Tetsuya Morioka
    • Tetsuya Morioka
    • G06F12/08G06F12/10G06F13/24
    • G06F12/1063
    • In a buffer storage control system for controlling a buffer storage for a store-through method based on a part of a page address of a logical address and a part of a byte index of the logical address used as a line address, the system includes: a buffer storage DATA for holding data and a tag portion TAG1 provided in a central processing unit CPU to retrieve a hit/mis-hit of data based on a part of the page address of the logical address and a part of the byte address of the logical address as a basic line address, and a tag portion TAG2 provided in a main control unit MCU to retrieve the hit/mis-hit of data by using a synonymic line address which is obtained by changing a variable portion of the basic line address. In a fetch access, the tag portion TAG1 is retrieved by using the basic line address and when the data is hit, the data is transferred from the buffer storage DATA to a source of the fetch access request. When the data is mis-hit, the tag TAG 2 is retrieved by using the synonymic line address. When the data is hit by tag TAG 2, the tag portion TAG 1 is invalidated. When the data is mis-hit by tag TAG 2, the fetch data is moved from the main storage unit MSU to the buffer storage DATA, and transferred to the source of the fetch access request.
    • PCT No.PCT / JP92 / 01034 Sec。 371日期:1993年4月9日 102(e)日期1993年4月9日PCT 1991年8月13日提交PCT。在缓冲存储控制系统中,用于基于逻辑地址的页面地址的一部分和部分来控制用于存储方法的缓冲存储器 用作线路地址的逻辑地址的字节索引,系统包括:用于保存数据的缓冲存储器DATA和设置在中央处理单元CPU中的标签部分TAG1,以基于一个或多个数据来检索数据的命中/错误命中 逻辑地址的页面地址的一部分和作为基本行地址的逻辑地址的字节地址的一部分,以及设置在主控制单元MCU中的标签部分TAG2,以通过使用来检索数据的命中/错误命中 通过改变基本行地址的可变部分而获得的同义词地址。 在提取访问中,通过使用基本行地址来检索标签部分TAG1,并且当数据被命中时,数据从缓冲存储器DATA传送到提取访问请求的源。 当数据被错误打击时,通过使用同步行地址来检索标签TAG 2。 当数据被标签TAG 2命中时,标签部分TAG 1无效。 当数据被标签TAG 2打错时,取出数据从主存储单元MSU移动到缓冲存储器DATA,并被传送到获取访问请求的源。
    • 8. 发明授权
    • Computer system using cache buffer storage unit and independent storage
buffer device for store through operation
    • 计算机系统采用缓存缓存存储单元和独立存储缓冲设备进行存储通过操作
    • US4742446A
    • 1988-05-03
    • US682309
    • 1984-12-17
    • Tetsuya MoriokaTsutomu TanakaKatsumi OnishiYuji Oinaga
    • Tetsuya MoriokaTsutomu TanakaKatsumi OnishiYuji Oinaga
    • G06F12/00G06F12/04G06F12/08G06F12/06
    • G06F12/0804
    • A computer system includes a processing unit; main storage; cache buffer storage provided between the processing unit and the main storage; and a store buffer device between the processing unit and main storage, receiving data identical to that stored in the cache buffer storage and control information in response to requests from the processing unit and transferring the data and control information to main storage. The transmission from the processing unit to the store buffer device and from the store buffer device to main storage are in a machine cycle. The store buffer device includes a controller, data register sets, each set including registers for receiving data to be stored in main storage, a byte mark register set of byte mark registers for information indicating storable data in the data registers, and an address register set of address registers for a starting store address in main storage for the data in the data registers. The number of data register sets is a plurality of times the bus width of the central processor. Each byte mark register has bits corresponding to the number of data register sets multiplied by the number of bytes in each data register.
    • 计算机系统包括处理单元; 主要存储; 在处理单元和主存储器之间提供缓存缓冲存储器; 以及在处理单元和主存储器之间的存储缓冲器设备,响应于来自处理单元的请求接收与存储在高速缓存缓冲存储器和控制信息中的数据相同的数据,并将数据和控制信息传送到主存储器。 从处理单元到存储缓冲设备以及从存储缓冲设备到主存储器的传输在机器周期中。 存储缓冲装置包括控制器,数据寄存器组,每组包括用于接收存储在主存储器中的数据的寄存器,用于指示数据寄存器中的可存储数据的信息的字节标记寄存器的字节标记寄存器组,以及地址寄存器组 用于数据寄存器中的数据的主存储器中的起始存储地址的地址寄存器。 数据寄存器组的数量是中央处理器的总线宽度的多倍。 每个字节标记寄存器都有与数据寄存器组数相乘的位数乘以每个数据寄存器中的字节数。