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1. 发明授权

US06962857B1 Shallow trench isolation process using oxide deposition and anneal 有权
标题翻译：使用氧化物沉积和退火的浅沟槽隔离工艺
公开(公告)号：US06962857B1
公开(公告)日：2005-11-08
申请号：US10358966
申请日：2003-02-05
申请人： Minh-Van Ngo , Ming-Ren Lin , Eric N. Paton , Haihong Wang , Qi Xiang , Jung-Suk Goo
发明人： Minh-Van Ngo , Ming-Ren Lin , Eric N. Paton , Haihong Wang , Qi Xiang , Jung-Suk Goo
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8234 , H01L21/8238
CPC分类号： H01L21/76224 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878
摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in a strained silicon (SMOS) process. The liner for the trench is formed from a layer deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be an LPCVD. An annealing step can be utilized to form the liner.
摘要翻译：集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。浅沟槽隔离技术用于应变硅（SMOS）工艺。用于沟槽的衬垫由沉积在低温过程中的层形成，其减少锗除气。低温过程可以是LPCVD。可以使用退火步骤来形成衬垫。

2. 发明申请

US20090047770A1 METHOD OF FORMING ISOLATION REGIONS FOR INTEGRATED CIRCUITS 有权
标题翻译：形成集成电路隔离区的方法
公开(公告)号：US20090047770A1
公开(公告)日：2009-02-19
申请号：US12205361
申请日：2008-09-05
申请人： Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
发明人： Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L21/823481 , H01L29/1054
摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a ALD process.
摘要翻译：集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。浅沟槽隔离技术用于应变硅（SMOS）工艺。用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。低温过程可以是ALD过程。

3. 发明授权

US07422961B2 Method of forming isolation regions for integrated circuits 有权
标题翻译：形成集成电路隔离区的方法
公开(公告)号：US07422961B2
公开(公告)日：2008-09-09
申请号：US10389456
申请日：2003-03-14
申请人： Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
发明人： Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/823481 , H01L29/1054
摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a CVD process.
摘要翻译：集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。浅沟槽隔离技术用于应变硅（SMOS）工艺。用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。低温工艺可以是CVD工艺。

4. 发明授权

US07713834B2 Method of forming isolation regions for integrated circuits 有权
标题翻译：形成集成电路隔离区的方法
公开(公告)号：US07713834B2
公开(公告)日：2010-05-11
申请号：US12205361
申请日：2008-09-05
申请人： Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
发明人： Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L21/823481 , H01L29/1054
摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a ALD process.
摘要翻译：集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。浅沟槽隔离技术用于应变硅（SMOS）工艺。用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。低温过程可以是ALD过程。

5. 发明授权

US07648886B2 Shallow trench isolation process 有权
标题翻译：浅沟槽隔离工艺
公开(公告)号：US07648886B2
公开(公告)日：2010-01-19
申请号：US10341863
申请日：2003-01-14
申请人： Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
发明人： Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed to in a low temperature process which reduces germanium outgassing. The low temperature process can be a UVO, ALD, CVD, PECVD, or HDP process.
摘要翻译：集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。浅沟槽隔离技术用于应变硅（SMOS）工艺。用于沟槽的衬垫形成为能够减少锗除气的低温过程。低温过程可以是UVO，ALD，CVD，PECVD或HDP工艺。

6. 发明授权

US06858503B1 Depletion to avoid cross contamination 失效
标题翻译：消耗以避免交叉污染
公开(公告)号：US06858503B1
公开(公告)日：2005-02-22
申请号：US10358484
申请日：2003-02-05
申请人： Minh V. Ngo , Ming-Ren Lin , Paul R. Besser , Qi Xiang , Eric N. Paton , Jung-Suk Goo
发明人： Minh V. Ngo , Ming-Ren Lin , Paul R. Besser , Qi Xiang , Eric N. Paton , Jung-Suk Goo
IPC分类号： H01L21/306 , H01L29/10 , H01L21/336
CPC分类号： H01L21/02046 , H01L29/1054
摘要： A fabrication system utilizes a protocol for removing germanium from a top surface of a wafer. An exposure to a gas, such as a gas containing the hydrochloric acid can remove germanium from the top surface. The protocol can allow shared equipment to be used in both Flash product fabrication lines and strained silicon (SMOS) fabrication lines. The protocol allows better silicidation in SMOS devices.
摘要翻译：制造系统利用从晶片顶表面去除锗的方案。暴露于气体，如含有盐酸的气体，可以从上表面除去锗。该协议可以允许在Flash产品制造线和应变硅（SMOS）生产线中使用共享设备。该协议允许在SMOS器件中更好的硅化。

7. 发明授权

US07312125B1 Fully depleted strained semiconductor on insulator transistor and method of making the same 有权
标题翻译：绝缘子晶体管的全耗尽应变半导体及其制造方法
公开(公告)号：US07312125B1
公开(公告)日：2007-12-25
申请号：US10773026
申请日：2004-02-05
申请人： Qi Xiang , Paul R. Besser , Minh Van Ngo , Eric N. Paton , Haihong Wang
发明人： Qi Xiang , Paul R. Besser , Minh Van Ngo , Eric N. Paton , Haihong Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L27/1203 , H01L29/66553 , H01L29/66621 , H01L29/7848 , H01L29/78621 , H01L29/78684 , Y10S438/938
摘要： An integrated circuit includes multiple layers. A semiconductor-on-insulator (SOI) wafer can be used to house transistors. Two substrates or wafers can be bonded to form the multiple layers. A strained semiconductor layer can be between a silicon germanium layer and a buried oxide layer. A hydrogen implant can provide a breaking interface to remove a silicon substrate from the silicon germanium layer.
摘要翻译：集成电路包括多层。可以使用绝缘体上半导体（SOI）晶片来容纳晶体管。可以结合两个基板或晶片以形成多个层。应变半导体层可以在硅锗层和掩埋氧化物层之间。氢注入可以提供断开界面以从硅锗层去除硅衬底。

8. 发明授权

US06730576B1 Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer 有权
标题翻译：形成厚应变硅层的方法和掺入厚应变硅层的半导体结构
公开(公告)号：US06730576B1
公开(公告)日：2004-05-04
申请号：US10335447
申请日：2002-12-31
申请人： Haihong Wang , Paul R. Besser , Jung-Suk Goo , Minh V. Ngo , Eric N. Paton , Qi Xiang
发明人： Haihong Wang , Paul R. Besser , Jung-Suk Goo , Minh V. Ngo , Eric N. Paton , Qi Xiang
IPC分类号： H01L21762
CPC分类号： H01L29/7833 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/76224 , H01L29/1054 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： A strained silicon layer is grown on a layer of silicon germanium and a layer of silicon germanium is grown on the strained silicon in a single continuous in situ deposition process with the strained silicon. Shallow trench isolations are formed in the lower layer of silicon germanium prior to formation of the strained silicon layer. The two silicon germanium layers effectively provide dual substrates at both surfaces of the strained silicon layer that serve to maintain the tensile strain of the strained silicon layer and resist the formation of misfit dislocations that might otherwise result from temperature changes during processing. Consequently the critical thickness of strained silicon that can be grown without significant misfit dislocations during later processing is effectively doubled for a given germanium content of the silicon germanium layers. The formation of shallow trench isolations prior to formation of the strained silicon layer avoids subjecting the strained silicon layer to extreme thermal stresses and further reduces the formation of misfit dislocations.
摘要翻译：应变硅层在硅锗层上生长，并且在应变硅上生长硅锗层，并在应变硅中进行单次连续原位沉积工艺。在形成应变硅层之前，在硅锗的下层形成浅沟槽隔离。两个硅锗层有效地在应变硅层的两个表面上提供双重衬底，其用于维持应变硅层的拉伸应变，并抵抗由加工过程中的温度变化引起的失配位错的形成。因此，对于硅锗层的给定锗含量，可以在后续处理期间可以生长而不显着失配位错的应变硅的临界厚度被有效地加倍。在形成应变硅层之前形成浅沟槽隔离避免使应变硅层受到极端的热应力，并进一步减少失配位错的形成。

9. 发明授权

US06800910B2 FinFET device incorporating strained silicon in the channel region 有权
标题翻译： FinFET器件在通道区域中包含应变硅
公开(公告)号：US06800910B2
公开(公告)日：2004-10-05
申请号：US10335474
申请日：2002-12-31
申请人： Ming-Ren Lin , Jung-Suk Goo , Haihong Wang , Qi Xiang
发明人： Ming-Ren Lin , Jung-Suk Goo , Haihong Wang , Qi Xiang
IPC分类号： H01L27105
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/42384 , H01L29/66795 , H01L29/78603 , H01L29/78687
摘要： A FinFET device employs strained silicon to enhance carrier mobility. In one method, a FinFET body is patterned from a layer of silicon germanium (SiGe) that overlies a dielectric layer. An epitaxial layer of silicon is then formed on the silicon germanium FinFET body. A strain is induced in the epitaxial silicon as a result of the different dimensionalities of intrinsic silicon and of the silicon germanium crystal lattice that serves as the template on which the epitaxial silicon is grown. Strained silicon has an increased carrier mobility compared to relaxed silicon, and as a result the epitaxial strained silicon provides increased carrier mobility in the FinFET. A higher driving current can therefore be realized in a FinFET employing a strained silicon channel layer.
摘要翻译： FinFET器件采用应变硅来增强载流子迁移率。在一种方法中，FinFET体从覆盖在电介质层上的硅锗层（SiGe）构图。然后在硅锗FinFET体上形成硅的外延层。由于本征硅和作为外延硅生长的模板的硅锗晶格的不同维度，在外延硅中引起应变。与松弛硅相比，应变硅具有增加的载流子迁移率，结果外延应变硅在FinFET中提供增加的载流子迁移率。因此，可以在采用应变硅沟道层的FinFET中实现更高的驱动电流。

10. 发明授权

US06924182B1 Strained silicon MOSFET having reduced leakage and method of its formation 有权
标题翻译：应变硅MOSFET具有减少的泄漏和其形成方法
公开(公告)号：US06924182B1
公开(公告)日：2005-08-02
申请号：US10642375
申请日：2003-08-15
申请人： Qi Xiang , Ming Ren Lin , Minh V. Ngo , Eric N. Paton , Haihong Wang
发明人： Qi Xiang , Ming Ren Lin , Minh V. Ngo , Eric N. Paton , Haihong Wang
IPC分类号： H01L21/762 , H01L21/8238 , H01L21/8234 , H01L21/76
CPC分类号： H01L21/823878 , H01L21/76237 , H01L21/823807
摘要： The formation of shallow trench isolations in a strained silicon MOSFET includes performing ion implantation in the strained silicon layer in the regions to be etched to form the trenches of the shallow trench isolations. The dosage of the implanted ions and the energy of implantation are chosen so as to damage the crystal lattice of the strained silicon throughout the thickness of the strained silicon layer in the shallow trench isolation regions to such a degree that the etch rate of the strained silicon in those regions is increased to approximately the same as or greater than the etch rate of the underlying undamaged silicon germanium. Subsequent etching yields trenches with significantly reduced or eliminated undercutting of the silicon germanium relative to the strained silicon. This in turn substantially prevents the formation of fully depleted silicon on insulator regions under the ends of the gate, thus improving the MOSFET leakage current.
摘要翻译：应变硅MOSFET中的浅沟槽隔离的形成包括在被蚀刻的区域中的应变硅层中执行离子注入以形成浅沟槽隔离的沟槽。选择注入离子的剂量和注入能量，以便在浅沟槽隔离区域中的应变硅层的整个厚度上损坏应变硅的晶格，使得应变硅的蚀刻速率在这些区域中增加到大致等于或大于底层未损坏的硅锗的蚀刻速率。随后的蚀刻产生相对于应变硅显着减少或消除硅锗底切的沟槽。这又大大防止了在栅极端部的绝缘体区域上形成完全耗尽的硅，从而改善MOSFET漏电流。

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