专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070249135A1 Collector tailored structures for integration of binary junction transistors 有权
标题翻译：集成器定制结构，用于二元结结晶体管的集成
公开(公告)号：US20070249135A1
公开(公告)日：2007-10-25
申请号：US11406788
申请日：2006-04-19
申请人： Ming-Yeh Chuang , Leland Swanson
发明人： Ming-Yeh Chuang , Leland Swanson
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/66272 , H01L21/8249 , H01L29/0821 , H01L29/6625
摘要： A bipolar transistor is formed in an integrated BiCMOS process. A buried layer is formed in a semiconductor body. An intrinsic dilute mask is formed over the buried layer that covers at least a portion of a selected region of a target deep well region. The intrinsic dilute mask is employed to implant a dopant into the target deep well region to form a deep well region with the selected region having a lowered dopant concentration. The lowered dopant concentration can yield a higher breakdown voltage for the bipolar device. The intrinsic dilute mask mitigates implantation within the selected region.
摘要翻译：在集成BiCMOS工艺中形成双极晶体管。掩埋层形成在半导体本体中。在覆盖目标深井区域的选定区域的至少一部分的掩埋层上形成固有稀释掩模。使用固有稀释掩模将掺杂剂注入到目标深阱区域中以形成具有降低的掺杂剂浓度的所选区域的深阱区域。降低的掺杂剂浓度可以产生双极器件的更高的击穿电压。固有稀释掩模减轻了所选区域内的植入。

2. 发明申请

US20070246800A1 Transistor apparatus 有权
标题翻译：晶体管装置
公开(公告)号：US20070246800A1
公开(公告)日：2007-10-25
申请号：US11408775
申请日：2006-04-21
申请人： Leland Swanson , Gregory Howard
发明人： Leland Swanson , Gregory Howard
IPC分类号： H01L27/12
CPC分类号： H01L29/7322 , H01L29/0821
摘要： A transistor apparatus includes a silicon substrate and a barrier structure extending substantially from generally adjacent the silicon substrate to a locus displaced from the silicon substrate. The barrier structure generally surrounds a volume containing connection loci for the transistor apparatus and a buried layer in a silicon medium. The connection loci and the buried layer occupy a space generally presenting a first lateral expanse generally parallel with the silicon substrate. The volume presents a second lateral expanse generally parallel with the silicon substrate. The second lateral expanse is greater than the first lateral expanse within a predetermined distance of the substrate.
摘要翻译：晶体管装置包括硅衬底和基本上从硅衬底基本上相邻延伸到从硅衬底移位的轨迹的阻挡结构。阻挡结构通常围绕用于晶体管装置的连接轨迹和硅介质中的掩埋层的体积。连接轨迹和埋层占据通常呈现与硅衬底大致平行的第一横向宽度的空间。体积呈现与硅衬底大致平行的第二横向宽度。第二横向宽度大于在衬底的预定距离内的第一横向宽度。

3. 发明申请

US20070152753A1 System and method for clamping a differential amplifier 有权
标题翻译：用于钳位差分放大器的系统和方法
公开(公告)号：US20070152753A1
公开(公告)日：2007-07-05
申请号：US11325843
申请日：2006-01-05
申请人： Leland Swanson
发明人： Leland Swanson
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F1/12 , H03F3/45183 , H03F2200/153 , H03F2203/45101 , H03F2203/45138 , H03F2203/45186 , H03F2203/45628 , H03F2203/45636
摘要： System and method for limiting an output signal of a differential amplifier. A preferred embodiment comprises a limit sense amplifier configured to detect when the output exceeds a permitted limit, a common mode bias current unit configured to increase a signal gain of a common mode amplifier in the differential operational amplifier when the limit sense amplifier detects that the output exceeded the permitted limit, and an output stage bias current unit configured to fix the output at a level substantially equal to the specified limit when the limit sense amplifier detects that the output exceeded the permitted limit. The clamping is achieved by changing the operation of circuitry within the differential amplifier and results in a smoother clamping that helps to maintain stable operation.
摘要翻译：限制差分放大器输出信号的系统和方法。优选实施例包括限制读出放大器，其被配置为检测何时输出超过允许极限;共模偏置电流单元，其被配置为当限位读出放大器检测到输出时增加差分运算放大器中的共模放大器的信号增益以及输出级偏置电流单元，其配置为当限位读出放大器检测到输出超过允许极限时将输出固定在基本上等于指定极限的电平。通过改变差分放大器内部电路的运行来实现钳位，从而实现更平滑的钳位，有助于保持稳定运行。

4. 发明申请

US20060151804A1 Versatile system for cross-lateral junction field effect transisor 有权
标题翻译：用于跨横向连接场效应的通用系统
公开(公告)号：US20060151804A1
公开(公告)日：2006-07-13
申请号：US11031586
申请日：2005-01-07
申请人： Gregory Howard , Leland Swanson
发明人： Gregory Howard , Leland Swanson
IPC分类号： H01L29/423
CPC分类号： H01L29/808 , H01L29/0692
摘要： The present invention provides a system for providing a cross-lateral junction field effect transistor (114) having desired high-performance desired voltage, frequency or current characteristics. The cross-lateral transistor is formed on a commercial semiconductor substrate (102). A channel structure (124) is formed along the substrate, having source (120) and drain (122) structures laterally formed on opposites sides thereof. A first gate structure (116) is formed along the substrate, laterally adjoining the channel structure orthogonal to the source and drain structures. A second gate structure (118) is formed along the substrate, laterally adjoining the channel structure, orthogonal to the source and drain structures and opposite the first gate structure.
摘要翻译：本发明提供了一种用于提供具有期望的高性能期望电压，频率或电流特性的横向结型场效应晶体管（114）的系统。横向晶体管形成在商用半导体衬底（102）上。沿着衬底形成通道结构（124），其具有在其相对侧上横向形成的源极（120）和漏极（122）结构。第一栅极结构（116）沿着衬底形成，横向邻接与源极和漏极结构正交的沟道结构。第二栅极结构（118）沿着衬底形成，横向邻接沟道结构，垂直于源极和漏极结构并与第一栅极结构相对。

5. 发明申请

US20050077590A1 Guard ring structure for a Schottky diode 有权
标题翻译：肖特基二极管的保护环结构
公开(公告)号：US20050077590A1
公开(公告)日：2005-04-14
申请号：US10681400
申请日：2003-10-08
申请人： Leland Swanson , Gregory Howard
发明人： Leland Swanson , Gregory Howard
IPC分类号： H01L21/765 , H01L27/08 , H01L29/06 , H01L29/40 , H01L29/417 , H01L29/872 , H01L27/095 , H01L21/28 , H01L21/44 , H01L29/47 , H01L29/812 , H01L31/07 , H01L31/108
CPC分类号： H01L29/402 , H01L21/765 , H01L27/0814 , H01L29/417 , H01L29/872
摘要： A Schottky device comprises a substrate layer of a first conductivity type having a surface, a guard ring formed over the surface of the substrate layer and surrounding a barrier region of the substrate layer. The guard ring comprises a gate of a second conductivity type disposed over a dielectric layer. A metal can be formed over the barrier region to form a Schottky junction.
摘要翻译：肖特基装置包括具有表面的第一导电类型的衬底层，形成在衬底层的表面上并围绕衬底层的阻挡区域的保护环。保护环包括布置在电介质层上的第二导电类型的栅极。可以在阻挡区域上形成金属以形成肖特基结。

6. 发明授权

US07459357B2 Versatile system for cross-lateral junction field effect transistor 有权
标题翻译：用于跨横向结型场效应晶体管的多功能系统
公开(公告)号：US07459357B2
公开(公告)日：2008-12-02
申请号：US11839832
申请日：2007-08-16
申请人： Gregory E Howard , Leland Swanson
发明人： Gregory E Howard , Leland Swanson
IPC分类号： H01L21/337
CPC分类号： H01L29/808 , H01L29/0692
摘要： The present invention provides a system for providing a cross-lateral junction field effect transistor (114) having desired high-performance desired voltage, frequency or current characteristics. The cross-lateral transistor is formed on a commercial semiconductor substrate (102). A channel structure (124) is formed along the substrate, having source (120) and drain (122) structures laterally formed on opposites sides thereof. A first gate structure (116) is formed along the substrate, laterally adjoining the channel structure orthogonal to the source and drain structures. A second gate structure (118) is formed along the substrate, laterally adjoining the channel structure, orthogonal to the source and drain structures and opposite the first gate stricture.
摘要翻译：本发明提供了一种用于提供具有期望的高性能期望电压，频率或电流特性的横向结型场效应晶体管（114）的系统。横向晶体管形成在商用半导体衬底（102）上。沿着衬底形成通道结构（124），其具有在其相对侧上横向形成的源极（120）和漏极（122）结构。第一栅极结构（116）沿着衬底形成，横向邻接与源极和漏极结构正交的沟道结构。沿着衬底形成第二栅极结构（118），其横向邻接沟道结构，垂直于源极和漏极结构并与第一栅极狭窄相对。

7. 发明申请

US20060226521A1 Semiconductor Package Having Integrated Metal Parts for Thermal Enhancement 审中-公开
标题翻译：具有集成金属部件用于热增强的半导体封装
公开(公告)号：US20060226521A1
公开(公告)日：2006-10-12
申请号：US11426166
申请日：2006-06-23
申请人： Anthony Coyle , William Boyd , Chris Haga , Leland Swanson
发明人： Anthony Coyle , William Boyd , Chris Haga , Leland Swanson
IPC分类号： H01L23/495
CPC分类号： H01L23/4334 , H01L24/48 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/01078 , H01L2924/14 , H01L2924/16152 , H01L2924/181 , H01L2924/19041 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device comprising a metallic leadframe (103) with a first surface (103a) and a second surface (103b). The leadframe includes a chip pad (104) and a plurality of segments (107); the chip pad is held by a plurality of straps (105), wherein each strap has a groove (106). A chip (101) is mounted on the chip pad and electrically connected to the segments. A heat spreader (110) is disposed on the first surface of the leadframe; the heat spreader has its central portion (110a) spaced above the chip connections (108), and also has positioning members (110b) extending outwardly from the edges of the central portion so that they rest in the grooves of the straps. Encapsulation material surrounds the chip, the electrical connections, and the spreader positioning members, and fills the space between the spreader and the chip, while leaving the second leadframe surface and the central spreader portion exposed.
摘要翻译：一种半导体器件，包括具有第一表面（103a）和第二表面（103b）的金属引线框架（103）。引线框架包括芯片焊盘（104）和多个段（107）; 芯片垫由多个带（105）保持，其中每个带具有凹槽（106）。芯片（101）安装在芯片焊盘上并电连接到段上。散热器（110）设置在引线框架的第一表面上; 散热器具有在芯片连接件（108）上方间隔开的中心部分（110a），并且还具有从中心部分的边缘向外延伸的定位构件（110b），使得它们搁置在带的凹槽中。封装材料围绕芯片，电连接和扩展器定位构件，并且填充扩展器和芯片之间的空间，同时使第二引线框表面和中心扩展器部分露出。

8. 发明申请

US20050247955A1 Implant-controlled-channel vertical JFET 审中-公开
公开(公告)号：US20050247955A1
公开(公告)日：2005-11-10
申请号：US11127991
申请日：2005-05-11
申请人： Gregory Howard , Leland Swanson
发明人： Gregory Howard , Leland Swanson
IPC分类号： H01L21/337 , H01L29/10 , H01L29/808 , H01L29/423
CPC分类号： H01L29/66909 , H01L29/1058 , H01L29/8083
摘要： We disclose the structure of an electronic device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has, near the top surface, a buried layer that is electrically communicable to a drain terminal. The device has a body region over the buried layer. A portion of the body region contacts a gate region connected to a gate terminal. The device has a channel region, of which the length spans the distance between the buried layer and a source region, which projects upward from the channel region and is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.

9. 发明申请

US20050230842A1 Multi-chip flip package with substrate for inter-die coupling 审中-公开
标题翻译：具有用于晶片间耦合的衬底的多芯片翻转封装
公开(公告)号：US20050230842A1
公开(公告)日：2005-10-20
申请号：US10827836
申请日：2004-04-20
申请人： Leland Swanson , William Boyd
发明人： Leland Swanson , William Boyd
IPC分类号： H01L23/48 , H01L23/495 , H01L23/498 , H01L25/065 , H01L25/16
CPC分类号： H01L25/0655 , H01L23/49575 , H01L23/49861 , H01L25/162 , H01L2224/16145 , H01L2224/16227 , H01L2224/16245 , H01L2224/32245 , H01L2224/73253 , H01L2924/15153 , H01L2924/15192
摘要： A method comprising coupling a substrate interconnect to a substrate pad, attaching at least two flip chips to said substrate interconnect to electrically connect together said chips, and coupling at least one lead to each of the chips.
摘要翻译：一种方法，包括将衬底互连件耦合到衬底焊盘，将至少两个倒装芯片附接到所述衬底互连以将所述芯片电连接在一起，以及将至少一个引线耦合到每个芯片。

10. 发明申请

US20050194621A1 Double diffused vertical JFET 审中-公开
标题翻译：双扩散垂直JFET
公开(公告)号：US20050194621A1
公开(公告)日：2005-09-08
申请号：US11035292
申请日：2005-01-12
申请人： Gregory Howard , Leland Swanson
发明人： Gregory Howard , Leland Swanson
IPC分类号： H01L21/337 , H01L29/808 , H01L29/80
CPC分类号： H01L29/66909 , H01L29/8083
摘要： We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a body region above the buried layer. A portion of the body region contacts a gate region connected to a gate terminal. The device has a channel region, of which the length spans the distance between the buried layer and a source region, which projects upward from the channel region and is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.
摘要翻译：我们公开了JFET器件的结构，制造器件的方法和器件的操作。该器件靠近基板顶部。它具有可电连接到漏极端子的掩埋层。它在埋层之上有一个体区。身体区域的一部分接触连接到栅极端子的栅极区域。该器件具有沟道区，其长度跨越掩埋层与源极区之间的距离，该距离从沟道区向上突出并连接到源极。器件电流在通道中基本上垂直于衬底的顶表面流动。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式