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1. 发明授权

US5736415A Method for manufacturing input/output port devices having low body effect 失效
标题翻译：用于制造具有低体效的输入/输出端口装置的方法
公开(公告)号：US5736415A
公开(公告)日：1998-04-07
申请号：US810075
申请日：1997-03-04
申请人： Ming-Chien Chang , Wuu-Larng Laih
发明人： Ming-Chien Chang , Wuu-Larng Laih
IPC分类号： H01L21/762 , H01L21/82 , H01L21/8238 , H01L21/265
CPC分类号： H01L21/82 , H01L21/762 , H01L21/823807
摘要： A method for manufacturing input/output port devices of a semiconductor circuit having low body effect, suitable for use on a semiconductor substrate on which a plurality of pull-up device regions and pull-down device regions are formed. First, when executing a channel implantation, an anti-punchthrough implantation, and a threshold adjustment implantation, a mask which masks PMOS devices in the CMOS process is used to mask pull-up device regions on a semiconductor substrate. Furthermore, when executing a cell implantation, a mask which masks the outside regions of memory cells is used to mask pull-down device regions. In the invention, the body effect of pull-up devices on the input/output port is reduced without using any extra mask and under the original process, thereby lowering the threshold voltage and reducing the output voltage drop.
摘要翻译：一种用于制造具有低体效应的半导体电路的输入/输出端口装置的方法，适用于形成有多个上拉器件区域和下拉器件区域的半导体衬底上。首先，当执行信道注入，抗穿透注入和阈值调整注入时，使用掩蔽CMOS工艺中的PMOS器件的掩模来掩蔽半导体衬底上的上拉器件区域。此外，当执行细胞注入时，使用掩蔽存储单元的外部区域的掩模来屏蔽下拉器件区域。在本发明中，上拉器件在输入/输出端口上的体效降低，而不需要任何额外的掩模，并且在原始工艺下，从而降低阈值电压并降低输出电压降。

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