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1. 发明授权

US08750070B2 Memory circuits, systems, and operating methods thereof 有权
标题翻译：存储器电路，系统及其操作方法
公开(公告)号：US08750070B2
公开(公告)日：2014-06-10
申请号：US13759791
申请日：2013-02-05
申请人： Ming-Chieh Huang , Kuoyuan (Peter) Hsu
发明人： Ming-Chieh Huang , Kuoyuan (Peter) Hsu
IPC分类号： G11C5/14 , G11C7/12
CPC分类号： G11C5/14 , G11C5/147 , G11C7/12 , G11C7/14 , G11C11/4094 , G11C11/4099
摘要： A memory circuit including at least one memory cell connected to a bit line. The memory circuit further includes a means for providing a bit line reference voltage VBLref to the bit line. A VBLref/VDD ratio of the bit line reference voltage VBLref to a power voltage VDD is adjustable corresponding to a change of the power voltage VDD, and the VBLref/VDD ratio ranges from about 0.4 to about 0.53.
摘要翻译：一种存储器电路，包括连接到位线的至少一个存储单元。存储电路还包括用于向位线提供位线参考电压VBLref的装置。位线参考电压VBLref与电源电压VDD的VBLref / VDD比可根据电源电压VDD的变化进行调整，VBLref / VDD比范围为约0.4至约0.53。

2. 发明授权

US08391094B2 Memory circuits, systems, and operating methods thereof 有权
标题翻译：存储器电路，系统及其操作方法
公开(公告)号：US08391094B2
公开(公告)日：2013-03-05
申请号：US12692534
申请日：2010-01-22
申请人： Ming-Chieh Huang , Kuoyuan Peter Hsu
发明人： Ming-Chieh Huang , Kuoyuan Peter Hsu
IPC分类号： G11C5/04
CPC分类号： G11C5/14 , G11C5/147 , G11C7/12 , G11C7/14 , G11C11/4094 , G11C11/4099
摘要： A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a bit line. The memory circuit includes a means for providing a bit line reference voltage VBLref to the bit line, wherein a VBLref/VDD ratio of the bit line reference voltage VBLref to a power voltage VDD is adjustable corresponding to a change of the power voltage VDD.
摘要翻译：存储电路包括至少一个用于存储表示数据的电荷的存储单元。存储单元与字线和位线耦合。存储电路包括用于向位线提供位线参考电压VBLref的装置，其中位线参考电压VBLref与电源电压VDD的VBLref / VDD比可根据电源电压VDD的变化而调节。

3. 发明授权

US09134360B2 Method and apparatus for feedback-based resistance calibration 有权
标题翻译：用于基于反馈的电阻校准的方法和装置
公开(公告)号：US09134360B2
公开(公告)日：2015-09-15
申请号：US13547101
申请日：2012-07-12
申请人： Tao Wen Chung , Chan-Hong Chern , Ming-Chieh Huang , Chih-Chang Lin , Yuwen Swei
发明人： Tao Wen Chung , Chan-Hong Chern , Ming-Chieh Huang , Chih-Chang Lin , Yuwen Swei
IPC分类号： H03L5/00 , G01R31/26
CPC分类号： G01R31/2621
摘要： A circuit has a first circuit module including a first resistor and first and second transistors coupled in parallel with the first resistor. The first resistor and the first and second transistors are coupled together at a first node. An equivalent resistance across the first circuit module increases as a voltage of the first node is increased from a first voltage to a second voltage, and the equivalent resistance across the first circuit module decreases as the voltage of the first node is increased from the second voltage to a third voltage.
摘要翻译：电路具有包括第一电阻器和与第一电阻器并联耦合的第一和第二晶体管的第一电路模块。第一电阻器和第一和第二晶体管在第一节点耦合在一起。当第一节点的电压从第一电压增加到第二电压时，跨第一电路模块的等效电阻增加，并且第一电路模块上的等效电阻随着第一节点的电压从第二电压增加而减小到第三电压。

4. 发明授权

US08896352B2 Drivers having T-coil structures 有权
标题翻译：驱动器具有T型线圈结构
公开(公告)号：US08896352B2
公开(公告)日：2014-11-25
申请号：US13278742
申请日：2011-10-21
申请人： Ming-Chieh Huang , Tao Wen Chung , Chan-Hong Chern , Chih-Chang Lin , Yuwen Swei , Chiang Pu
发明人： Ming-Chieh Huang , Tao Wen Chung , Chan-Hong Chern , Chih-Chang Lin , Yuwen Swei , Chiang Pu
IPC分类号： H03K3/00
CPC分类号： H03H11/44 , H01S5/0427 , H04B10/504
摘要： A driver includes a first driver stage having at least one input node and at least one first output node. The first driver stage includes a T-coil structure that is disposed adjacent to the at least one first output node. The T-coil structure includes a first set of inductors each being operable to provide a first inductance. A second set of inductors are electrically coupled with the first set of inductors in a parallel fashion. The second set of inductors each are operable to provide a second inductance. A second driver stage is electrically coupled with the first driver stage.
摘要翻译：驱动器包括具有至少一个输入节点和至少一个第一输出节点的第一驱动器级。第一驱动级包括邻近于至少一个第一输出节点设置的T型线圈结构。 T型线圈结构包括第一组电感器，每个电感器可操作以提供第一电感。第二组电感器以并行方式与第一组电感器电耦合。第二组电感器可操作以提供第二电感。第二驱动级与第一驱动器级电耦合。

5. 发明授权

US08816732B2 Capactive load PLL with calibration loop 有权
标题翻译：带校准回路的负载负载PLL
公开(公告)号：US08816732B2
公开(公告)日：2014-08-26
申请号：US13530136
申请日：2012-06-22
申请人： Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin , Tsung-Ching Huang , Fu-Lung Hsueh
发明人： Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin , Tsung-Ching Huang , Fu-Lung Hsueh
IPC分类号： H03L7/06
CPC分类号： H03L7/103 , H03L7/097 , H03L7/0995 , H03L7/1072 , H03L7/18 , H03L2207/06
摘要： A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.
摘要翻译：电路包括电容负载压控振荡器，其具有被配置为接收第一输入信号的输入和被配置为输出振荡输出信号的输出。校准电路耦合到压控振荡器，并被配置为将一个或多个控制信号输出到电容负载压控振荡器，用于调整振荡输出信号的频率。校准电路被配置为响应于输入电压与至少一个参考电压的比较而输出一个或多个控制信号。

6. 发明申请

US20140038085A1 Automatic Misalignment Balancing Scheme for Multi-Patterning Technology 有权
标题翻译：多图案化技术的自动对准平衡方案
公开(公告)号：US20140038085A1
公开(公告)日：2014-02-06
申请号：US13562436
申请日：2012-07-31
申请人： Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin , Tsung-Ching (Jim) Huang , Fu-Lung Hsueh
发明人： Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin , Tsung-Ching (Jim) Huang , Fu-Lung Hsueh
IPC分类号： G06F17/50 , G03F1/68
CPC分类号： G03F7/70466 , G03F7/70433 , G06F17/5077
摘要： Some aspects of the present disclosure provide for a method of automatically balancing mask misalignment for multiple patterning layers to minimize the consequences of mask misalignment. In some embodiments, the method defines a routing grid for one or more double patterning layers within an IC layout. The routing grid has a plurality of vertical grid lines extending along a first direction and a plurality of horizontal grid lines extending along a second, orthogonal direction. Alternating lines of the routing grid in a given direction (e.g., the horizontal and vertical direction) are assigned different colors. Shapes on the double patterning layers are then routed along the routing grid in a manner that alternates between different colored grid lines. By routing in such a manner, variations in capacitive coupling caused by mask misalignment are reduced.
摘要翻译：本公开的一些方面提供了一种自动平衡多个图案化层的掩模未对准的方法，以最小化掩模未对准的后果。在一些实施例中，该方法定义了IC布局内的一个或多个双图案化层的布线网格。路由网格具有沿着第一方向延伸的多个垂直网格线和沿着第二正交方向延伸的多个水平网格线。在给定方向（例如，水平和垂直方向）上布线网格的交替线被分配不同的颜色。然后双重图案化层上的形状沿着布线网格以不同颜色的网格线之间交替的方式布线。通过以这种方式进行布线，减少了由掩模未对准引起的电容耦合的变化。

7. 发明申请

US20140028407A1 Reconfigurable and Auto-Reconfigurable Resonant Clock 有权
标题翻译：可重构和自动重新配置的谐振时钟
公开(公告)号：US20140028407A1
公开(公告)日：2014-01-30
申请号：US13558670
申请日：2012-07-26
申请人： Chan-Hong Chern , Tao Wen Chung , Chih-Chang Lin , Ming-Chieh Huang , Tsung-Ching Huang , Fu-Lung Hsueh
发明人： Chan-Hong Chern , Tao Wen Chung , Chih-Chang Lin , Ming-Chieh Huang , Tsung-Ching Huang , Fu-Lung Hsueh
IPC分类号： H03B5/12
CPC分类号： G06F1/10 , H03B5/12 , H03B5/32 , H03K5/15
摘要： The present disclosure relates to a resonant clock system having a driver component, a clock load capacitor, and a reconfigurable inductor array. The driver component generates a driven input signal. The clock load capacitor is configured to receive the driven input signal. The inductor array is configured to have an effective inductance according to a selected frequency. The inductor array also generates a resonant signal at the selected frequency using the effective inductance.
摘要翻译：本公开涉及具有驱动器部件，时钟负载电容器和可重构电感器阵列的谐振时钟系统。驱动器组件产生驱动输入信号。时钟负载电容器被配置为接收驱动输入信号。电感器阵列被配置为具有根据选定频率的有效电感。电感器阵列还使用有效电感在选定频率处产生谐振信号。

8. 发明授权

US08610421B2 Current generator and method of operating 有权
标题翻译：电流发生器和操作方法
公开(公告)号：US08610421B2
公开(公告)日：2013-12-17
申请号：US12976504
申请日：2010-12-22
申请人： Ming-Chieh Huang , Chan-Hong Chern , Chih-Chang Lin
发明人： Ming-Chieh Huang , Chan-Hong Chern , Chih-Chang Lin
IPC分类号： G05F1/648
CPC分类号： G05F1/648 , G11C5/147 , H02M3/158
摘要： A current generator includes an op-amp having a negative terminal arranged to be coupled to an input voltage, a resistance selection circuit having at least one tunable resistor connected with each other, and at least one power transistor. A gate of the at least one power transistor is coupled to an output of the op-amp, and a drain of the at least one power transistor is coupled to the at least one tunable resistor or a load. The resistance selection circuit is configured to select a node of the at least one tunable resistor based on the input voltage for coupling from a positive terminal of the op-amp. The at least one tunable resistor is configured to adjust a resistance setting to control a current level of the current generator based on a power supply voltage or a current of a reference resistor.
摘要翻译：电流发生器包括具有布置为耦合到输入电压的负极端子的运算放大器，具有彼此连接的至少一个可调电阻器的电阻选择电路和至少一个功率晶体管。所述至少一个功率晶体管的栅极耦合到所述运算放大器的输出，并且所述至少一个功率晶体管的漏极耦合到所述至少一个可调电阻器或负载。电阻选择电路被配置为基于用于从运算放大器的正极端子耦合的输入电压来选择至少一个可调电阻器的节点。所述至少一个可调电阻器被配置为基于电源电压或参考电阻器的电流来调整电阻设置以控制电流发生器的电流水平。

9. 发明授权

US08369172B2 Integrated circuits for providing clock periods and operating methods thereof 有权
标题翻译：用于提供时钟周期的集成电路及其操作方法
公开(公告)号：US08369172B2
公开(公告)日：2013-02-05
申请号：US12844204
申请日：2010-07-27
申请人： Chiang Pu , Ming-Chieh Huang , Chan-Hong Chern
发明人： Chiang Pu , Ming-Chieh Huang , Chan-Hong Chern
IPC分类号： G11C7/00
CPC分类号： G05F1/10 , G11C7/22 , G11C7/222 , G11C11/406 , G11C11/40615 , G11C11/40626 , G11C2211/4065
摘要： An integrated circuit includes a capacitor. A switch is electrically coupled with the capacitor in a parallel fashion. A comparator includes a first input node, a second input node, and an output node. The second input node is electrically coupled with a first plate of the capacitor. The output node is electrically coupled with the switch. A transistor is electrically coupled with a second plate of the capacitor. A circuit is electrically coupled with a gate of the transistor. The circuit is configured to provide a bias voltage to the gate of the transistor so as to control a current that is supplied to charge the capacitor.
摘要翻译：集成电路包括电容器。开关以并联方式与电容器电耦合。比较器包括第一输入节点，第二输入节点和输出节点。第二输入节点与电容器的第一板电耦合。输出节点与开关电耦合。晶体管与电容器的第二板电耦合。电路与晶体管的栅极电耦合。电路被配置为向晶体管的栅极提供偏置电压，以便控制供给电容器充电的电流。

10. 发明申请

US20120182058A1 NEGATIVE CHARGE PUMP 有权
标题翻译：负电荷泵
公开(公告)号：US20120182058A1
公开(公告)日：2012-07-19
申请号：US13005643
申请日：2011-01-13
申请人： Tien-Chun Yang , Yvonne Lin , Ming-Chieh Huang
发明人： Tien-Chun Yang , Yvonne Lin , Ming-Chieh Huang
IPC分类号： H03K3/00 , G05F1/10
CPC分类号： H03K5/15013 , H02M3/07 , H02M2003/071
摘要： A charge pump includes a first node configured to receive a first voltage and a second node coupled to the first node through a first transistor. The second node is configured to output a voltage having a greater voltage magnitude than the first voltage. A first capacitor is coupled to a third node, and a fourth node is configured to receive a first clock signal. The third node is disposed between a drain of the first transistor and the fourth node. A leaky circuit device is coupled in parallel with the first capacitor for draining charges of a first polarity away from the second node.
摘要翻译：电荷泵包括被配置为通过第一晶体管接收耦合到第一节点的第一电压和第二节点的第一节点。第二节点被配置为输出具有比第一电压更大的电压幅度的电压。第一电容器耦合到第三节点，并且第四节点被配置为接收第一时钟信号。第三节点设置在第一晶体管的漏极和第四节点之间。泄漏电路装置与第一电容并联耦合，用于从第二节点排出第一极性的电荷。

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