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1. 发明授权

US08816732B2 Capactive load PLL with calibration loop 有权
标题翻译：带校准回路的负载负载PLL
公开(公告)号：US08816732B2
公开(公告)日：2014-08-26
申请号：US13530136
申请日：2012-06-22
申请人： Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin , Tsung-Ching Huang , Fu-Lung Hsueh
发明人： Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin , Tsung-Ching Huang , Fu-Lung Hsueh
IPC分类号： H03L7/06
CPC分类号： H03L7/103 , H03L7/097 , H03L7/0995 , H03L7/1072 , H03L7/18 , H03L2207/06
摘要： A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.
摘要翻译：电路包括电容负载压控振荡器，其具有被配置为接收第一输入信号的输入和被配置为输出振荡输出信号的输出。校准电路耦合到压控振荡器，并被配置为将一个或多个控制信号输出到电容负载压控振荡器，用于调整振荡输出信号的频率。校准电路被配置为响应于输入电压与至少一个参考电压的比较而输出一个或多个控制信号。

2. 发明申请

US20140028407A1 Reconfigurable and Auto-Reconfigurable Resonant Clock 有权
标题翻译：可重构和自动重新配置的谐振时钟
公开(公告)号：US20140028407A1
公开(公告)日：2014-01-30
申请号：US13558670
申请日：2012-07-26
申请人： Chan-Hong Chern , Tao Wen Chung , Chih-Chang Lin , Ming-Chieh Huang , Tsung-Ching Huang , Fu-Lung Hsueh
发明人： Chan-Hong Chern , Tao Wen Chung , Chih-Chang Lin , Ming-Chieh Huang , Tsung-Ching Huang , Fu-Lung Hsueh
IPC分类号： H03B5/12
CPC分类号： G06F1/10 , H03B5/12 , H03B5/32 , H03K5/15
摘要： The present disclosure relates to a resonant clock system having a driver component, a clock load capacitor, and a reconfigurable inductor array. The driver component generates a driven input signal. The clock load capacitor is configured to receive the driven input signal. The inductor array is configured to have an effective inductance according to a selected frequency. The inductor array also generates a resonant signal at the selected frequency using the effective inductance.
摘要翻译：本公开涉及具有驱动器部件，时钟负载电容器和可重构电感器阵列的谐振时钟系统。驱动器组件产生驱动输入信号。时钟负载电容器被配置为接收驱动输入信号。电感器阵列被配置为具有根据选定频率的有效电感。电感器阵列还使用有效电感在选定频率处产生谐振信号。

3. 发明授权

US08847652B2 Reconfigurable and auto-reconfigurable resonant clock 有权
标题翻译：可重构和自动重构谐振时钟
公开(公告)号：US08847652B2
公开(公告)日：2014-09-30
申请号：US13558670
申请日：2012-07-26
申请人： Chan-Hong Chern , Tao Wen Chung , Chih-Chang Lin , Ming-Chieh Huang , Tsung-Ching Huang , Fu-Lung Hsueh
发明人： Chan-Hong Chern , Tao Wen Chung , Chih-Chang Lin , Ming-Chieh Huang , Tsung-Ching Huang , Fu-Lung Hsueh
IPC分类号： G06F1/10 , H03K5/15
CPC分类号： G06F1/10 , H03B5/12 , H03B5/32 , H03K5/15
摘要： The present disclosure relates to a resonant clock system having a driver component, a clock load capacitor, and a reconfigurable inductor array. The driver component generates a driven input signal. The clock load capacitor is configured to receive the driven input signal. The inductor array is configured to have an effective inductance according to a selected frequency. The inductor array also generates a resonant signal at the selected frequency using the effective inductance.
摘要翻译：本公开涉及具有驱动器部件，时钟负载电容器和可重构电感器阵列的谐振时钟系统。驱动器组件产生驱动输入信号。时钟负载电容器被配置为接收驱动输入信号。电感器阵列被配置为具有根据选定频率的有效电感。电感器阵列还使用有效电感在选定频率处产生谐振信号。

4. 发明申请

US20140038085A1 Automatic Misalignment Balancing Scheme for Multi-Patterning Technology 有权
标题翻译：多图案化技术的自动对准平衡方案
公开(公告)号：US20140038085A1
公开(公告)日：2014-02-06
申请号：US13562436
申请日：2012-07-31
申请人： Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin , Tsung-Ching (Jim) Huang , Fu-Lung Hsueh
发明人： Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin , Tsung-Ching (Jim) Huang , Fu-Lung Hsueh
IPC分类号： G06F17/50 , G03F1/68
CPC分类号： G03F7/70466 , G03F7/70433 , G06F17/5077
摘要： Some aspects of the present disclosure provide for a method of automatically balancing mask misalignment for multiple patterning layers to minimize the consequences of mask misalignment. In some embodiments, the method defines a routing grid for one or more double patterning layers within an IC layout. The routing grid has a plurality of vertical grid lines extending along a first direction and a plurality of horizontal grid lines extending along a second, orthogonal direction. Alternating lines of the routing grid in a given direction (e.g., the horizontal and vertical direction) are assigned different colors. Shapes on the double patterning layers are then routed along the routing grid in a manner that alternates between different colored grid lines. By routing in such a manner, variations in capacitive coupling caused by mask misalignment are reduced.
摘要翻译：本公开的一些方面提供了一种自动平衡多个图案化层的掩模未对准的方法，以最小化掩模未对准的后果。在一些实施例中，该方法定义了IC布局内的一个或多个双图案化层的布线网格。路由网格具有沿着第一方向延伸的多个垂直网格线和沿着第二正交方向延伸的多个水平网格线。在给定方向（例如，水平和垂直方向）上布线网格的交替线被分配不同的颜色。然后双重图案化层上的形状沿着布线网格以不同颜色的网格线之间交替的方式布线。通过以这种方式进行布线，减少了由掩模未对准引起的电容耦合的变化。

5. 发明授权

US08709684B2 Automatic misalignment balancing scheme for multi-patterning technology 有权
标题翻译：多图案化技术的自动对准平衡方案
公开(公告)号：US08709684B2
公开(公告)日：2014-04-29
申请号：US13562436
申请日：2012-07-31
申请人： Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin , Tsung-Ching (Jim) Huang , Fu-Lung Hsueh
发明人： Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin , Tsung-Ching (Jim) Huang , Fu-Lung Hsueh
IPC分类号： G03F1/68
CPC分类号： G03F7/70466 , G03F7/70433 , G06F17/5077
摘要： Some aspects of the present disclosure provide for a method of automatically balancing mask misalignment for multiple patterning layers to minimize the consequences of mask misalignment. In some embodiments, the method defines a routing grid for one or more double patterning layers within an IC layout. The routing grid has a plurality of vertical grid lines extending along a first direction and a plurality of horizontal grid lines extending along a second, orthogonal direction. Alternating lines of the routing grid in a given direction (e.g., the horizontal and vertical direction) are assigned different colors. Shapes on the double patterning layers are then routed along the routing grid in a manner that alternates between different colored grid lines. By routing in such a manner, variations in capacitive coupling caused by mask misalignment are reduced.
摘要翻译：本公开的一些方面提供了一种自动平衡多个图案化层的掩模未对准的方法，以最小化掩模未对准的后果。在一些实施例中，该方法定义了IC布局内的一个或多个双图案化层的布线网格。路由网格具有沿着第一方向延伸的多个垂直网格线和沿着第二正交方向延伸的多个水平网格线。在给定方向（例如，水平和垂直方向）上布线网格的交替线被分配不同的颜色。然后双重图案化层上的形状沿着布线网格以不同颜色的网格线之间交替的方式布线。通过以这种方式进行布线，减少了由掩模未对准引起的电容耦合的变化。

6. 发明授权

US08698566B2 Phase locked loop calibration 有权
标题翻译：锁相环校准
公开(公告)号：US08698566B2
公开(公告)日：2014-04-15
申请号：US13252498
申请日：2011-10-04
申请人： Chan-Hong Chern , Ming-Chieh Huang , Tao Wen Chung , Chih-Chang Lin , Fu-Lung Hsueh , Yuwen Swei
发明人： Chan-Hong Chern , Ming-Chieh Huang , Tao Wen Chung , Chih-Chang Lin , Fu-Lung Hsueh , Yuwen Swei
IPC分类号： H03L7/085 , H03L7/10 , H03B5/12
CPC分类号： H03L7/102 , H03L7/099 , H03L2207/06
摘要： An inductor-capacitor phase locked loop (LCPLL) includes an inductor-capacitor voltage controlled oscillator (LCVCO) that provides an output frequency. A calibration circuit includes two comparators and provides a coarse tune signal to the LCVCO. The two comparators respectively compare the loop filter signal with a first reference voltage and a second reference voltage that is higher than the first reference voltage to supply a first and second comparator output, respectively. The calibration circuit is capable of adjusting the coarse tune signal continuously in voltage values and adjusts the coarse tune signal based on the two comparator outputs. A loop filter provides a loop filter signal to the calibration circuit and a fine tune signal to the LCVCO. A coarse tune frequency range is greater than a fine tune frequency range.
摘要翻译：电感 - 电容器锁相环（LCPLL）包括提供输出频率的电感 - 电容压控振荡器（LCVCO）。校准电路包括两个比较器，并向LCVCO提供粗调信号。两个比较器分别将环路滤波器信号与第一参考电压和高于第一参考电压的第二参考电压进行比较，以分别提供第一和第二比较器输出。校准电路能够在电压值中连续调整粗调信号，并根据两个比较器输出调整粗调信号。环路滤波器向校准电路提供环路滤波器信号，并向LCVCO提供微调信号。粗调频率范围大于微调频率范围。

7. 发明授权

US08432204B1 Current-controlled oscillator (CCO) based PLL 有权
标题翻译：基于电流控制振荡器（CCO）的PLL
公开(公告)号：US08432204B1
公开(公告)日：2013-04-30
申请号：US13344637
申请日：2012-01-06
申请人： Chan-Hong Chern , Ming-Chieh Huang , Tao Wen Chung , Chih-Chang Lin , Yuwen Swei , Fu-Lung Hsueh
发明人： Chan-Hong Chern , Ming-Chieh Huang , Tao Wen Chung , Chih-Chang Lin , Yuwen Swei , Fu-Lung Hsueh
IPC分类号： H03L7/06
CPC分类号： H03L7/102 , H03L7/099 , H03L7/104
摘要： A PLL circuit includes a phase frequency detector; a programmable charge pump coupled to an output of the phase frequency detector; a loop filter coupled to an output of the charge pump, the loop filter providing a fine tuning voltage; a first voltage-to-current converter, the first voltage-to-current converter providing a fine tuning current corresponding to the fine tuning voltage; a current-controlled oscillator (CCO); a feedback divider coupled to an output of the CCO and an input of the phase frequency detector; and an analog calibration circuit. The analog calibration circuit provides a coarse adjustment current for coarse adjustments to a frequency pivot point for an oscillator frequency of the CCO, wherein the CCO generates a frequency signal at an output responsive to a summed coarse adjustment and fine tuning current, wherein the frequency pivot point is continuously adjustable.
摘要翻译： PLL电路包括相位检波器; 耦合到所述相位频率检测器的输出的可编程电荷泵; 耦合到电荷泵的输出的环路滤波器，所述环路滤波器提供微调电压; 第一电压 - 电流转换器，第一电压 - 电流转换器提供对应于微调电压的微调电流; 电流控制振荡器（CCO）; 耦合到CCO的输出的反馈分压器和相位频率检测器的输入端; 和模拟校准电路。模拟校准电路提供用于对CCO的振荡器频率的频率枢转点进行粗调整的粗调电流，其中CCO响应于总和的粗调和微调电流而在输出端产生频率信号，其中频率枢轴点连续可调。

8. 发明授权

US08872592B2 High-speed transimpedance amplifier 有权
标题翻译：高速互阻放大器
公开(公告)号：US08872592B2
公开(公告)日：2014-10-28
申请号：US13527365
申请日：2012-06-19
申请人： Tsung-Ching Huang , Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin
发明人： Tsung-Ching Huang , Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin
IPC分类号： H03F3/08
CPC分类号： H03F3/082 , H03F1/0205 , H03F3/08 , H03F3/3022 , H03F3/45179 , H03F3/45183 , H03F2200/216 , H03F2203/30031 , H03F2203/45222 , H03F2203/45644 , H03F2203/45686 , H03F2203/45702 , H03F2203/45724
摘要： A transimpedance amplifier includes a first inverter having a first input node and a first output node. The first input node is configured to be coupled to an input signal. A second inverter has a second input node and a second output node. The second input node is configured to receive a reference voltage terminal. The first inverter and the second inverter are configured to provide a differential output voltage signal between the first output node and the second output node.
摘要翻译：跨阻放大器包括具有第一输入节点和第一输出节点的第一反相器。第一输入节点被配置为耦合到输入信号。第二反相器具有第二输入节点和第二输出节点。第二输入节点被配置为接收参考电压端子。第一反相器和第二反相器被配置为在第一输出节点和第二输出节点之间提供差分输出电压信号。

9. 发明授权

US08862951B2 Decision feedback equalizer 有权
标题翻译：决策反馈均衡器
公开(公告)号：US08862951B2
公开(公告)日：2014-10-14
申请号：US13528877
申请日：2012-06-21
申请人： Ming-Chieh Huang , Chan-Hong Chern , Tao Wen Chung , Yuwen Swei , Chih-Chang Lin , Tsung-Ching Huang
发明人： Ming-Chieh Huang , Chan-Hong Chern , Tao Wen Chung , Yuwen Swei , Chih-Chang Lin , Tsung-Ching Huang
IPC分类号： G06F11/00 , H04L27/01
CPC分类号： H04L25/03057 , H04L25/06 , H04L25/08
摘要： A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.
摘要翻译：电路包括用于接收输入数据信号和包括先前数据位的反馈信号的求和电路。求和电路被配置为将调节的输入数据信号输出到时钟和数据恢复电路。第一触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第一比特组和具有小于输入数据信号的频率的频率的第一时钟信号由第一求和电路接收。第二触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第二组比特和具有小于输入数据信号的频率的频率的第二时钟信号由第一求和电路接收。

10. 发明授权

US09722818B2 Decision feedback equalizer summation circuit 有权
公开(公告)号：US09722818B2
公开(公告)日：2017-08-01
申请号：US14492237
申请日：2014-09-22
申请人： Ming-Chieh Huang , Chan-Hong Chern , Tao Wen Chung , Yuwen Swei , Chih-Chang Lin , Tsung-Ching Huang
发明人： Ming-Chieh Huang , Chan-Hong Chern , Tao Wen Chung , Yuwen Swei , Chih-Chang Lin , Tsung-Ching Huang
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159 , H04L25/03 , H04L25/06 , H04L25/08
CPC分类号： H04L25/03057 , H04L25/06 , H04L25/08
摘要： A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.

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