专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08241928B2 Test structure and method for detecting charge effects during semiconductor processing 有权
标题翻译：用于在半导体处理期间检测电荷效应的测试结构和方法
公开(公告)号：US08241928B2
公开(公告)日：2012-08-14
申请号：US12777858
申请日：2010-05-11
申请人： Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
发明人： Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
IPC分类号： H01L21/66
CPC分类号： H01L22/34 , H01L2224/73204 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor process test structure comprises an electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. Gate-induced drain leakage (GIDL) measurement techniques can then be used to characterize the charging status of the test structure.
摘要翻译：半导体工艺测试结构包括电极，电荷俘获层和扩散区域。测试结构是电容器状结构，其中电荷捕获层将在各种处理步骤期间捕获电荷。然后可以使用栅极漏极泄漏（GIDL）测量技术来表征测试结构的充电状态。

2. 发明授权

US07608886B2 Systems and methods for a high density, compact memory array 有权
标题翻译：用于高密度，紧凑型存储器阵列的系统和方法
公开(公告)号：US07608886B2
公开(公告)日：2009-10-27
申请号：US11327792
申请日：2006-01-06
申请人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
发明人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , G11C16/0475 , H01L27/11568 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array.
摘要翻译：包括垂直存储单元的存储器阵列不需要单元之间的任何隔离层。因此，可以实现非常紧凑，高密度的存储器阵列。存储器阵列中的每个存储单元被配置为存储每个单元的4位数据。可以使用多电平充电技术来增加每个电池的位数，并实现更高密度的存储器阵列。

3. 发明授权

US08178407B2 Systems and methods for a high density, compact memory array 有权
标题翻译：用于高密度，紧凑型存储器阵列的系统和方法
公开(公告)号：US08178407B2
公开(公告)日：2012-05-15
申请号：US12561395
申请日：2009-09-17
申请人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
发明人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , G11C16/0475 , H01L27/11568 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi-level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array.
摘要翻译：包括垂直存储单元的存储器阵列不需要单元之间的任何隔离层。因此，可以实现非常紧凑，高密度的存储器阵列。存储器阵列中的每个存储单元被配置为存储每个单元的4位数据。可以使用多电平充电技术来增加每个单元的位数，并实现对存储器阵列的进一步增加的密度。

4. 发明授权

US07817472B2 Operating method of memory device 有权
标题翻译：存储器件的操作方法
公开(公告)号：US07817472B2
公开(公告)日：2010-10-19
申请号：US12169155
申请日：2008-07-08
申请人： Ming-Chang Kuo , Ming-Hsiu Lee , Chao-I Wu
发明人： Ming-Chang Kuo , Ming-Hsiu Lee , Chao-I Wu
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , G11C16/10 , G11C16/14
摘要： An operating method of a memory array is provided. The operating method includes performing a programming operation. The programming operation is performed by applying a first voltage to a bit line of the memory array and a second voltage to a plurality of word lines of the memory array to cause simultaneously programming a plurality of selected memory cells in the memory array.
摘要翻译：提供了一种存储器阵列的操作方法。操作方法包括执行编程操作。通过将第一电压施加到存储器阵列的位线并将第二电压施加到存储器阵列的多个字线来执行编程操作，以同时对存储器阵列中的多个选择的存储器单元进行编程。

5. 发明授权

US07787294B2 Operating method of memory 有权
标题翻译：记忆的操作方法
公开(公告)号：US07787294B2
公开(公告)日：2010-08-31
申请号：US12031189
申请日：2008-02-14
申请人： Ming-Chang Kuo , Ming-Hsiu Lee
发明人： Ming-Chang Kuo , Ming-Hsiu Lee
IPC分类号： G11C16/04
CPC分类号： G11C11/5671 , G11C16/0466 , G11C16/0475 , G11C16/0491
摘要： An operating method of a memory is provided. The memory includes a memory cell array composed of a plurality of memory cells, a plurality of bit lines, and a plurality of word lines. During programming the memory, a column of memory cells is selected. A voltage difference is respectively occurred between a bit line corresponding to first source/drain regions of the memory cells in the selected column and adjacent two bit lines, and a bias is respectively applied to a word line corresponding to a control gate of each memory cell in the selected column so as to allow a data bit of the memory cell at a plurality of predetermined programmed states and an unusable bit of each memory cell in an adjacent column which shares the same bit line with the selected column at an unusable state.
摘要翻译：提供了一种存储器的操作方法。存储器包括由多个存储单元，多个位线和多个字线组成的存储单元阵列。在编程存储器期间，选择一列存储单元。在对应于所选列的存储单元的第一源极/漏极区域和相邻的两个位线的位线之间分别产生电压差，偏置分别施加到与每个存储单元的控制栅极相对应的字线在所选择的列中，以允许存储器单元的数据位处于多个预定编程状态，并且在相邻列中的每个存储器单元的不可用位与所选择的列共享与不可用状态相同的位线。

6. 发明申请

US20090207658A1 OPERATING METHOD OF MEMORY DEVICE 有权
标题翻译：存储器件的操作方法
公开(公告)号：US20090207658A1
公开(公告)日：2009-08-20
申请号：US12169155
申请日：2008-07-08
申请人： Ming-Chang Kuo , Ming-Hsiu Lee , Chao-I Wu
发明人： Ming-Chang Kuo , Ming-Hsiu Lee , Chao-I Wu
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0416 , G11C16/10 , G11C16/14
摘要： An operating method of a memory array is provided. The operating method includes performing a programming operation. The programming operation is performed by applying a first voltage to a bit line of the memory array and a second voltage to a plurality of word lines of the memory array to cause simultaneously programming a plurality of selected memory cells in the memory array
摘要翻译：提供了一种存储器阵列的操作方法。操作方法包括执行编程操作。通过将第一电压施加到存储器阵列的位线并将第二电压施加到存储器阵列的多个字线来执行编程操作，以同时编程存储器阵列中的多个选择的存储器单元

7. 发明申请

US20090207656A1 OPERATING METHOD OF MEMORY 有权
标题翻译：存储器的操作方法
公开(公告)号：US20090207656A1
公开(公告)日：2009-08-20
申请号：US12031189
申请日：2008-02-14
申请人： Ming-Chang Kuo , Ming-Hsiu Lee
发明人： Ming-Chang Kuo , Ming-Hsiu Lee
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5671 , G11C16/0466 , G11C16/0475 , G11C16/0491
摘要： An operating method of a memory is provided. The memory includes a memory cell array composed of a plurality of memory cells, a plurality of bit lines, and a plurality of word lines. During programming the memory, a column of memory cells is selected. A voltage difference is respectively occurred between a bit line corresponding to first source/drain regions of the memory cells in the selected column and adjacent two bit lines, and a bias is respectively applied to a word line corresponding to a control gate of each memory cell in the selected column so as to allow a data bit of the memory cell at a plurality of predetermined programmed states and an unusable bit of each memory cell in an adjacent column which shares the same bit line with the selected column at an unusable state.
摘要翻译：提供了一种存储器的操作方法。存储器包括由多个存储单元，多个位线和多个字线组成的存储单元阵列。在编程存储器期间，选择一列存储单元。在对应于所选列的存储单元的第一源极/漏极区域和相邻的两个位线的位线之间分别产生电压差，偏置分别施加到与每个存储单元的控制栅极相对应的字线在所选择的列中，以允许存储器单元的数据位处于多个预定编程状态，并且在相邻列中的每个存储器单元的不可用位与所选择的列共享与不可用状态相同的位线。

8. 发明申请

US20080023699A1 A TEST STRUCTURE AND METHOD FOR DETECTING CHARGE EFFECTS DURING SEMICONDUCTOR PROCESSING 审中-公开
标题翻译：用于检测半导体加工过程中的充电效应的测试结构和方法
公开(公告)号：US20080023699A1
公开(公告)日：2008-01-31
申请号：US11460209
申请日：2006-07-26
申请人： Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
发明人： Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
IPC分类号： H01L23/58
CPC分类号： H01L22/34 , H01L2224/73204 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor process test structure comprises an electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. Gate-induced drain leakage (GIDL) measurement techniques can then be used to characterize the charging status of the test structure.
摘要翻译：半导体工艺测试结构包括电极，电荷俘获层和扩散区域。测试结构是电容器状结构，其中电荷捕获层将在各种处理步骤期间捕获电荷。然后可以使用栅极漏极泄漏（GIDL）测量技术来表征测试结构的充电状态。

9. 发明申请

US20070236237A1 A TEST STRUCTURE AND METHOD FOR DETECTING CHARGE EFFECTS DURING SEMICONDUCTOR PROCESSING USING A DELAYED INVERSION POINT TECHNIQUE 有权
标题翻译：使用延迟反转点技术在半导体处理期间检测充电效应的测试结构和方法
公开(公告)号：US20070236237A1
公开(公告)日：2007-10-11
申请号：US11279224
申请日：2006-04-10
申请人： Ming-Chang Kuo , Ming-Hsiu Lee , Chao-l Wu
发明人： Ming-Chang Kuo , Ming-Hsiu Lee , Chao-l Wu
IPC分类号： G01R31/26
CPC分类号： H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor process test structure comprises a gate electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. A CV measurement can then be used to detect whether a Vfb shift has occurred. If the process step resulted in a charge effect, then the induced charge will not be uniform. If the charging of the test structure is not uniform, then there will not be a Vfb shift. A delayed inversion point technique can then be used to monitor the charging status.
摘要翻译：半导体工艺测试结构包括栅电极，电荷捕获层和扩散区。测试结构是电容器状结构，其中电荷捕获层将在各种处理步骤期间捕获电荷。然后可以使用CV测量来检测是否发生了Vfb偏移。如果处理步骤导致电荷效应，则感应电荷将不均匀。如果测试结构的充电不均匀，则不会有Vfb偏移。然后可以使用延迟反转点技术来监视充电状态。

10. 发明申请

US20070161193A1 Systems and methods for a high density, compact memory array 有权
标题翻译：用于高密度，紧凑型存储器阵列的系统和方法
公开(公告)号：US20070161193A1
公开(公告)日：2007-07-12
申请号：US11327792
申请日：2006-01-06
申请人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
发明人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , G11C16/0475 , H01L27/11568 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi-level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array.
摘要翻译：包括垂直存储单元的存储器阵列不需要单元之间的任何隔离层。因此，可以实现非常紧凑，高密度的存储器阵列。存储器阵列中的每个存储单元被配置为存储每个单元的4位数据。可以使用多电平充电技术来增加每个单元的位数，并实现对存储器阵列的进一步增加的密度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式