专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5840602A Methods of forming nonmonocrystalline silicon-on-insulator thin-film transistors 失效
标题翻译：形成非晶硅绝缘体上薄膜晶体管的方法
公开(公告)号：US5840602A
公开(公告)日：1998-11-24
申请号：US686242
申请日：1996-07-25
申请人： Min-Koo Han , Byung-Hyuk Min , Cheol-Min Park , Byung-Seong Bae
发明人： Min-Koo Han , Byung-Hyuk Min , Cheol-Min Park , Byung-Seong Bae
IPC分类号： H01L29/786 , H01L21/77 , H01L21/84 , H01L27/12 , H01L21/8238
CPC分类号： H01L27/1214
摘要： Methods of forming thin-film transistors include the steps of forming an amorphous silicon (a-Si) layer of predetermined conductivity type on a face of an electrically insulating substrate and then forming a first insulating layer on the amorphous silicon layer. The first insulating layer and amorphous silicon layer are then patterned to define spaced amorphous source and drain regions having exposed sidewalls. An amorphous silicon channel region is then deposited in the space between the source and drain regions and in contact with the sidewalls thereof. An annealing step is then performed to convert the amorphous source, drain and channel regions to polycrystalline silicon, prior to the step of forming an insulated gate electrode on the channel region.
摘要翻译：形成薄膜晶体管的方法包括以下步骤：在电绝缘基板的表面上形成预定导电类型的非晶硅（a-Si）层，然后在非晶硅层上形成第一绝缘层。然后对第一绝缘层和非晶硅层进行构图以限定具有暴露的侧壁的间隔开的无定形源极和漏极区域。然后在源区和漏区之间的空间中沉积非晶硅沟道区，并与其侧壁接触。然后在通道区域上形成绝缘栅电极的步骤之前，执行退火步骤以将非晶硅源，漏极和沟道区域转换为多晶硅。

2. 发明授权

US5804837A Polysilicon thin-film transistor and method for fabricating the same 失效
标题翻译：多晶硅薄膜晶体管及其制造方法
公开(公告)号：US5804837A
公开(公告)日：1998-09-08
申请号：US687630
申请日：1996-07-26
申请人： Min-Koo Han , Byung-Hyuk Min , Cheol-Min Park
发明人： Min-Koo Han , Byung-Hyuk Min , Cheol-Min Park
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/786 , H01L29/76 , H01L31/036 , H01L31/112
CPC分类号： H01L29/42384 , H01L21/28105 , H01L29/4908 , H01L29/4983 , H01L29/6675 , H01L29/66757 , H01L29/78621
摘要： To accomplish the objects of the present invention, among others, the present invention provides a thin-film transistor that has a channel region operatively having an offset region only during turn-off. Source and drain regions self-aligned with different ends of the channel region. A gate region is formed on a gate insulating layer disposed over the channel region and has a main gate accepting a gate voltage, a subgate which comes into ohmic contact with the source region, and a junction gate for forming a rectifying junction between the main gate and subgate.
摘要翻译：为了实现本发明的目的，除其他之外，本发明提供一种薄膜晶体管，其具有仅在关断期间可操作地具有偏移区域的沟道区。源极和漏极区域与通道区域的不同端部自对准。栅极区域形成在栅极绝缘层上，栅极绝缘层设置在沟道区上方，并且具有接受栅极电压的主栅极，与源极区域欧姆接触的子栅极和用于在主栅极之间形成整流结的结栅极和subgate。

3. 发明授权

US5920085A Multiple floating gate field effect transistors and methods of operating same 失效
标题翻译：多个浮栅场效应晶体管及其工作方式相同
公开(公告)号：US5920085A
公开(公告)日：1999-07-06
申请号：US104585
申请日：1998-06-25
申请人： Min-Koo Han , Byung-Hyuk Min , Cheol-Min Park , Keun-Ho Jang , Jae-Hong Jun
发明人： Min-Koo Han , Byung-Hyuk Min , Cheol-Min Park , Keun-Ho Jang , Jae-Hong Jun
IPC分类号： H01L21/28 , H01L29/788 , H04L29/788
CPC分类号： H01L29/788 , H01L21/28273
摘要： A field effect transistor includes laterally spaced apart source and drain regions in a substrate, laterally spaced apart undoped regions in the substrate between the laterally spaced apart source and drain regions, a doped channel region in the substrate between the laterally spaced apart undoped regions, and a gate insulating layer on the substrate. A main gate is on the gate insulating layer opposite the channel, and first and second sub gates are on the gate insulating layer, a respective one of which is opposite a respective one of the spaced apart undoped regions. The first and second sub gates are laterally spaced apart from and electrically insulated from the main gate. The transistor may be formed by patterning a photoresist layer and a gate layer to form a main gate and first and second sub gates, reflowing the photoresist into the lateral space between the main gate and the first and second sub gates, etching the gate insulating layer using the reflowed photoresist as a mask, and implanting ions into the substrate to form source and drain regions using the etched gate insulating layer as a mask.
摘要翻译：场效应晶体管包括在衬底中的横向间隔开的源极和漏极区域，在横向间隔开的源极和漏极区域之间的衬底中横向间隔开的未掺杂区域，在横向间隔开的未掺杂区域之间的衬底中的掺杂沟道区域，以及基板上的栅极绝缘层。主栅极在与沟道相对的栅极绝缘层上，第一和第二子栅极位于栅极绝缘层上，其相应的一个与相应的一个间隔开的未掺杂区域相对。第一和第二子门与主门横向间隔开并与之绝缘。可以通过图案化光致抗蚀剂层和栅极层来形成晶体管，以形成主栅极和第一和第二子栅极，将光致抗蚀剂回流到主栅极和第一和第二子栅极之间的横向空间中，蚀刻栅极绝缘层使用回流光致抗蚀剂作为掩模，并且使用蚀刻的栅绝缘层作为掩模将离子注入到衬底中以形成源区和漏区。

4. 发明授权

US5793058A Multi-gate offset source and drain field effect transistors and methods of operating same 失效
标题翻译：多栅极偏移源极和漏极场效应晶体管及其工作方式相同
公开(公告)号：US5793058A
公开(公告)日：1998-08-11
申请号：US692924
申请日：1996-07-31
申请人： Min-Koo Han , Byung-Hyuk Min , Cheol-Min Park , Keun-Ho Jang , Jae-Hong Jun
发明人： Min-Koo Han , Byung-Hyuk Min , Cheol-Min Park , Keun-Ho Jang , Jae-Hong Jun
IPC分类号： H01L29/70 , H01L21/336 , H01L29/08 , H01L29/78 , H01L29/786 , H01L29/788
CPC分类号： H01L29/6675 , H01L29/0847 , H01L29/7831 , H01L29/7833 , H01L29/78621 , H01L29/78645 , H01L29/788
摘要： A field effect transistor includes laterally spaced apart source and drain regions in a substrate, laterally spaced apart undoped regions in the substrate between the laterally spaced apart source and drain regions, a doped channel region in the substrate between the laterally spaced apart undoped regions, and a gate insulating layer on the substrate. A main gate is on the gate insulating layer opposite the channel, and first and second sub gates are on the gate insulating layer, a respective one of which is opposite a respective one of the spaced apart undoped regions. The first and second sub gates are laterally spaced apart from and electrically insulated from the main gate. The transistor may be formed by patterning a photoresist layer and a gate layer to form a main gate and first and second sub gates, reflowing the photoresist into the lateral space between the main gate and the first and second sub gates, etching the gate insulating layer using the reflowed photoresist as a mask, and implanting ions into the substrate to form source and drain regions using the etched gate insulating layer as a mask.
摘要翻译：场效应晶体管包括在衬底中的横向间隔开的源极和漏极区域，在横向间隔开的源极和漏极区域之间的衬底中横向间隔开的未掺杂区域，在横向间隔开的未掺杂区域之间的衬底中的掺杂沟道区域，以及基板上的栅极绝缘层。主栅极在与沟道相对的栅极绝缘层上，第一和第二子栅极位于栅极绝缘层上，其相应的一个与相应的一个间隔开的未掺杂区域相对。第一和第二子门与主门横向间隔开并与之绝缘。可以通过图案化光致抗蚀剂层和栅极层来形成晶体管，以形成主栅极和第一和第二子栅极，将光致抗蚀剂回流到主栅极和第一和第二子栅极之间的横向空间中，蚀刻栅极绝缘层使用回流光致抗蚀剂作为掩模，并且使用蚀刻的栅绝缘层作为掩模将离子注入到衬底中以形成源区和漏区。

5. 发明授权

US5885859A Methods of fabricating multi-gate, offset source and drain field effect transistors 失效
标题翻译：制造多栅极，偏移源和漏极场效应晶体管的方法
公开(公告)号：US5885859A
公开(公告)日：1999-03-23
申请号：US960631
申请日：1997-10-29
申请人： Min-Koo Han , Byung-Hyuk Min , Cheol-Min Park , Keun-Ho Jang , Jae-Hong Jun
发明人： Min-Koo Han , Byung-Hyuk Min , Cheol-Min Park , Keun-Ho Jang , Jae-Hong Jun
IPC分类号： H01L29/70 , H01L21/336 , H01L29/08 , H01L29/78 , H01L29/786 , H01L29/788 , H01L21/00 , H01L21/84 , H01L21/338 , H01L21/337
CPC分类号： H01L29/6675 , H01L29/0847 , H01L29/7831 , H01L29/7833 , H01L29/78621 , H01L29/78645 , H01L29/788
摘要： A field effect transistor includes laterally spaced apart source and drain regions in a substrate, laterally spaced apart undoped regions in the substrate between the laterally spaced apart source and drain regions, a doped channel region in the substrate between the laterally spaced apart undoped regions, and a gate insulating layer on the substrate. A main gate is on the gate insulating layer opposite the channel, and first and second sub gates are on the gate insulating layer, a respective one of which is opposite a respective one of the spaced apart undoped regions. The first and second sub gates are laterally spaced apart from and electrically insulated from the main gate. The transistor may be formed by patterning a photoresist layer and a gate layer to form a main gate and first and second sub gates, reflowing the photoresist into the lateral space between the main gate and the first and second sub gates, etching the gate insulating layer using the reflowed photoresist as a mask, and implanting ions into the substrate to form source and drain regions using the etched gate insulating layer as a mask.
摘要翻译：场效应晶体管包括在衬底中的横向间隔开的源极和漏极区域，在横向间隔开的源极和漏极区域之间的衬底中横向间隔开的未掺杂区域，在横向间隔开的未掺杂区域之间的衬底中的掺杂沟道区域，以及基板上的栅极绝缘层。主栅极在与沟道相对的栅极绝缘层上，第一和第二子栅极位于栅极绝缘层上，其相应的一个与相应的一个间隔开的未掺杂区域相对。第一和第二子门与主门横向间隔开并与之绝缘。可以通过图案化光致抗蚀剂层和栅极层来形成晶体管，以形成主栅极和第一和第二子栅极，将光致抗蚀剂回流到主栅极和第一和第二子栅极之间的横向空间中，蚀刻栅极绝缘层使用回流光致抗蚀剂作为掩模，并且使用蚀刻的栅绝缘层作为掩模将离子注入到衬底中以形成源区和漏区。

6. 发明授权

US5894157A MOS transistor having an offset resistance derived from a multiple region gate electrode 失效
标题翻译： MOS晶体管具有源自多区域栅电极的偏移电阻
公开(公告)号：US5894157A
公开(公告)日：1999-04-13
申请号：US266420
申请日：1994-06-27
申请人： Min-Koo Han , Byung-Hyuk Min
发明人： Min-Koo Han , Byung-Hyuk Min
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L29/49 , H01L29/786 , H01L29/76
CPC分类号： H01L29/66757 , H01L21/28105 , H01L29/4908 , H01L29/4983 , H01L29/6675 , H01L29/78621
摘要： A method for fabricating a MOS transistor having an offset resistance in a channel region controlled by a gate voltage and structure thereof is disclosed. A gate electrode is divided into three adjacent regions of respectively a second conductivity type, first conductivity type and second conductivity type connected laterally to one another on a channel region. A gate control voltage is applied to a central region of the first conductivity type, and a predetermined voltage between maximum and minimum values of the gate control voltage is applied to left and right adjacent regions of the second conductivity type. If a gate turn-on voltage is applied to the central region the gate turn-on voltage is forward biased to the adjacent left and right regions and is therefore also applied to the forwardly biased left and right regions. The effective length of the gate electrode then becomes the total length of the central region and the left and right adjacent regions. If a gate turn-off voltage is applied to the central region the central region becomes reverse biased with the left and right adjacent regions and thus the effective length of the gate electrode becomes the length of only the central region of the first conductivity type. This reduces the length of the channel region, and thus forms an offset resistance structure which reduces leakage current in the off state of the MOS transistor.
摘要翻译：公开了一种制造具有由栅极电压控制的沟道区域中的偏移电阻的MOS晶体管及其结构的方法。栅极电极被分成在沟道区域上彼此侧向连接的第二导电类型，第一导电类型和第二导电类型的三个相邻区域。栅极控制电压施加到第一导电类型的中心区域，栅极控制电压的最大值和最小值之间的预定电压被施加到第二导电类型的左右相邻区域。如果栅极导通电压施加到中心区域，则栅极导通电压被正向偏置到相邻的左右区域，并且因此也被施加到向前偏置的左右区域。然后，栅电极的有效长度变为中心区域和左右相邻区域的总长度。如果向中心区域施加栅极截止电压，则中心区域与左右相邻区域反向偏置，因此栅电极的有效长度仅成为第一导电类型的中心区域的长度。这减小了沟道区的长度，从而形成了减小MOS晶体管的截止状态下的漏电流的偏移电阻结构。

7. 发明授权

US5593909A Method for fabricating a MOS transistor having an offset resistance 失效
标题翻译：具有偏移电阻的MOS晶体管的制造方法
公开(公告)号：US5593909A
公开(公告)日：1997-01-14
申请号：US467715
申请日：1995-06-06
申请人： Min-Koo Han , Byung-Hyuk Min
发明人： Min-Koo Han , Byung-Hyuk Min
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L29/49 , H01L29/786 , H01L21/265
CPC分类号： H01L29/66757 , H01L21/28105 , H01L29/4908 , H01L29/4983 , H01L29/6675 , H01L29/78621
摘要： A method for fabricating a MOS transistor having an offset resistance in a channel region controlled by a gate voltage and structure thereof is disclosed. A gate electrode is divided into three adjacent regions of respectively a second conductivity type, first conductivity type and second conductivity type connected laterally to one another on a channel region. A gate control voltage is applied to a central region of the first conductivity type, and a predetermined voltage between maximum and minimum values of the gate control voltage is applied to left and right adjacent regions of the second conductivity type. If a gate turn-on voltage is applied to the central region the gate turn-on voltage is forward biased to the adjacent left and right regions and is therefore also applied to the forwardly biased left and right regions. The effective length of the gate electrode then becomes the total length of the central region and the left and right adjacent regions. If a gate turn-off voltage is applied to the central region the central region becomes reverse biased with the and left and right adjacent regions and thus the effective length of the gate electrode becomes the length of only the central region of the first conductivity type. This reduces the length of the channel region, and thus forms an offset resistance structure which reduces leakage current in the off state of the MOS transistor.
摘要翻译：公开了一种制造具有由栅极电压控制的沟道区域中的偏移电阻的MOS晶体管及其结构的方法。栅极电极被分成在沟道区域上彼此侧向连接的第二导电类型，第一导电类型和第二导电类型的三个相邻区域。栅极控制电压施加到第一导电类型的中心区域，栅极控制电压的最大值和最小值之间的预定电压被施加到第二导电类型的左右相邻区域。如果栅极导通电压施加到中心区域，则栅极导通电压被正向偏置到相邻的左右区域，并且因此也被施加到向前偏置的左右区域。然后，栅电极的有效长度变为中心区域和左右相邻区域的总长度。如果向中心区域施加栅极截止电压，则中心区域与左右相邻区域反向偏置，因此栅电极的有效长度变为仅第一导电类型的中心区域的长度。这减小了沟道区的长度，从而形成了减小MOS晶体管的截止状态下的漏电流的偏移电阻结构。

8. 发明授权

US5488005A Process for manufacturing an offset gate structure thin film transistor 失效
标题翻译：用于制造偏移栅结构薄膜晶体管的工艺
公开(公告)号：US5488005A
公开(公告)日：1996-01-30
申请号：US435324
申请日：1995-05-05
申请人： Min-Ku Han , Byung-Hyuk Min
发明人： Min-Ku Han , Byung-Hyuk Min
IPC分类号： H01L29/786 , H01L21/8248 , H01L27/12 , H01L21/86
CPC分类号： H01L21/8248 , Y10S148/15
摘要： A process for manufacturing an offset gate structure thin film transistor which includes the steps of forming a first semiconductor layer, e.g., an active layer made of amorphous silicon or polysilicon, on a major surface of a substrate, e.g., a glass substrate of an LCD, forming a buffer layer on the first semiconductor layer, etching away a first region of the buffer layer and etching a corresponding region of the first semiconductor layer to a predetermined depth, to thereby form a recess and an underlying thin channel region in the first semiconductor layer, the thin channel region having a thickness less than that of the remainder of the first semiconductor layer, forming a second semiconductor layer on the buffer layer and exposed portions of the first semiconductor layer defining the recess, forming a gate insulating layer on the second semiconductor layer, forming a conductive layer on the gate insulating layer, etching the second semiconductor layer, the gate insulating layer, and the conductive layer so as to form a gate electrode structure overlying the thin channel region of the first semiconductor layer and offset resistance regions of the first semiconductor layer disposed on opposite sides of the thin channel region, and, ion-implanting impurities into the first semiconductor layer through exposed portions of the buffer layer disposed on opposite sides of the gate electrode structure, to thereby form source and drain regions on opposite sides of the offset resistance regions of the first semiconductor layer.
摘要翻译：一种偏移栅极结构薄膜晶体管的制造方法，包括以下步骤：在基板的主表面上形成第一半导体层，例如由非晶硅或多晶硅制成的有源层，例如LCD的玻璃基板在所述第一半导体层上形成缓冲层，蚀刻所述缓冲层的第一区域并将所述第一半导体层的对应区域蚀刻到预定深度，从而在所述第一半导体层中形成凹槽和下面的薄沟道区域层，所述薄沟道区的厚度小于所述第一半导体层的剩余部分的厚度，在所述缓冲层上形成第二半导体层，以及限定所述凹部的所述第一半导体层的暴露部分，在所述第二半导体层上形成栅绝缘层半导体层，在栅极绝缘层上形成导电层，蚀刻第二半导体层，栅极绝缘层，以及导电层，以形成覆盖第一半导体层的薄沟道区域和设置在薄沟道区域的相对侧上的第一半导体层的偏移电阻区域的栅电极结构，以及将杂质离子注入第一半导体层半导体层通过设置在栅电极结构的相对侧上的缓冲层的暴露部分，从而在第一半导体层的偏移电阻区域的相对侧上形成源区和漏区。

9. 发明授权

US5283760A Data transmission circuit 失效
标题翻译：数据传输电路
公开(公告)号：US5283760A
公开(公告)日：1994-02-01
申请号：US918615
申请日：1992-07-27
申请人： Dae-Je Chin , Byung-Hyuk Min
发明人： Dae-Je Chin , Byung-Hyuk Min
IPC分类号： G11C11/409 , G11C11/4096 , H01L27/10 , G11C7/00
CPC分类号： G11C11/4096
摘要： A data transmission circuit capable of a high-speed data input/output operation and a large-scaled integration for use in a semiconductor memory device, is disclosed. The data transmission circuit has at least one memory cell 51, a word line 52, a pair of bit lines 65, 66, a sense amplifier 55, and a pair of isolation transistors 53, 54. Further, the circuit includes a pair of common input/output lines 67, 68 for transmitting input or output data with a complementary logic operation, a discharging transistor 56 receiving a control signal at its gate and having a channel connected with a ground voltage node, for transferring an electric potential applied to one end of the channel into the ground voltage level, and a pair of transmission transistors 59, 60 receiving the control signal at their respective gates and having each channel connected with the common input/output lines. Two pairs of input transistors 61, 62 and 63, 64 are connected with the bit lines, their channels each being connected between the bit lines 65, 66 and the transmission transistors 59, 60, their gates each connected with the input/output lines. A pair of output transistors 57, 58 each have a gate electrode connected to the bit lines, and having a channel connected between the channel of the discharging transistor 56 and the channel of the transmission transistors 59, 60. To control electrodes of the discharging transistor 56 and the first and second transmission transistor 59, 60 is applied a column selection line (CSL) signal.
摘要翻译：公开了一种能够在半导体存储器件中使用的高速数据输入/输出操作和大规模集成的数据传输电路。数据传输电路具有至少一个存储单元51，字线52，一对位线65,66，读出放大器55和一对隔离晶体管53,54。此外，该电路包括一对公共输入/输出线67,68，用于传输具有互补逻辑操作的输入或输出数据，放电晶体管56在其栅极处接收控制信号，并具有与接地电压节点连接的通道，用于传送施加到一端的电位以及一对发射晶体管59,60，在其各自的栅极处接收控制信号，并且每个通道与公共输入/输出线连接。两对输入晶体管61,62,63,64与位线连接，它们的通道各自连接在位线65,66和透射晶体管59,60之间，它们的栅极各自与输入/输出线连接。一对输出晶体管57,58各自具有连接到位线的栅电极，并且具有连接在放电晶体管56的沟道和透射晶体管59,60的沟道之间的沟道。为了控制放电晶体管的电极 56和第一和第二传输晶体管59,60被施加列选择线（CSL）信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式