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1. 发明授权

US5840602A Methods of forming nonmonocrystalline silicon-on-insulator thin-film transistors 失效
标题翻译：形成非晶硅绝缘体上薄膜晶体管的方法
公开(公告)号：US5840602A
公开(公告)日：1998-11-24
申请号：US686242
申请日：1996-07-25
申请人： Min-Koo Han , Byung-Hyuk Min , Cheol-Min Park , Byung-Seong Bae
发明人： Min-Koo Han , Byung-Hyuk Min , Cheol-Min Park , Byung-Seong Bae
IPC分类号： H01L29/786 , H01L21/77 , H01L21/84 , H01L27/12 , H01L21/8238
CPC分类号： H01L27/1214
摘要： Methods of forming thin-film transistors include the steps of forming an amorphous silicon (a-Si) layer of predetermined conductivity type on a face of an electrically insulating substrate and then forming a first insulating layer on the amorphous silicon layer. The first insulating layer and amorphous silicon layer are then patterned to define spaced amorphous source and drain regions having exposed sidewalls. An amorphous silicon channel region is then deposited in the space between the source and drain regions and in contact with the sidewalls thereof. An annealing step is then performed to convert the amorphous source, drain and channel regions to polycrystalline silicon, prior to the step of forming an insulated gate electrode on the channel region.
摘要翻译：形成薄膜晶体管的方法包括以下步骤：在电绝缘基板的表面上形成预定导电类型的非晶硅（a-Si）层，然后在非晶硅层上形成第一绝缘层。然后对第一绝缘层和非晶硅层进行构图以限定具有暴露的侧壁的间隔开的无定形源极和漏极区域。然后在源区和漏区之间的空间中沉积非晶硅沟道区，并与其侧壁接触。然后在通道区域上形成绝缘栅电极的步骤之前，执行退火步骤以将非晶硅源，漏极和沟道区域转换为多晶硅。

2. 发明授权

US5804837A Polysilicon thin-film transistor and method for fabricating the same 失效
标题翻译：多晶硅薄膜晶体管及其制造方法
公开(公告)号：US5804837A
公开(公告)日：1998-09-08
申请号：US687630
申请日：1996-07-26
申请人： Min-Koo Han , Byung-Hyuk Min , Cheol-Min Park
发明人： Min-Koo Han , Byung-Hyuk Min , Cheol-Min Park
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/786 , H01L29/76 , H01L31/036 , H01L31/112
CPC分类号： H01L29/42384 , H01L21/28105 , H01L29/4908 , H01L29/4983 , H01L29/6675 , H01L29/66757 , H01L29/78621
摘要： To accomplish the objects of the present invention, among others, the present invention provides a thin-film transistor that has a channel region operatively having an offset region only during turn-off. Source and drain regions self-aligned with different ends of the channel region. A gate region is formed on a gate insulating layer disposed over the channel region and has a main gate accepting a gate voltage, a subgate which comes into ohmic contact with the source region, and a junction gate for forming a rectifying junction between the main gate and subgate.
摘要翻译：为了实现本发明的目的，除其他之外，本发明提供一种薄膜晶体管，其具有仅在关断期间可操作地具有偏移区域的沟道区。源极和漏极区域与通道区域的不同端部自对准。栅极区域形成在栅极绝缘层上，栅极绝缘层设置在沟道区上方，并且具有接受栅极电压的主栅极，与源极区域欧姆接触的子栅极和用于在主栅极之间形成整流结的结栅极和subgate。

3. 发明授权

US5894157A MOS transistor having an offset resistance derived from a multiple region gate electrode 失效
标题翻译： MOS晶体管具有源自多区域栅电极的偏移电阻
公开(公告)号：US5894157A
公开(公告)日：1999-04-13
申请号：US266420
申请日：1994-06-27
申请人： Min-Koo Han , Byung-Hyuk Min
发明人： Min-Koo Han , Byung-Hyuk Min
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L29/49 , H01L29/786 , H01L29/76
CPC分类号： H01L29/66757 , H01L21/28105 , H01L29/4908 , H01L29/4983 , H01L29/6675 , H01L29/78621
摘要： A method for fabricating a MOS transistor having an offset resistance in a channel region controlled by a gate voltage and structure thereof is disclosed. A gate electrode is divided into three adjacent regions of respectively a second conductivity type, first conductivity type and second conductivity type connected laterally to one another on a channel region. A gate control voltage is applied to a central region of the first conductivity type, and a predetermined voltage between maximum and minimum values of the gate control voltage is applied to left and right adjacent regions of the second conductivity type. If a gate turn-on voltage is applied to the central region the gate turn-on voltage is forward biased to the adjacent left and right regions and is therefore also applied to the forwardly biased left and right regions. The effective length of the gate electrode then becomes the total length of the central region and the left and right adjacent regions. If a gate turn-off voltage is applied to the central region the central region becomes reverse biased with the left and right adjacent regions and thus the effective length of the gate electrode becomes the length of only the central region of the first conductivity type. This reduces the length of the channel region, and thus forms an offset resistance structure which reduces leakage current in the off state of the MOS transistor.
摘要翻译：公开了一种制造具有由栅极电压控制的沟道区域中的偏移电阻的MOS晶体管及其结构的方法。栅极电极被分成在沟道区域上彼此侧向连接的第二导电类型，第一导电类型和第二导电类型的三个相邻区域。栅极控制电压施加到第一导电类型的中心区域，栅极控制电压的最大值和最小值之间的预定电压被施加到第二导电类型的左右相邻区域。如果栅极导通电压施加到中心区域，则栅极导通电压被正向偏置到相邻的左右区域，并且因此也被施加到向前偏置的左右区域。然后，栅电极的有效长度变为中心区域和左右相邻区域的总长度。如果向中心区域施加栅极截止电压，则中心区域与左右相邻区域反向偏置，因此栅电极的有效长度仅成为第一导电类型的中心区域的长度。这减小了沟道区的长度，从而形成了减小MOS晶体管的截止状态下的漏电流的偏移电阻结构。

4. 发明授权

US5885859A Methods of fabricating multi-gate, offset source and drain field effect transistors 失效
标题翻译：制造多栅极，偏移源和漏极场效应晶体管的方法
公开(公告)号：US5885859A
公开(公告)日：1999-03-23
申请号：US960631
申请日：1997-10-29
申请人： Min-Koo Han , Byung-Hyuk Min , Cheol-Min Park , Keun-Ho Jang , Jae-Hong Jun
发明人： Min-Koo Han , Byung-Hyuk Min , Cheol-Min Park , Keun-Ho Jang , Jae-Hong Jun
IPC分类号： H01L29/70 , H01L21/336 , H01L29/08 , H01L29/78 , H01L29/786 , H01L29/788 , H01L21/00 , H01L21/84 , H01L21/338 , H01L21/337
CPC分类号： H01L29/6675 , H01L29/0847 , H01L29/7831 , H01L29/7833 , H01L29/78621 , H01L29/78645 , H01L29/788
摘要： A field effect transistor includes laterally spaced apart source and drain regions in a substrate, laterally spaced apart undoped regions in the substrate between the laterally spaced apart source and drain regions, a doped channel region in the substrate between the laterally spaced apart undoped regions, and a gate insulating layer on the substrate. A main gate is on the gate insulating layer opposite the channel, and first and second sub gates are on the gate insulating layer, a respective one of which is opposite a respective one of the spaced apart undoped regions. The first and second sub gates are laterally spaced apart from and electrically insulated from the main gate. The transistor may be formed by patterning a photoresist layer and a gate layer to form a main gate and first and second sub gates, reflowing the photoresist into the lateral space between the main gate and the first and second sub gates, etching the gate insulating layer using the reflowed photoresist as a mask, and implanting ions into the substrate to form source and drain regions using the etched gate insulating layer as a mask.
摘要翻译：场效应晶体管包括在衬底中的横向间隔开的源极和漏极区域，在横向间隔开的源极和漏极区域之间的衬底中横向间隔开的未掺杂区域，在横向间隔开的未掺杂区域之间的衬底中的掺杂沟道区域，以及基板上的栅极绝缘层。主栅极在与沟道相对的栅极绝缘层上，第一和第二子栅极位于栅极绝缘层上，其相应的一个与相应的一个间隔开的未掺杂区域相对。第一和第二子门与主门横向间隔开并与之绝缘。可以通过图案化光致抗蚀剂层和栅极层来形成晶体管，以形成主栅极和第一和第二子栅极，将光致抗蚀剂回流到主栅极和第一和第二子栅极之间的横向空间中，蚀刻栅极绝缘层使用回流光致抗蚀剂作为掩模，并且使用蚀刻的栅绝缘层作为掩模将离子注入到衬底中以形成源区和漏区。

5. 发明授权

US5593909A Method for fabricating a MOS transistor having an offset resistance 失效
标题翻译：具有偏移电阻的MOS晶体管的制造方法
公开(公告)号：US5593909A
公开(公告)日：1997-01-14
申请号：US467715
申请日：1995-06-06
申请人： Min-Koo Han , Byung-Hyuk Min
发明人： Min-Koo Han , Byung-Hyuk Min
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L29/49 , H01L29/786 , H01L21/265
CPC分类号： H01L29/66757 , H01L21/28105 , H01L29/4908 , H01L29/4983 , H01L29/6675 , H01L29/78621
摘要： A method for fabricating a MOS transistor having an offset resistance in a channel region controlled by a gate voltage and structure thereof is disclosed. A gate electrode is divided into three adjacent regions of respectively a second conductivity type, first conductivity type and second conductivity type connected laterally to one another on a channel region. A gate control voltage is applied to a central region of the first conductivity type, and a predetermined voltage between maximum and minimum values of the gate control voltage is applied to left and right adjacent regions of the second conductivity type. If a gate turn-on voltage is applied to the central region the gate turn-on voltage is forward biased to the adjacent left and right regions and is therefore also applied to the forwardly biased left and right regions. The effective length of the gate electrode then becomes the total length of the central region and the left and right adjacent regions. If a gate turn-off voltage is applied to the central region the central region becomes reverse biased with the and left and right adjacent regions and thus the effective length of the gate electrode becomes the length of only the central region of the first conductivity type. This reduces the length of the channel region, and thus forms an offset resistance structure which reduces leakage current in the off state of the MOS transistor.
摘要翻译：公开了一种制造具有由栅极电压控制的沟道区域中的偏移电阻的MOS晶体管及其结构的方法。栅极电极被分成在沟道区域上彼此侧向连接的第二导电类型，第一导电类型和第二导电类型的三个相邻区域。栅极控制电压施加到第一导电类型的中心区域，栅极控制电压的最大值和最小值之间的预定电压被施加到第二导电类型的左右相邻区域。如果栅极导通电压施加到中心区域，则栅极导通电压被正向偏置到相邻的左右区域，并且因此也被施加到向前偏置的左右区域。然后，栅电极的有效长度变为中心区域和左右相邻区域的总长度。如果向中心区域施加栅极截止电压，则中心区域与左右相邻区域反向偏置，因此栅电极的有效长度变为仅第一导电类型的中心区域的长度。这减小了沟道区的长度，从而形成了减小MOS晶体管的截止状态下的漏电流的偏移电阻结构。

6. 发明授权

US5920085A Multiple floating gate field effect transistors and methods of operating same 失效
标题翻译：多个浮栅场效应晶体管及其工作方式相同
公开(公告)号：US5920085A
公开(公告)日：1999-07-06
申请号：US104585
申请日：1998-06-25
申请人： Min-Koo Han , Byung-Hyuk Min , Cheol-Min Park , Keun-Ho Jang , Jae-Hong Jun
发明人： Min-Koo Han , Byung-Hyuk Min , Cheol-Min Park , Keun-Ho Jang , Jae-Hong Jun
IPC分类号： H01L21/28 , H01L29/788 , H04L29/788
CPC分类号： H01L29/788 , H01L21/28273
摘要： A field effect transistor includes laterally spaced apart source and drain regions in a substrate, laterally spaced apart undoped regions in the substrate between the laterally spaced apart source and drain regions, a doped channel region in the substrate between the laterally spaced apart undoped regions, and a gate insulating layer on the substrate. A main gate is on the gate insulating layer opposite the channel, and first and second sub gates are on the gate insulating layer, a respective one of which is opposite a respective one of the spaced apart undoped regions. The first and second sub gates are laterally spaced apart from and electrically insulated from the main gate. The transistor may be formed by patterning a photoresist layer and a gate layer to form a main gate and first and second sub gates, reflowing the photoresist into the lateral space between the main gate and the first and second sub gates, etching the gate insulating layer using the reflowed photoresist as a mask, and implanting ions into the substrate to form source and drain regions using the etched gate insulating layer as a mask.
摘要翻译：场效应晶体管包括在衬底中的横向间隔开的源极和漏极区域，在横向间隔开的源极和漏极区域之间的衬底中横向间隔开的未掺杂区域，在横向间隔开的未掺杂区域之间的衬底中的掺杂沟道区域，以及基板上的栅极绝缘层。主栅极在与沟道相对的栅极绝缘层上，第一和第二子栅极位于栅极绝缘层上，其相应的一个与相应的一个间隔开的未掺杂区域相对。第一和第二子门与主门横向间隔开并与之绝缘。可以通过图案化光致抗蚀剂层和栅极层来形成晶体管，以形成主栅极和第一和第二子栅极，将光致抗蚀剂回流到主栅极和第一和第二子栅极之间的横向空间中，蚀刻栅极绝缘层使用回流光致抗蚀剂作为掩模，并且使用蚀刻的栅绝缘层作为掩模将离子注入到衬底中以形成源区和漏区。

7. 发明授权

US5793058A Multi-gate offset source and drain field effect transistors and methods of operating same 失效
标题翻译：多栅极偏移源极和漏极场效应晶体管及其工作方式相同
公开(公告)号：US5793058A
公开(公告)日：1998-08-11
申请号：US692924
申请日：1996-07-31
申请人： Min-Koo Han , Byung-Hyuk Min , Cheol-Min Park , Keun-Ho Jang , Jae-Hong Jun
发明人： Min-Koo Han , Byung-Hyuk Min , Cheol-Min Park , Keun-Ho Jang , Jae-Hong Jun
IPC分类号： H01L29/70 , H01L21/336 , H01L29/08 , H01L29/78 , H01L29/786 , H01L29/788
CPC分类号： H01L29/6675 , H01L29/0847 , H01L29/7831 , H01L29/7833 , H01L29/78621 , H01L29/78645 , H01L29/788
摘要： A field effect transistor includes laterally spaced apart source and drain regions in a substrate, laterally spaced apart undoped regions in the substrate between the laterally spaced apart source and drain regions, a doped channel region in the substrate between the laterally spaced apart undoped regions, and a gate insulating layer on the substrate. A main gate is on the gate insulating layer opposite the channel, and first and second sub gates are on the gate insulating layer, a respective one of which is opposite a respective one of the spaced apart undoped regions. The first and second sub gates are laterally spaced apart from and electrically insulated from the main gate. The transistor may be formed by patterning a photoresist layer and a gate layer to form a main gate and first and second sub gates, reflowing the photoresist into the lateral space between the main gate and the first and second sub gates, etching the gate insulating layer using the reflowed photoresist as a mask, and implanting ions into the substrate to form source and drain regions using the etched gate insulating layer as a mask.
摘要翻译：场效应晶体管包括在衬底中的横向间隔开的源极和漏极区域，在横向间隔开的源极和漏极区域之间的衬底中横向间隔开的未掺杂区域，在横向间隔开的未掺杂区域之间的衬底中的掺杂沟道区域，以及基板上的栅极绝缘层。主栅极在与沟道相对的栅极绝缘层上，第一和第二子栅极位于栅极绝缘层上，其相应的一个与相应的一个间隔开的未掺杂区域相对。第一和第二子门与主门横向间隔开并与之绝缘。可以通过图案化光致抗蚀剂层和栅极层来形成晶体管，以形成主栅极和第一和第二子栅极，将光致抗蚀剂回流到主栅极和第一和第二子栅极之间的横向空间中，蚀刻栅极绝缘层使用回流光致抗蚀剂作为掩模，并且使用蚀刻的栅绝缘层作为掩模将离子注入到衬底中以形成源区和漏区。

8. 发明授权

US07868280B2 Illumination sensing apparatus, driving method thereof and display device having the illumination sensing apparatus 有权
标题翻译：照明感测装置及其驱动方法以及具有照明感测装置的显示装置
公开(公告)号：US07868280B2
公开(公告)日：2011-01-11
申请号：US12179360
申请日：2008-07-24
申请人： Hyun-Sang Park , Min-Koo Han , Doo-Hyung Woo , Jae-Beom Choi , Kwang-Sub Shin
发明人： Hyun-Sang Park , Min-Koo Han , Doo-Hyung Woo , Jae-Beom Choi , Kwang-Sub Shin
IPC分类号： G01J1/32 , G02F1/1335
CPC分类号： G09G3/3406 , G09G2320/0626 , G09G2330/021 , G09G2360/144
摘要： Provided are an illumination sensing apparatus, a driving method thereof and a display device having the illumination sensing apparatus. The illumination sensing apparatus includes an illumination sensor unit configured to generate a sensing signal according to peripheral illumination, an illumination determination unit configured to generate an illumination signal according to the sensing signal, and an illumination judgment unit configured to output a brightness select signal using the illumination signal, wherein the illumination sensor unit controls sensitivity of sensing the peripheral illumination to be varied according to the brightness select signal. Therefore, the sensitivity of an illumination sensor is automatically controlled according to the peripheral illumination, thus improving peripheral illumination sensibility. Further, an illumination signal corresponding to the peripheral illumination is provided to a light source module to thereby control the output brightness of the light source module, which makes it possible to reduce power consumption and improve image quality.
摘要翻译：提供了一种照明感测装置，其驱动方法和具有该照明感测装置的显示装置。该照明感测装置具备：照明传感器单元，被配置为根据周边照明产生感测信号;照明判定单元，其根据感测信号生成照明信号;照明判断单元，其使用照明信号，其中所述照明传感器单元控制根据所述亮度选择信号来感测要周边照明的灵敏度。因此，根据周边照明自动控制照明传感器的灵敏度，从而提高周边照明灵敏度。此外，将与周边照明相对应的照明信号提供给光源模块，从而控制光源模块的输出亮度，这使得可以降低功耗并提高图像质量。

9. 发明授权

US07586358B2 Level shifter and driving method 有权
标题翻译：电平转换器和驱动方式
公开(公告)号：US07586358B2
公开(公告)日：2009-09-08
申请号：US11771138
申请日：2007-06-29
申请人： Kee-Chan Park , Min-Koo Han , Woo-Jin Nam , Jae-Hoon Lee
发明人： Kee-Chan Park , Min-Koo Han , Woo-Jin Nam , Jae-Hoon Lee
IPC分类号： H03L5/00
CPC分类号： H03K3/35613 , G09G3/3611 , G09G3/3648 , G09G2300/0408 , G09G2310/0289 , G09G2310/08
摘要： A level shifter includes; a level conversion unit which receives a first input signal and a second input signal, wherein the second input signal is an inversion of the first input signal, and generates a first output signal having substantially a same phase of the first input signal and a voltage which is higher than the first input signal and a second output signal having substantially a same phase as the first input signal and a voltage which is lower than the first input signal; and wherein the level shifter further includes an amplifying unit which receives the first and second output signals and generates a third output signal having substantially a same phase as the first input signal and an amplitude which is greater than the first input signal.
摘要翻译：电平转换器包括：电平转换单元，其接收第一输入信号和第二输入信号，其中所述第二输入信号是所述第一输入信号的反相，并且产生具有与所述第一输入信号基本上相同相位的第一输出信号和高于第一输入信号，第二输出信号具有与第一输入信号基本相同的相位和低于第一输入信号的电压; 并且其中所述电平移位器还包括放大单元，其接收所述第一和第二输出信号，并产生具有与所述第一输入信号基本相同的相位的第三输出信号和大于所述第一输入信号的幅度。

10. 发明申请

US20060256057A1 Pixel structure using voltage programming-type for active matrix organic light emitting device 有权
标题翻译：使用有源矩阵有机发光器件的电压编程类型的像素结构
公开(公告)号：US20060256057A1
公开(公告)日：2006-11-16
申请号：US11412525
申请日：2006-04-27
申请人： Min-Koo Han , Jae-Hoon Lee
发明人： Min-Koo Han , Jae-Hoon Lee
IPC分类号： G09G3/36
CPC分类号： G09G3/3258 , G09G2300/0819 , G09G2300/0842 , G09G2320/0233
摘要： A pixel structure using a voltage programming type active matrix organic light emitting diode (OLED) which can minimize a current deterioration phenomenon is disclosed. The pixel structure includes a fifth TFT receiving an external management signal EMS through its gate, having a drain region connected to a cathode part of an OLED, and receiving an input of an OLED current through its source-drain current path when the OLED emits light, a fourth TFT receiving a set scan signal SCAN through its gate and having source and drain regions connected to gate and drain parts of a third TFT T3, respectively, the third TFT T3 being a current driving transistor for determining the OLED current when the OLED emits light, a capacitor C having upper and lower plates connected to the gate part of the third TFT T3 and a ground voltage VSS, respectively, a first TFT receiving the SCAN signal through its gate and transferring a data voltage to a source region of the third TFT T3, a second TFT receiving the EMS signal through its gate and connecting the lower part of the capacitor C to the source region of the third TFT T3, and a sixth TFT having source and drain regions connected to an external clock signal CLK and the gate region of the third TFT T3, respectively, and having a gate connected to the gate part of the third TFT T3. An anode part of the OLED receives a voltage VDD.
摘要翻译：公开了一种可以使电流劣化现象最小化的电压编程型有源矩阵有机发光二极管（OLED）的像素结构。像素结构包括通过其栅极接收外部管理信号EMS的第五TFT，具有连接到OLED的阴极部分的漏极区域，并且当OLED发光时，通过其源极 - 漏极电流路径接收OLED电流的输入，第四TFT通过其栅极接收设置的扫描信号SCAN，并且分别具有连接到第三TFT T 3的栅极和漏极部分的源极和漏极区域，第三TFT T 3是用于确定OLED电流的电流驱动晶体管， OLED发光，具有连接到第三TFT T 3的栅极部分的上板和下板的电容器C和接地电压VSS分别通过其栅极接收SCAN信号的第一TFT并将数据电压传送到源极区域，第二TFT通过其栅极接收EMS信号并将电容器C的下部连接到第三TFT T 3的源极区域，以及第六TFT，其具有源极和栅极连接到外部时钟信号CLK的n个区域和第三TFT T 3的栅极区域，并且具有连接到第三TFT T 3的栅极部分的栅极。 OLED的阳极部分接收电压VDD。

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