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1. 发明授权

US4298770A Printed board 失效
标题翻译：印刷板
公开(公告)号：US4298770A
公开(公告)日：1981-11-03
申请号：US69346
申请日：1979-08-24
申请人： Mikio Nishihara , Masahiro Oda , Takamitsu Tsuchimoto
发明人： Mikio Nishihara , Masahiro Oda , Takamitsu Tsuchimoto
IPC分类号： H05K1/02 , H05K1/00 , H05K1/11 , H05K3/42 , H05K3/46
CPC分类号： H05K1/116 , H05K1/0289 , H05K2201/09381 , H05K2201/09609 , H05K3/429
摘要： A printed board comprising a plurality of through holes formed therein and located on intersecting points of an X-Y orthogonal basic grid, and an oblique conductor pattern, wherein conductors are formed along channels arranged in accordance with a principle that one conductor passes between adjacent grid points arranged in the X direction, while two or more conductors pass between adjacent grid points arranged in the Y direction, and each conductor obliquely extends in a zigzag line without contacting the grid points. Such conductor pattern ensures a high density and minimum length of wiring.
摘要翻译：一种印刷电路板，包括形成在其中并位于XY正交基本栅极的交叉点上的多个通孔和倾斜导体图案，其中导体沿着沿着布置的通道形成，该导体根据一个导体在相邻的格栅点之间通过的原理布置在X方向上，当两个或多个导体在沿Y方向布置的相邻栅格点之间通过时，并且每个导体以Z字形线倾斜地延伸而不接触网格点。这种导体图形确保了高密度和最小布线长度。

2. 发明授权

US4197555A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4197555A
公开(公告)日：1980-04-08
申请号：US925788
申请日：1978-07-18
申请人： Takao Uehara , Takamitsu Tsuchimoto , Katsuyuki Hamada , Hideo Masuzawa , Makoto Mukai
发明人： Takao Uehara , Takamitsu Tsuchimoto , Katsuyuki Hamada , Hideo Masuzawa , Makoto Mukai
IPC分类号： H01L23/528 , H01L23/538 , H01L23/48
CPC分类号： H01L23/528 , H01L23/5384 , H01L2924/0002
摘要： An electronic device which includes at least one semiconductor chip with at least one circuit element thereon and connection patterns thereon being connected to the circuit element or elements. The connection patterns comprise a lower connection pattern, which is standardized and widely applicable to many kinds of circuits, and an upper connection pattern, which is positioned on the upper side of said lower connection pattern. The upper connection pattern and the lower connection pattern are connected in conformity with the desired circuit to be obtained.
摘要翻译：一种电子设备，其包括至少一个其上具有至少一个电路元件的半导体芯片及其上的连接图案连接到电路元件。连接图案包括标准化并广泛适用于多种电路的下连接图案，以及位于所述下连接图案的上侧的上连接图案。上连接图案和下连接图案根据要获得的期望电路连接。

3. 发明授权

US4414620A Inter-subsystem communication system 失效
标题翻译：子系统间通信系统
公开(公告)号：US4414620A
公开(公告)日：1983-11-08
申请号：US204931
申请日：1980-11-07
申请人： Takamitsu Tsuchimoto , Saburo Kaneda , Tatsushi Miyazawa , Toshio Shimada , Hideo Suzuki , Mitsuru Sanagai , Kaoru Hiraoka
发明人： Takamitsu Tsuchimoto , Saburo Kaneda , Tatsushi Miyazawa , Toshio Shimada , Hideo Suzuki , Mitsuru Sanagai , Kaoru Hiraoka
IPC分类号： G06F13/00 , G06F13/12 , G06F13/38 , G06F15/16 , G06F15/17 , G06F15/177 , G06F7/00 , G06F15/20
CPC分类号： G06F13/122 , G06F15/17
摘要： A communication system operation between computer systems which realizes highly efficient data transfer in a data processing system has sender and receiver subsystems operating under the control of an independent or common operating system. The communication system also includes: a plurality of sending buffers, a sending buffer address table having a plurality of entries and a buffer control block in the sender subsystem and a plurality of receiving buffers, a receiving buffer address table having a plurality of entries and a buffer control block in the receiver subsystem, and the communication path for transferring the data stored in the sending buffer to the receiving buffer.
摘要翻译：在数据处理系统中实现高效数据传输的计算机系统之间的通信系统操作具有在独立或公共操作系统的控制下操作的发送器和接收器子系统。通信系统还包括：多个发送缓冲器，具有多个条目的发送缓冲器地址表和发送器子系统中的缓冲器控制块以及多个接收缓冲器，具有多个条目的接收缓冲器地址表和接收器子系统中的缓冲器控制块，以及用于将存储在发送缓冲器中的数据传送到接收缓冲器的通信路径。

4. 发明授权

US4145749A Log in-out system for logic apparatus 失效
标题翻译：逻辑设备登录系统
公开(公告)号：US4145749A
公开(公告)日：1979-03-20
申请号：US836077
申请日：1977-09-23
申请人： Tatsuro Yoshimura , Takamitsu Tsuchimoto , Katsuyuki Hamada
发明人： Tatsuro Yoshimura , Takamitsu Tsuchimoto , Katsuyuki Hamada
IPC分类号： G06F13/42 , G06F7/76 , G01R15/00 , G11C7/00 , G11C17/00
CPC分类号： G06F7/76
摘要： A plurality of logic circuits having log in-out functions are connected in sequence. A clock distribution circuit is connected to each sequential logic circuit via a corresponding one of a plurality of bidirectional lines. A mode designation signal is supplied in common to each sequential logic circuit and the clock distribution circuit. A sequential logic circuit selection signal, which selects one of the sequential logic circuits, is supplied to the clock distribution circuit. A clock signal is supplied from the clock distribution circuit to each sequential logic circuit via the bidirectional lines in the clock mode. Log in data is supplied from the clock distribution circuit to the sequential logic circuit via a specific bidirectional line in accordance with the sequential logic circuit selection signal in the log in mode. Log out data is supplied to the clock distribution circuit from the sequential logic circuit in the log out mode via a specific bidirectional line in accordance with the sequential logic circuit selection signal.
摘要翻译：具有登录功能的多个逻辑电路依次连接。时钟分配电路通过多条双向线路中的相应一条连接到每个顺序逻辑电路。模式指定信号被共同地提供给每个顺序逻辑电路和时钟分配电路。选择顺序逻辑电路之一的顺序逻辑电路选择信号被提供给时钟分配电路。在时钟模式下，时钟信号经由双向线从时钟分配电路提供给每个顺序逻辑电路。根据登录模式中的顺序逻辑电路选择信号，通过特定双向线将登录数据从时钟分配电路提供给顺序逻辑电路。根据顺序逻辑电路选择信号，经由特定的双向线路，从注销模式的顺序逻辑电路将注销数据提供给时钟分配电路。

5. 发明授权

US4181937A Data processing system having an intermediate buffer memory 失效
标题翻译：数据处理系统具有中间缓冲存储器
公开(公告)号：US4181937A
公开(公告)日：1980-01-01
申请号：US846427
申请日：1977-10-28
申请人： Akira Hattori , Takamitsu Tsuchimoto
发明人： Akira Hattori , Takamitsu Tsuchimoto
IPC分类号： G06F12/08 , G06F15/16
CPC分类号： G06F12/0811
摘要： In a data processing system having an intermediate buffer memory provided between a large space main memory and small space, high speed buffer memories of a plurality of processors, a data block of the intermediate buffer memory to be replaced with a data block of the main memory is determined by utilizing LRU (Least Recently Used) algorithm as well as copy flags employed in buffer invalidation processing. In the intermediate buffer memory, a data block that the number of its copy flags in the ON state is smaller than any other data blocks, is selected as the data block to be replaced. The fact that the number of copy flags in the ON state implies that the data block is not frequently used by the processors. Replacement of such a data block alleviates the burden of the buffer invalidation processing imposed on the intermediate buffer memory.
摘要翻译：在具有设置在大空间主存储器和小空间之间的中间缓冲存储器的数据处理系统中，多个处理器的高速缓冲存储器，要被主存储器的数据块替换的中间缓冲存储器的数据块通过利用LRU（最近最少使用）算法以及在缓冲器无效化处理中使用的复制标志来确定。在中间缓冲存储器中，选择其ON状态下的复制标志的数量小于任何其他数据块的数据块作为要替换的数据块。在ON状态下的复制标志的数量意味着数据块不被处理器频繁地使用。替换这样的数据块减轻了对中间缓冲存储器的缓冲器无效处理的负担。

6. 发明授权

US4550367A Data processing system having hierarchical memories 失效
标题翻译：具有分层存储器的数据处理系统
公开(公告)号：US4550367A
公开(公告)日：1985-10-29
申请号：US245646
申请日：1981-03-20
申请人： Akira Hattori , Takamitsu Tsuchimoto
发明人： Akira Hattori , Takamitsu Tsuchimoto
IPC分类号： G06F12/06 , G06F12/08 , G06F9/00 , G06F7/00
CPC分类号： G06F12/0851
摘要： A data processing system having hierarchical memories comprised of buffer memories contained in a plurality of central processing units, an intermediate buffer memory and a main memory having a plurality of banks. The intermediate buffer memory and the main memory are controlled under both a swap control method and a set associative control method. These two memories are accessed by address information which includes both bank-selection address bits and set-selection address bits. The bank-selection address bits are partially modified by part of the set-selection address bits.
摘要翻译： PCT No.PCT / JP80 / 00169 Sec。 371日期1981年3月25日 102（e）1981年3月20日PCT PCT。1980年7月24日PCT公布。公开号WO81 / 00321 日期：1981年2月5日。具有包含在多个中央处理单元中的缓冲存储器的分级存储器的数据处理系统，中间缓冲存储器和具有多个存储体的主存储器。中间缓冲存储器和主存储器均以交换控制方法和集合关联控制方式进行控制。这两个存储器由包括存储体选择地址位和设置选择地址位的地址信息访问。存储体选择地址位由设置选择地址位的一部分部分修改。

7. 发明授权

US4347565A Address control system for software simulation 失效
标题翻译：软件仿真地址控制系统
公开(公告)号：US4347565A
公开(公告)日：1982-08-31
申请号：US98989
申请日：1979-11-30
申请人： Saburo Kaneda , Takamitsu Tsuchimoto , Kazuyuki Shimizu , Fujio Ikegami
发明人： Saburo Kaneda , Takamitsu Tsuchimoto , Kazuyuki Shimizu , Fujio Ikegami
IPC分类号： G06F9/455 , G06F9/46 , G06F12/10 , G06F7/00 , G06F9/00
CPC分类号： G06F12/1036
摘要： An address control system for software simulation in a virtual machine system having a virtual storage function. When a simulator program is simulating an instruction of a program to be simulated, an address translation of an operand address in the program to be simulated is achieved using a translation lookaside buffer, thereby greatly reducing the overhead for the address translation during the simulator program execution.
摘要翻译：一种具有虚拟存储功能的虚拟机系统中用于软件仿真的地址控制系统。当模拟器程序模拟要仿真的程序的指令时，使用转换后备缓冲器实现要仿真的程序中的操作数地址的地址转换，从而大大减少了在模拟器程序执行期间的地址转换的开销。

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