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1. 发明授权

US06519728B2 Semiconductor integrated circuit having test circuit 失效
标题翻译：具有测试电路的半导体集成电路
公开(公告)号：US06519728B2
公开(公告)日：2003-02-11
申请号：US09303624
申请日：1999-05-03
申请人： Toshiyuki Tsujii , Masahiko Hyozo
发明人： Toshiyuki Tsujii , Masahiko Hyozo
IPC分类号： G01R3128
CPC分类号： G01R31/318572 , G01R31/2884
摘要： A semiconductor integrated circuit has a test circuit in which signal pad (15) to input a switching signal TM is formed on a non-mounting surface of a LSI and one group of signal pads (11 to 13) formed on the non-mounting surface and signal pads (16 to 18) formed on a mounting surface is selected based on a signal level of the switching signal TM.
摘要翻译：半导体集成电路具有测试电路，其中输入切换信号TM的信号焊盘（15）形成在LSI的非安装表面上，并且形成在非安装表面上的一组信号焊盘（11至13）并且基于开关信号TM的信号电平来选择形成在安装表面上的信号焊盘（16至18）。

2. 发明授权

US5894172A Semiconductor device with identification function 失效
标题翻译：半导体器件具有识别功能
公开(公告)号：US5894172A
公开(公告)日：1999-04-13
申请号：US745273
申请日：1996-11-08
申请人： Masahiko Hyozo , Toshiyuki Tsujii , Tetsuo Tada , Hiroshi Noda , Ryouichi Takagi , Mikio Asai
发明人： Masahiko Hyozo , Toshiyuki Tsujii , Tetsuo Tada , Hiroshi Noda , Ryouichi Takagi , Mikio Asai
IPC分类号： H01L21/02 , G05B19/12 , G06K7/06 , G06K19/06 , G06K19/067 , H01L23/544 , H01L29/06 , H01L31/0203 , H01L23/04
CPC分类号： H01L23/544 , G05B19/128 , G06K19/06018 , G06K19/06037 , G06K19/067 , G06K7/065 , G05B2219/25294 , G06K2019/06271 , H01L2223/54406 , H01L2223/5442 , H01L2223/5444 , H01L2223/54473 , H01L2223/5448 , H01L2223/54486 , H01L29/0657 , H01L2924/0002
摘要： A bare chip (1) is rectangular, and has a front surface (1a) on the center of which semiconductor elements are integrated and a back surface. Notches (2) are formed on a side of the bare chip (1) according to the kind of the semiconductor elements integrated on the bare chip (1). The notches (2) are oblong and extend through the bare chip (1) from the front surface (1a) to the back surface. For example, assuming that the notch (2) represents "1" and a portion without the notch (2) represents "0", one-bit information is obtained according to the presence or absence of the notch (2). When detection of several portions is made, binary information according to a detection result, i.e., information regarding the type of the bare chip (1), is obtained. For detection of the presence or absence of the notch (2), the bare chip (1) is irradiated with light, and then whether the light goes through the notch (2) or is intercepted by the bare chip (1) is detected. Thus, a semiconductor device which allows easy identification of its type is provided.
摘要翻译：裸芯片（1）是矩形的，并且在其半导体元件集成的中心上具有前表面（1a）和后表面。根据集成在裸芯片（1）上的半导体元件的种类，在裸芯片（1）的一侧形成凹口（2）。凹口（2）是长圆形的，并且通过裸芯片（1）从前表面（1a）延伸到后表面。例如，假设凹口（2）表示“1”，没有凹口（2）的部分表示“0”，则根据凹口（2）的存在或不存在获得一位信息。当进行几个部分的检测时，获得根据检测结果的二进制信息，即关于裸芯片（1）的类型的信息。为了检测凹口（2）的存在或不存在，用光照射裸芯片（1），然后检测光是否穿过凹口（2）或被裸芯片（1）截取。因此，提供了容易识别其类型的半导体器件。

3. 发明授权

US06351836B1 Semiconductor device with boundary scanning circuit 失效
标题翻译：半导体器件，其中属于公共焊盘组的焊盘和每个焊盘组中的每一个的焊盘之间的位置关系相同
公开(公告)号：US06351836B1
公开(公告)日：2002-02-26
申请号：US09176312
申请日：1998-10-22
申请人： Toshiyuki Tsujii
发明人： Toshiyuki Tsujii
IPC分类号： G01R3128
CPC分类号： G01R31/318572
摘要： Provided is a semiconductor device capable of performing a function test and a DC test including an output voltage test every time a test jig is sequentially caused to come in contact with pads of the semiconductor device. The semiconductor device comprises a principal plane (2) of a semiconductor substrate, and pads (3) provided on the principal plane (2). The principal plane (2) is provided with four probing areas (PA1) to (PA4) with which the test jig comes in contact. A large number of pads (3) include four sets of driving pads (3ab) for supplying a driving voltage, and four sets of boundary scanning pads (BSP) for performing boundary scan. Even if it comes in contact with any of the probing areas (PA1) to (PA4), the test jig comes in contact with the driving pads (3ab) and the boundary scanning pads (BSP).
摘要翻译：提供一种半导体器件，其能够在每次使测试夹具依次与半导体器件的焊盘接触时进行功能测试和包括输出电压测试的DC测试。半导体器件包括半导体衬底的主平面（2）和设置在主平面（2）上的焊盘（3）。主平面（2）设有与测试夹具接触的四个探测区域（PA1）至（PA4）。多个焊盘（3）包括用于提供驱动电压的四组驱动焊盘（3ab）和用于进行边界扫描的四组边界扫描焊盘（BSP）。即使与任何探测区域（PA1）到（PA4）接触，测试夹具与驱动焊盘（3ab）和边界扫描焊盘（BSP）接触。

4. 发明授权

US06300577B1 Film carrier and method of burn-in testing 失效
标题翻译：电影载体和老化测试方法
公开(公告)号：US06300577B1
公开(公告)日：2001-10-09
申请号：US09118927
申请日：1998-07-20
申请人： Toshiyuki Tsujii
发明人： Toshiyuki Tsujii
IPC分类号： H01R1204
CPC分类号： G01R31/2863 , H01L23/4985 , H01L2224/16 , H01L2924/01078
摘要： A film carrier includes a base film (1), a first interconnect line (5a) formed on the top surface of the base film (1) and connected to test pads (3), and a second interconnect line (5b) formed on the bottom surface of the base film (1) and connected to the test pads (3). After leads (6) are plated, connecting portions between the first interconnect line (5a) and other than one of the test pads which is associated with a pad which is to receive a power supply potential, and connecting portions between the second interconnect line (5b) and other than one of the test pads which is associated with a pad which is to receive a ground potential are severed using a laser and the like. Then, the film carrier is wound onto a reel, and the reel with the film carrier wound thereon is loaded into a burn-in apparatus. A potential supply portion of the burn-in apparatus applies the power supply potential to the first interconnect line (5a) and applies the ground potential to the second interconnect line (5b). The film carrier and a method of burn-in testing eliminate the need for a burn-in board and a socket and reduce the time for preparation for burn-in.
摘要翻译：膜载体包括基膜（1），形成在基膜（1）的顶表面上并连接到测试焊盘（3）的第一互连线（5a）和形成在基膜底膜（1）的底表面并连接到测试垫（3）。在引线（6）被电镀之后，第一互连线（5a）之间的连接部分和与接收电源电位的焊盘相关联的测试焊盘之外的连接部分以及第二互连线 5b）和与接收地电位的焊盘相关联的一个测试焊盘之外的激光等被切断。然后，将胶片载体卷绕在卷轴上，将卷绕有胶片载体的卷轴装入老化装置。老化装置的电源部分将电源电位施加到第一互连线（5a），并将接地电位施加到第二互连线（5b）。电影载体和老化测试方法消除了对老化板和插座的需要，并减少了烧录准备的时间。

5. 发明授权

US06486691B2 Tester for a semiconductor IC circuit having multiple pins 失效
标题翻译：具有多个引脚的半导体IC电路的测试器
公开(公告)号：US06486691B2
公开(公告)日：2002-11-26
申请号：US09368578
申请日：1999-08-05
申请人： Toshiyuki Tsujii
发明人： Toshiyuki Tsujii
IPC分类号： G01R3126
CPC分类号： G01R31/31922
摘要： A tester for testing a semiconductor IC circuit having multiple pins includes a timing signal generator and a test signal generator for outputting a test signal to an input pin of a semiconductor IC circuit. The timing signal generating device can supply timing signals to one or more of the test signal generating devices.
摘要翻译：用于测试具有多个引脚的半导体IC电路的测试器包括定时信号发生器和用于将测试信号输出到半导体IC电路的输入引脚的测试信号发生器。定时信号发生装置可以向一个或多个测试信号产生装置提供定时信号。

6. 发明授权

US06489791B1 Build off self-test (Bost) testing method 失效
标题翻译：建立自检（Bost）测试方法
公开(公告)号：US06489791B1
公开(公告)日：2002-12-03
申请号：US09596708
申请日：2000-06-19
申请人： Toshiyuki Tsujii
发明人： Toshiyuki Tsujii
IPC分类号： G01R3102
CPC分类号： G01R1/07314
摘要： A large scale integrated circuit for a build off self-test and a device to be tested are mounted in a single socket so that their respective electrodes are in direct contact.
摘要翻译：用于建立自检的大规模集成电路和待测试的装置安装在单个插座中，使得它们各自的电极直接接触。

7. 发明授权

US06393593B1 Tester and method for testing LSI designed for scan method 失效
标题翻译：用于扫描方法设计的测试仪和测试方法
公开(公告)号：US06393593B1
公开(公告)日：2002-05-21
申请号：US09368579
申请日：1999-08-05
申请人： Toshiyuki Tsujii
发明人： Toshiyuki Tsujii
IPC分类号： G01R3128
CPC分类号： G01R31/3181 , G01R31/3004
摘要： In a dc test, a plurality of dc test devices are connected to a plurality of tester pins, respectively and, in a function test, a function test device is connected to the plurality of tester pins.
摘要翻译：在直流测试中，多个直流测试设备分别连接到多个测试器引脚，并且在功能测试中，功能测试设备连接到多个测试器引脚。

8. 发明授权

US6006350A Semiconductor device testing apparatus and method for testing memory and logic sections of a semiconductor device 失效
标题翻译：用于测试半导体器件的存储器和逻辑部分的半导体器件测试装置和方法
公开(公告)号：US6006350A
公开(公告)日：1999-12-21
申请号：US946991
申请日：1997-10-08
申请人： Toshiyuki Tsujii
发明人： Toshiyuki Tsujii
IPC分类号： G01R31/28 , G01R31/3181 , G01R31/3183 , G01R31/319 , G11C29/02 , H01L21/66 , H01L27/10
CPC分类号： G01R31/318385 , G01R31/31813 , G01R31/31921 , G01R31/31926
摘要： A semiconductor device testing apparatus for a memory- built-in logic LSI or the like, which has a hardware configuration that test patterns for logic and memory sections of the semiconductor device can be described independently of each other.
摘要翻译：可以彼此独立地描述具有用于测试半导体器件的逻辑和存储器部分的图案的硬件配置的存储器内置逻辑LSI等的半导体器件测试装置。

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