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1. 发明授权

US5141888A Process of manufacturing semiconductor integrated circuit device having trench and field isolation regions 失效
标题翻译：制造具有TRENCH和现场隔离区域的半导体集成电路装置的制造方法
公开(公告)号：US5141888A
公开(公告)日：1992-08-25
申请号：US642922
申请日：1991-01-18
申请人： Mikinori Kawaji , Toshihiko Takakura , Akihisa Uchida , Shigeo Kuroda , Yoichi Tamaki , Takeo Shiba , Kazuhiko Sagara , Masao Kawamura
发明人： Mikinori Kawaji , Toshihiko Takakura , Akihisa Uchida , Shigeo Kuroda , Yoichi Tamaki , Takeo Shiba , Kazuhiko Sagara , Masao Kawamura
IPC分类号： H01L21/762 , H01L21/763 , H01L29/732
CPC分类号： H01L21/763 , H01L21/76224 , H01L29/7325 , Y10S148/05
摘要： A bipolar type of semiconductor integrated circuit device is provided with U-shaped grooves which are formed by cutting a main surface of a semiconductor body to form isolation regions between bipolar transistors. A silicon oxide film can be formed in the U-shaped grooves by thermal oxidation simultaneously with the formation of a silicon oxide film used to form isolation regions between each collector contact region and base region. No separate step is needed for forming the silicon oxide film between the collector contact region and the base region. The thickness of the silicon oxide film can be controlled, and has a sufficient thickness even at its two edges, i.e., at its boundaries with the U-shaped grooves, so that the bipolar transistors exhibit good electrical characteristics. Namely, the collector resistance thereof does not increase, and the breakdown voltage at the pn junction between the collector region and the base region does not decrease. The U-shaped grooves can each comprise narrow and deep sub-grooves, with thick oxide films formed on the surfaces of the sub-grooves and a thick oxide film formed on a surface of an area between the sub-grooves, and with wiring formed on the oxide on the area between the sub-grooves.

2. 发明授权

US4819054A Semiconductor IC with dual groove isolation 失效
标题翻译：半导体IC双沟槽隔离
公开(公告)号：US4819054A
公开(公告)日：1989-04-04
申请号：US11932
申请日：1987-02-06
申请人： Mikinori Kawaji , Toshihiko Takakura , Akihisa Uchida , Shigeo Kuroda , Yoichi Tamaki , Takeo Shiba , Kazuhiko Sagara , Masao Kawamura
发明人： Mikinori Kawaji , Toshihiko Takakura , Akihisa Uchida , Shigeo Kuroda , Yoichi Tamaki , Takeo Shiba , Kazuhiko Sagara , Masao Kawamura
IPC分类号： H01L21/762 , H01L21/763 , H01L29/732 , H01L27/12
CPC分类号： H01L21/763 , H01L21/76224 , H01L29/7325 , Y10S148/05
摘要： A bipolar type of semiconductor integrated circuit device is provided with U-shaped grooves which are formed by cutting a main surface of a semiconductor body to form isolation regions between bipolar transistors. A silicon oxide film can be formed in the U-shaped grooves by thermal oxidation simultaneously with the formation of a silicon oxide film used to form isolation regions between each collector contact region and base region. No separate step is needed for forming the silicon oxide film between the collector contact region and the base region. The thickness of the silicon oxide film can be controlled, and has a sufficient thickness even at its two edges, i.e., at its boundaries with the U-shaped grooves, so that the bipolar transistors exhibit good electrical characteristics. Namely, the collector resistance thereof does not increase, and the breakdown voltage at the pn junction between the collector region and the base region does not decrease. The U-shaped grooves can each comprise narrow and deep sub-grooves, with thick oxide films formed on the surfaces of the sub-grooves and a thick oxide film formed on a surface of an area between the sub-grooves, and with wiring formed on the oxide on the area between the sub-grooves.
摘要翻译：双极型半导体集成电路器件设置有通过切割半导体本体的主表面以在双极晶体管之间形成隔离区而形成的U形沟槽。可以通过热氧化在U形槽中形成氧化硅膜，同时形成用于在每个集电极接触区域和基极区域之间形成隔离区域的氧化硅膜。在集电极接触区域和基极区域之间形成氧化硅膜不需要单独的步骤。可以控制氧化硅膜的厚度，并且即使在其两个边缘，即与U形槽的边界处，也具有足够的厚度，使得双极晶体管表现出良好的电特性。也就是说，其集电极电阻不增加，并且集电极区域和基极区域之间的pn结处的击穿电压不降低。 U形槽可以各自包括窄的和深的子槽，其中形成在子槽的表面上的厚的氧化膜和形成在子槽之间的区域的表面上的厚氧化膜，并且形成有布线在子槽之间的区域上的氧化物上。

3. 发明授权

US5011788A Process of manufacturing semiconductor integrated circuit device and product formed thereby 失效
标题翻译：制造半导体集成电路器件的工艺和由此形成的产品
公开(公告)号：US5011788A
公开(公告)日：1991-04-30
申请号：US284557
申请日：1988-12-15
申请人： Mikinori Kawaji , Toshihiko Takakura , Akihisa Uchida , Shigeo Kuroda , Yoichi Tamaki , Takeo Shiba , Kazuhiko Sagara , Masao Kawamura
发明人： Mikinori Kawaji , Toshihiko Takakura , Akihisa Uchida , Shigeo Kuroda , Yoichi Tamaki , Takeo Shiba , Kazuhiko Sagara , Masao Kawamura
IPC分类号： H01L21/762 , H01L21/763 , H01L29/732
CPC分类号： H01L21/763 , H01L21/76224 , H01L29/7325 , Y10S148/05
摘要： A bipolar type of semiconductor integrated circuit device is provided with U-shaped grooves which are formed by cutting a main surface of a semiconductor body to form isolation regions between bipolar transistors. A silicon oxide film can be formed in the U-shaped grooves by thermal oxidation simultaneously with the formation of a silicon oxide film used to form isolation regions between each collector contact region and base region. No separate step is needed for forming the silicon oxide film between the collector contact region and the base region. The thickness of the silicon oxide film can be controlled, and has a sufficient thickness even at its two edges, i.e., at its boundaries with the U-shaped grooves, so that the bipolar transistors exhibit good electrical characteristics. Namely, the collector resistance thereof does not increase, and the breakdown voltage at the pn junction between the collector region and the base region does not decrease. The U-shaped grooves can each comprise narrow and deep sub-grooves, with thick oxide films formed on the surfaces of the sub-grooves and a thick oxide film formed on a surface of an area between the sub-grooves, and with wiring formed on the oxide on the area between the sub-grooves.

4. 发明授权

US5191224A Wafer scale of full wafer memory system, packaging method thereof, and wafer processing method employed therein 失效
标题翻译：全晶圆存储器系统的晶片尺寸，其封装方法和其中采用的晶片处理方法
公开(公告)号：US5191224A
公开(公告)日：1993-03-02
申请号：US627881
申请日：1990-12-13
申请人： Masanori Tazunoki , Hiromitsu Mishimagi , Makoto Homma , Toshiyuki Sakuta , Hisashi Nakamura , Keiji Sasaki , Minoru Enomoto , Toshihiko Satoh , Kunizo Sahara , Shigeo Kuroda , Kanji Otsuka , Masao Kawamura , Hinoko Kurosawa , Kazuya Ito
发明人： Masanori Tazunoki , Hiromitsu Mishimagi , Makoto Homma , Toshiyuki Sakuta , Hisashi Nakamura , Keiji Sasaki , Minoru Enomoto , Toshihiko Satoh , Kunizo Sahara , Shigeo Kuroda , Kanji Otsuka , Masao Kawamura , Hinoko Kurosawa , Kazuya Ito
IPC分类号： H01L23/14 , H01L23/32 , H01L23/538 , H01L25/065 , H01L25/07
CPC分类号： H01L23/147 , H01L23/32 , H01L23/5385 , H01L25/0652 , H01L25/073 , H01L2224/0401 , H01L2224/16225 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/48091 , H01L2224/48464 , H01L2224/48599 , H01L2224/48699 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01039 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/12042 , H01L2924/1305 , H01L2924/14 , H01L2924/15174 , H01L2924/15312 , H01L2924/16152 , H01L2924/3025
摘要： To achieve higher packaging density and one wafer level for a full-sized wafer memory, or wafer-scale integration memory system, the wafers are vertically stacked with each other at a predetermined interval. A packaging technique is improved in such a way that a memory system layout can be precisely realized and a precise through hole can be formed. Moreover, other chips are fixed on the wafer so as to achieve furthermore the high packaging density.
摘要翻译：为了实现全尺寸晶片存储器或晶片级积分存储器系统的更高的封装密度和一个晶片级，晶片以预定的间隔彼此垂直堆叠。改进了封装技术，使得可以精确地实现存储器系统布局并且可以形成精确的通孔。此外，其他芯片固定在晶片上，从而进一步实现高封装密度。

5. 发明授权

US5309011A Wafer scale or full wafer memory system, packaging method thereof, and wafer processing method employed therein 失效
标题翻译：晶圆规模或全晶圆存储器系统，其封装方法和其中采用的晶片处理方法
公开(公告)号：US5309011A
公开(公告)日：1994-05-03
申请号：US960848
申请日：1992-10-14
申请人： Masanori Tazunoki , Hiromitsu Mishimagi , Makoto Homma , Toshiyuki Sakuta , Hisashi Nakamura , Keiji Sasaki , Minoru Enomoto , Toshihiko Satoh , Kunizo Sahara , Shigeo Kuroda , Kanji Otsuka , Masao Kawamura , Hinoko Kurosawa , Kazuya Ito
发明人： Masanori Tazunoki , Hiromitsu Mishimagi , Makoto Homma , Toshiyuki Sakuta , Hisashi Nakamura , Keiji Sasaki , Minoru Enomoto , Toshihiko Satoh , Kunizo Sahara , Shigeo Kuroda , Kanji Otsuka , Masao Kawamura , Hinoko Kurosawa , Kazuya Ito
IPC分类号： H01L23/14 , H01L23/32 , H01L23/538 , H01L25/065 , H01L25/07 , H01L27/02 , H01L27/10 , H01L27/15
CPC分类号： H01L23/147 , H01L23/32 , H01L23/5385 , H01L25/0652 , H01L25/073 , H01L2224/0401 , H01L2224/16225 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/48091 , H01L2224/48464 , H01L2224/48599 , H01L2224/48699 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01039 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/12042 , H01L2924/1305 , H01L2924/14 , H01L2924/15174 , H01L2924/15312 , H01L2924/16152 , H01L2924/3025
摘要： To achieve higher packaging density and one wafer level for a full-sized wafer memory, or wafer-scale integration memory system, the wafers are vertically stacked with each other at a predetermined interval. A packaging technique is improved in such a way that a memory system layout can be precisely realized and a precise through hole can be formed. Moreover, other chips are fixed on the wafer so as to achieve furthermore the high packaging density.
摘要翻译：为了实现全尺寸晶片存储器或晶片级积分存储器系统的更高的封装密度和一个晶片级，晶片以预定的间隔彼此垂直堆叠。改进了封装技术，使得可以精确地实现存储器系统布局并且可以形成精确的通孔。此外，其他芯片固定在晶片上，从而进一步实现高封装密度。

6. 发明授权

US4739125A Electric component part having lead terminals 失效
标题翻译：具有引线端子的电气部件
公开(公告)号：US4739125A
公开(公告)日：1988-04-19
申请号：US907006
申请日：1986-09-15
申请人： Yutaka Watanabe , Fumiyuki Kobayashi , Masao Sekibata , Shigeo Kuroda , Akio Yasukawa , Shigejiro Sekine
发明人： Yutaka Watanabe , Fumiyuki Kobayashi , Masao Sekibata , Shigeo Kuroda , Akio Yasukawa , Shigejiro Sekine
IPC分类号： H01L23/50 , H01L23/495 , H01L23/498 , H05K1/02 , H05K1/18 , H05K3/34
CPC分类号： H01L23/49555 , H01L23/49811 , H05K3/3426 , H01L2924/0002 , H05K1/0271 , H05K2201/10689 , H05K2201/10719 , H05K2201/10727 , H05K2201/10757 , H05K2201/10946 , Y02P70/613
摘要： An electric component part has its lead terminals bent in thickness directions in a middle section thereof at least two positions so that a step section virtually in parallel to the bottom of a circuit substrate is formed with the intention of absorbing the external force applied to the part by chaging the shape of the lead terminals. Increase in the part layout area due to the formation of the horizontal step section can be avoided, when necessary, by shifting the terminal lead out position on the component part inward thereby to minimize the jetty dimensions.
摘要翻译：电气部件的导线端子在其中间部分的至少两个位置处具有在厚度方向上弯曲的引线端子，从而形成与电路基板的底部实际上平行的台阶部分，其目的是吸收施加到部件的外力通过跟踪引线端子的形状。当需要时，可以避免由于形成水平台阶部而导致的部件布局区域的增加，通过将部件部件上的端子引出位置向内移位，从而使喷射尺寸最小化。

7. 发明授权

US5223454A Method of manufacturing semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US5223454A
公开(公告)日：1993-06-29
申请号：US760889
申请日：1991-09-17
申请人： Takayuki Uda , Tasuku Tanaka , Yoshiaki Emoto , Shigeo Kuroda
发明人： Takayuki Uda , Tasuku Tanaka , Yoshiaki Emoto , Shigeo Kuroda
IPC分类号： H01L23/31 , H01L25/065 , H01L25/16
CPC分类号： H01L23/3121 , H01L25/0655 , H01L25/165 , H01L2224/1147 , H01L2224/11472 , H01L2224/11474 , H01L2224/16145 , H01L2224/45124 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01014 , H01L2924/01039 , H01L2924/01079 , H01L2924/12032 , H01L2924/1305 , H01L2924/14 , H01L2924/1532 , H01L2924/16152 , H01L2924/181 , H01L2924/19041 , Y10S148/10 , Y10S438/951
摘要： A method of manufacturing a semiconductor integrated circuit device wherein a conductor film is formed on a front surface of a substrate by a lift-off technique; comprising forming a first resist film on that area of the substrate surface on which the conductor film is not formed, forming a second resist film on the whole substrate surface including the first resist film and a conductor film forming area of the substrate surface, providing a first opening for forming the conductor film in a conductor film forming area of the second resist film and also providing a second opening for forming a dummy conductor film in that area of the second resist film in which the conductor film is not formed, depositing the conductor film on the whole substrate surface including the substrate surface inside the first opening, the first resist film inside the second opening and the second resist film, and removing the second resist film and the first resist film respectively, so as to leave the conductor film inside the first opening and to remove the conductor film on the second resist film and the dummy conductor film on the first resist film.
摘要翻译：一种制造半导体集成电路器件的方法，其中通过剥离技术在衬底的前表面上形成导体膜; 包括在其上未形成导体膜的基板表面的区域上形成第一抗蚀剂膜，在包括第一抗蚀剂膜和基板表面的导体膜形成区域的整个基板表面上形成第二抗蚀剂膜，用于在第二抗蚀剂膜的导体膜形成区域中形成导体膜的第一开口，并且还在其中未形成导体膜的第二抗蚀剂膜的区域中提供用于形成虚设导体膜的第二开口，在包括第一开口内的基板表面，第二开口内的第一抗蚀剂膜和第二抗蚀剂膜的整个基板表面上分别去除第二抗蚀剂膜和第一抗蚀剂膜，以便将导体膜留在内部第一开口并且去除第二抗蚀剂膜上的导体膜和第一抗蚀剂膜上的虚设导体膜。

8. 发明授权

US4965653A Semiconductor device and method of mounting the semiconductor device 失效
标题翻译：半导体装置及其安装方法
公开(公告)号：US4965653A
公开(公告)日：1990-10-23
申请号：US489714
申请日：1990-02-28
申请人： Kanji Otsuka , Shigeo Kuroda , Katsuyuki Sato , Hisashi Nakamura , Shinichi Shouji
发明人： Kanji Otsuka , Shigeo Kuroda , Katsuyuki Sato , Hisashi Nakamura , Shinichi Shouji
IPC分类号： H01L21/60 , H01L23/00 , H01L23/32 , H01L23/498 , H01L25/065 , H01L29/06
CPC分类号： H01L23/562 , H01L23/32 , H01L23/49827 , H01L24/19 , H01L24/32 , H01L25/0657 , H01L29/0657 , H01L2223/54493 , H01L2224/04105 , H01L2224/20 , H01L2224/211 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06524 , H01L2225/06555 , H01L2225/06589 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/10329 , H01L2924/12041 , H01L2924/13091 , H01L2924/14 , H01L2924/15151 , H01L2924/15787 , H01L2924/181 , H01L2924/18162
摘要： The present invention discloses a suitable mounting of a wafer scale LSI (wafer scale integration) (WSI) in which a slit formed in a wafer is fit to a connector, a U-shaped reinforcing rubber member is disposed at the circumferential edge of the wafer, or a flexible adhesive is used for bonding a substrate formed with through-holes and a wafer, to provide a WSI mounting structure of high integration degree and high reliability. Furthermore, a method of efficient mounting by conducting the wiring of the wafer and the connection with the external terminal of the chip in one identical production step is disclosed.
摘要翻译：本发明公开了一种晶片规模LSI（晶片规模集成）（WSI）的合适安装，其中形成在晶片中的狭缝与连接器配合，U形加强橡胶件设置在晶片的周边边缘或柔性粘合剂用于接合形成有通孔和晶片的基板，以提供高集成度和高可靠性的WSI安装结构。此外，公开了通过在一个相同的制造步骤中导通晶片的布线和与芯片的外部端子的连接来有效地安装的方法。

9. 发明授权

US4469535A Method of fabricating semiconductor integrated circuit devices 失效
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US4469535A
公开(公告)日：1984-09-04
申请号：US457219
申请日：1983-01-11
申请人： Shigeo Kuroda , Takahiko Takahashi , Akio Anzai
发明人： Shigeo Kuroda , Takahiko Takahashi , Akio Anzai
IPC分类号： H01L29/73 , H01L21/331 , H01L21/76 , H01L21/762 , H01L21/8222 , H01L29/72 , H01L21/22
CPC分类号： H01L21/8222 , H01L21/76202 , H01L29/72
摘要： A method of fabricating semiconductor integrated circuit devices having a semiconductor region in a position separated by a predetermined distance from a dielectric isolating region provided on the surface of a semiconductor wafer, comprising the steps of forming a first mask to define the dielectric isolating region and semiconductor region, forming a second mask over the first mask so as to cover the region which is to become the semiconductor region, and removing the second mask after the dielectric isolating region has been formed by the first and second masks, to form the semiconductor region. The method thus permits the semiconductor region to be self-aligned with the dielectric isolating region.
摘要翻译：一种制造半导体集成电路器件的方法，该半导体集成电路器件具有与设置在半导体晶片的表面上的绝缘隔离区隔开预定距离的位置的半导体区域，包括以下步骤：形成第一掩模以限定绝缘隔离区域和半导体区域，在第一掩模上形成第二掩模，以覆盖将成为半导体区域的区域，以及在通过第一和第二掩模形成介电隔离区域之后去除第二掩模，以形成半导体区域。因此，该方法允许半导体区域与电介质隔离区域自对准。

10. 发明授权

US5067007A Semiconductor device having leads for mounting to a surface of a printed circuit board 失效
标题翻译：具有用于安装到印刷电路板表面的引线的半导体器件
公开(公告)号：US5067007A
公开(公告)日：1991-11-19
申请号：US645357
申请日：1991-01-24
申请人： Kanji Otsuka , Masao Kato , Takashi Kumagai , Mitsuo Usami , Shigeo Kuroda , Kunizo Sahara , Takeo Yamada , Seiji Miyamoto , Yuuji Shirai , Takayuki Okinaga , Kazutoshi Kubo , Hiroshi Tachi , Masayuki Kawashima
发明人： Kanji Otsuka , Masao Kato , Takashi Kumagai , Mitsuo Usami , Shigeo Kuroda , Kunizo Sahara , Takeo Yamada , Seiji Miyamoto , Yuuji Shirai , Takayuki Okinaga , Kazutoshi Kubo , Hiroshi Tachi , Masayuki Kawashima
IPC分类号： H01L23/50 , H01L23/433 , H01L23/495 , H01L23/498 , H05K3/34
CPC分类号： H01L23/49555 , H01L23/433 , H01L23/49579 , H01L23/49811 , H05K3/3426 , H01L2224/16225 , H01L2224/32225 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/73253 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01013 , H01L2924/01025 , H01L2924/01029 , H01L2924/01039 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15174 , H01L2924/15312 , H01L2924/16152 , H01L2924/19105 , H01L2924/3011 , H05K2201/0308 , H05K2201/10318 , H05K2201/10681 , H05K2201/10704 , H05K2201/10909 , H05K2201/2081 , Y02P70/613
摘要： Attempts have been made to increase the number of pins of packages accompanying the trend toward fabricating integrated circuits highly densely and in smaller sizes. The present invention provides technology for improving reliability in fabricating packages of the surface-mounted type that have increased number of pins. That is, when the packages are mounted on the wiring substrate, the lead pins that receive load from the axial direction exhibit bending strength which is smaller than the junction strength of solder at the junction portions. To achieve this object, the lead pins are made of a material having large resiliency such as a fiber-reinforced material, a transformation pseudo elastic material, an ultra-high tension material, or a heat-resistant ultra-high tension material.
摘要翻译：随着制造高密度和小尺寸集成电路的趋势，已经尝试增加封装引脚的数量。本发明提供了提高具有增加的引脚数的表面安装型封装的可靠性的技术。也就是说，当封装被安装在布线基板上时，从轴向接收负载的引线销显示出小于接合部处的焊料的接合强度的弯曲强度。为了实现该目的，引脚由具有大弹性的材料制成，例如纤维增强材料，变形假弹性材料，超高张力材料或耐热超高张力材料。

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