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1. 发明授权

US07027335B2 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US07027335B2
公开(公告)日：2006-04-11
申请号：US10720980
申请日：2003-11-24
申请人： Mikihiko Ito , Masaru Koyanagi , Takashi Taira
发明人： Mikihiko Ito , Masaru Koyanagi , Takashi Taira
IPC分类号： G11C7/00
CPC分类号： G11C7/065 , G11C11/4091 , G11C2207/005 , G11C2207/065 , G11C2207/2281
摘要： A semiconductor storage device comprises a memory cell array including memory cells, and bit lines for transfer of data in the memory cells; an amplifier circuit connected to the bit lines to amplify data in the memory cells; a first switching element connected between the bit lines and the amplifier circuit; a first reference voltage source which applies to the gate of the first switching element a voltage for turning the first switching element ON; a second switching element and a third switching element connected in series between the gate of the first switching element and the first reference voltage source, said second switching element and said third switching element being connected in parallel to each other; a second reference voltage source which applies to the gates of the second and third switching elements a voltage for turning the second and third switching elements ON; and a first timing shift circuit connected between the gate of the third switching element and the second reference voltage source to delay the operation of the third switching element from the operation of the second switching element.
摘要翻译：半导体存储装置包括存储单元阵列，其包括存储单元，以及用于在存储单元中传送数据的位线; 连接到位线的放大器电路，以放大存储器单元中的数据; 连接在位线与放大电路之间的第一开关元件; 第一参考电压源，其向第一开关元件的栅极施加用于使第一开关元件导通的电压; 第二开关元件和第三开关元件串联连接在第一开关元件的栅极和第一参考电压源之间，所述第二开关元件和所述第三开关元件彼此并联连接; 第二参考电压源，其向第二和第三开关元件的栅极施加用于使第二和第三开关元件接通的电压; 以及连接在第三开关元件的栅极和第二参考电压源之间的第一定时偏移电路，用于延迟第三开关元件的操作与第二开关元件的操作。

2. 发明授权

US06577551B2 Semiconductor integrated circuit having a built-in data storage circuit for nonvolatile storage of control data 失效
标题翻译：具有用于非易失存储控制数据的内置数据存储电路的半导体集成电路
公开(公告)号：US06577551B2
公开(公告)日：2003-06-10
申请号：US10007148
申请日：2001-12-04
申请人： Mikihiko Ito , Masaru Koyanagi , Takahiko Hara , Satoru Takase , Tohru Kimura
发明人： Mikihiko Ito , Masaru Koyanagi , Takahiko Hara , Satoru Takase , Tohru Kimura
IPC分类号： G11C700
CPC分类号： G11C17/18 , G11C17/16
摘要： A semiconductor integrated circuit includes a control data storage circuit (6) having nonvolatile storage devices with programmed control data and a latch circuit for holding data read out from the storage devices, and a read control circuit (7) for controlling read operations of the control data, which are built in a semiconductor chip. The control data storage circuit (6) is divided into groups (1, 2), and the read control circuit (7) generates read control signals for the groups (1, 2) at different timings, using an output of an internal potential detecting circuit 41 as the timing reference, thereby preventing the peak of power consumption from unacceptably rising during reading operations.
摘要翻译：半导体集成电路包括具有编程控制数据的非易失性存储装置的控制数据存储电路（6）和用于保存从存储装置读出的数据的锁存电路，以及用于控制控制的读取操作的读取控制电路（7）数据，内置在半导体芯片中。控制数据存储电路（6）被分成组（1,2），读取控制电路（7）使用内部电位检测的输出在不同的定时产生用于组（1,2）的读取控制信号电路41作为定时参考，从而防止功耗峰值在读取操作期间不可接受地上升。

3. 发明授权

US07843089B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07843089B2
公开(公告)日：2010-11-30
申请号：US11780240
申请日：2007-07-19
申请人： Mikihiko Ito , Masaru Koyanagi , Katsuki Matsudera
发明人： Mikihiko Ito , Masaru Koyanagi , Katsuki Matsudera
IPC分类号： H01B7/30
CPC分类号： G11C5/14 , G11C5/02 , G11C5/025 , H01L2224/48091 , H01L2224/48227 , H01L2225/06562 , H01L2924/13091 , H01L2924/15192 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device comprises a board; a semiconductor chip; a memory controller operative to control the semiconductor chip; and a power supply chip having a capacitor. The semiconductor chip is stacked on the board. The memory controller and the power supply chip are stacked on the semiconductor chip. The capacitor is used to stabilize the voltage applied to the semiconductor chip.
摘要翻译：半导体器件包括板; 半导体芯片; 存储器控制器，用于控制半导体芯片; 以及具有电容器的电源芯片。半导体芯片堆叠在板上。存储器控制器和电源芯片堆叠在半导体芯片上。电容器用于稳定施加到半导体芯片的电压。

4. 发明申请

US20080019203A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080019203A1
公开(公告)日：2008-01-24
申请号：US11780240
申请日：2007-07-19
申请人： Mikihiko ITO , Masaru Koyanagi , Katsuki Matsudera
发明人： Mikihiko ITO , Masaru Koyanagi , Katsuki Matsudera
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C5/02 , G11C5/025 , H01L2224/48091 , H01L2224/48227 , H01L2225/06562 , H01L2924/13091 , H01L2924/15192 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device comprises a board; a semiconductor chip; a memory controller operative to control the semiconductor chip; and a power supply chip having a capacitor. The semiconductor chip is stacked on the board. The memory controller and the power supply chip are stacked on the semiconductor chip. The capacitor is used to stabilize the voltage applied to the semiconductor chip.
摘要翻译：半导体器件包括板; 半导体芯片; 存储器控制器，用于控制半导体芯片; 以及具有电容器的电源芯片。半导体芯片堆叠在板上。存储器控制器和电源芯片堆叠在半导体芯片上。电容器用于稳定施加到半导体芯片的电压。

5. 发明申请

US20050213395A1 Dynamic type semiconductor memory apparatus 失效
标题翻译：动态型半导体存储装置
公开(公告)号：US20050213395A1
公开(公告)日：2005-09-29
申请号：US11079369
申请日：2005-03-15
申请人： Mikihiko Ito , Masaru Koyanagi
发明人： Mikihiko Ito , Masaru Koyanagi
IPC分类号： G11C11/409 , G11C5/00 , G11C11/401
CPC分类号： G11C7/1018 , G11C7/1069 , G11C7/1096 , G11C11/4045 , G11C11/4076 , G11C11/4093 , G11C11/4097
摘要： A dynamic type semiconductor memory apparatus performs an operation of continuous column access at a high speed while minimizing an increase of a chip size. The dynamic type semiconductor memory apparatus includes first and second memory cell groups divided based on a column address, a first bit line connected to the first memory cell group, a second bit line connected to the second memory cell group, first and second local data lines, and a column selection unit configured to connect the first and second bit lines to the first and second local data line based on a column address. The dynamic type semiconductor memory apparatus further includes first and second master data line, a local data line selecting unit configured to connect the first and second local data lines to the first and second master data lines, respectively, a DBR configured to read data from the first or second master data lines, and a DWB configured to write data to the first or second master data lines.
摘要翻译：动态类型半导体存储装置在最大限度地提高芯片尺寸的同时，高速地执行连续的列存取操作。动态型半导体存储装置包括基于列地址划分的第一和第二存储单元组，连接到第一存储单元组的第一位线，连接到第二存储单元组的第二位线，第一和第二本地数据线以及列选择单元，被配置为基于列地址将第一和第二位线连接到第一和第二本地数据线。动态型半导体存储装置还包括第一和第二主数据线，本地数据线选择单元，被配置为分别将第一和第二本地数据线连接到第一和第二主数据线，DBR被配置为从第一或第二主数据线，以及被配置为将数据写入到第一或第二主数据线的DWB。

6. 发明授权

US07133303B2 Dynamic type semiconductor memory apparatus 失效
标题翻译：动态型半导体存储装置
公开(公告)号：US07133303B2
公开(公告)日：2006-11-07
申请号：US11079369
申请日：2005-03-15
申请人： Mikihiko Ito , Masaru Koyanagi
发明人： Mikihiko Ito , Masaru Koyanagi
IPC分类号： G11C5/06
CPC分类号： G11C7/1018 , G11C7/1069 , G11C7/1096 , G11C11/4045 , G11C11/4076 , G11C11/4093 , G11C11/4097
摘要： A dynamic type semiconductor memory apparatus performs an operation of continuous column access at a high speed while minimizing an increase of a chip size. The dynamic type semiconductor memory apparatus includes first and second memory cell groups divided based on a column address, a first bit line connected to the first memory cell group, a second bit line connected to the second memory cell group, first and second local data lines, and a column selection unit configured to connect the first and second bit lines to the first and second local data line based on a column address. The dynamic type semiconductor memory apparatus further includes first and second master data line, a local data line selecting unit configured to connect the first and second local data lines to the first and second master data lines, respectively, a DBR configured to read data from the first or second master data lines, and a DWB configured to write data to the first or second master data lines.
摘要翻译：动态型半导体存储装置在最大限度地提高芯片尺寸的同时，高速地进行连续的列存取操作。动态型半导体存储装置包括基于列地址划分的第一和第二存储单元组，连接到第一存储单元组的第一位线，连接到第二存储单元组的第二位线，第一和第二本地数据线以及列选择单元，被配置为基于列地址将第一和第二位线连接到第一和第二本地数据线。动态型半导体存储装置还包括第一和第二主数据线，本地数据线选择单元，被配置为分别将第一和第二本地数据线连接到第一和第二主数据线，DBR被配置为从第一或第二主数据线，以及被配置为将数据写入到第一或第二主数据线的DWB。

7. 发明申请

US20090051020A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法和半导体器件
公开(公告)号：US20090051020A1
公开(公告)日：2009-02-26
申请号：US12035813
申请日：2008-02-22
申请人： Takashi Taira , Masaru Koyanagi
发明人： Takashi Taira , Masaru Koyanagi
IPC分类号： H01L21/58 , H01L23/495
CPC分类号： H01L23/4951 , H01L23/49537 , H01L23/49575 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48091 , H01L2224/49 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/30107 , H01L2224/45099 , H01L2224/05599
摘要： A semiconductor memory device includes: A method of manufacturing a semiconductor device, wherein a semiconductor chip is mounted on a lead frame including a plurality of lead lines, and terminals included in the semiconductor chip are connected to the lead lines, thereby to manufacture the semiconductor device, comprising the steps of: arranging distal end parts of the plurality of lead lines at equal intervals along a direction of a first axis, the distal end parts being connected with the terminals included in the semiconductor chip; arranging terminal parts for inputting/outputting signals, at equal intervals along a direction of a second axis; shaping intermediate parts for connecting the distal end parts and the terminal parts, so as to be bent between the distal end parts and the terminal parts; forming a half number of the plurality of lead lines and the remaining half number of the plurality of lead lines so as to have a shape of line symmetry with respect to the second axis; and mounting the semiconductor chip on a front surface side of a package.
摘要翻译：半导体存储器件包括：半导体器件的制造方法，其中将半导体芯片安装在包括多根引线的引线框架上，并且包含在半导体芯片中的端子连接到引线，从而制造半导体装置，包括以下步骤：沿着第一轴线的方向以相等的间隔布置多条引线的远端部分，所述远端部分与包括在所述半导体芯片中的端子连接; 沿着第二轴的方向以等间隔布置用于输入/输出信号的端子部分; 成形用于连接远端部分和端子部分的中间部分，以在远端部分和端部部分之间弯曲; 形成所述多根引线的半数和所述多根引线的剩余的半数，使其相对于所述第二轴具有线对称的形状; 以及将半导体芯片安装在封装的前表面侧。

8. 发明授权

US08558602B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08558602B2
公开(公告)日：2013-10-15
申请号：US12884533
申请日：2010-09-17
申请人： Ryo Fukuda , Masaru Koyanagi
发明人： Ryo Fukuda , Masaru Koyanagi
IPC分类号： H03L5/00
CPC分类号： H03K3/356113
摘要： According to one embodiment, a semiconductor integrated circuit includes first and second level shift circuits. The first level shifter includes a plurality of transistors and is connected to a power source voltage supply node of a first power source system and to which a first signal of a second power source system and a level inversion signal of the first signal are input. The second level shifter includes a plurality of transistors and is connected to the power source voltage supply node of the first power source system and to which the level inversion signal of the first signal of the second power source system and an output signal of the first level shifter are input. The first and second level shifters have substantially the same circuit configuration and driving abilities of corresponding ones of the transistors in the first and second level shifters are substantially set equal.
摘要翻译：根据一个实施例，半导体集成电路包括第一和第二电平移位电路。第一电平移位器包括多个晶体管，并连接到第一电源系统的电源电压供应节点，第二电源系统的第一信号和第一信号的电平反转信号被输入到该第一电源系统。第二电平移位器包括多个晶体管，并连接到第一电源系统的电源电压供应节点，并且第二电源系统的第一信号的电平反转信号和第一电平系统的输出信号移位器被输入。第一和第二电平移位器具有基本上相同的电路配置，并且第一和第二电平移位器中对应的晶体管的驱动能力基本上相等。

9. 发明授权

US07911844B2 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07911844B2
公开(公告)日：2011-03-22
申请号：US12337808
申请日：2008-12-18
申请人： Dai Nakamura , Hiroyuki Kutsukake , Kenji Gomikawa , Takeshi Shimane , Mitsuhiro Noguchi , Koji Hosono , Masaru Koyanagi , Takashi Aoi
发明人： Dai Nakamura , Hiroyuki Kutsukake , Kenji Gomikawa , Takeshi Shimane , Mitsuhiro Noguchi , Koji Hosono , Masaru Koyanagi , Takashi Aoi
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/24
摘要： A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.
摘要翻译：非挥发性半导体存储装置包括：具有布置在其中的存储单元的存储单元阵列，所述存储单元以非易失性方式存储数据; 以及向存储单元传送电压的多个转移晶体管，用于相对于存储单元进行数据读取，写入和擦除操作的电压。每个转移晶体管包括：通过栅极绝缘膜形成在半导体衬底上的栅电极; 以及形成为将栅极电极夹在其间并用作漏极/源极层的扩散层。上层布线设置在扩散层上方，并具有预定电压，以至少在传输晶体管导通时防止扩散层的耗尽。

10. 发明授权

US07359255B2 Semiconductor device having auto trimming function for automatically adjusting voltage 失效
标题翻译：具有自动修整功能的半导体器件，用于自动调节电压
公开(公告)号：US07359255B2
公开(公告)日：2008-04-15
申请号：US11438345
申请日：2006-05-23
申请人： Tohru Kimura , Masahiro Yoshihara , Masaru Koyanagi
发明人： Tohru Kimura , Masahiro Yoshihara , Masaru Koyanagi
IPC分类号： G11C7/00
CPC分类号： H03M1/1061 , G11C5/147 , G11C16/30 , G11C29/02 , G11C29/021 , G11C29/028
摘要： A reference voltage generation circuit generates a reference voltage. An internal voltage generation circuit generates an internal voltage on the basis of the reference voltage generated by the reference voltage generation circuit. A first trimming circuit trims the internal voltage. During trimming of the internal voltage, the first trimming circuit trims an externally supplied first target voltage in accordance with first trimming data. The first trimming circuit ends the trimming when the first target voltage meets a given condition for the reference voltage.
摘要翻译：参考电压产生电路产生参考电压。内部电压产生电路基于由参考电压产生电路产生的参考电压产生内部电压。第一个微调电路修剪内部电压。在微调内部电压期间，第一微调电路根据第一微调数据修正外部提供的第一目标电压。当第一目标电压满足参考电压的给定条件时，第一微调电路结束修整。

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