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1. 发明授权

US08384441B2 Semiconductor integrated circuit having a squelch circuit 有权
标题翻译：具有静噪电路的半导体集成电路
公开(公告)号：US08384441B2
公开(公告)日：2013-02-26
申请号：US13009032
申请日：2011-01-19
申请人： Katsuki Matsudera
发明人： Katsuki Matsudera
IPC分类号： H03K5/22
CPC分类号： H03K5/24
摘要： A semiconductor integrated circuit has a squelch circuit which has a first noninverting input terminal and a first inverting input terminal, which compares differential amplitude between a signal which is input to the first noninverting input terminal and a signal which is input to the first inverting input terminal with a preset threshold, and which outputs a signal depending upon a result of the comparison. The semiconductor integrated circuit has a first switch circuit between a first reception terminal and the first noninverting input terminal. The semiconductor integrated circuit has a second switch circuit between a second reception terminal and the first inverting input terminal. The semiconductor integrated circuit has a third switch circuit between the first reception terminal and the first inverting input terminal. The semiconductor integrated circuit has a fourth switch circuit between the second reception terminal and the first noninverting input terminal.
摘要翻译：半导体集成电路具有静噪电路，其具有第一同相输入端子和第一反相输入端子，该第一反相输入端子将输入到第一同相输入端子的信号和输入到第一反相输入端子的信号之间的差分幅度进行比较具有预设阈值，并且根据比较的结果输出信号。半导体集成电路在第一接收端和第一同相输入端之间具有第一开关电路。半导体集成电路在第二接收端和第一反相输入端之间具有第二开关电路。半导体集成电路在第一接收端和第一反相输入端之间具有第三开关电路。半导体集成电路在第二接收端子和第一同相输入端子之间具有第四开关电路。

2. 发明申请

US20100327904A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20100327904A1
公开(公告)日：2010-12-30
申请号：US12875612
申请日：2010-09-03
申请人： Katsuki Matsudera
发明人： Katsuki Matsudera
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H03F1/56 , H03F3/45183 , H03F2200/222 , H03F2200/387 , H03F2203/45691
摘要： A semiconductor integrated circuit includes a control signal generating circuit which is configured to set, at least at a time of a first state, first and fifth control signals at a first voltage level, and second, third and fourth control signals at a second voltage level, and to set, at a time of a second state, the first to fourth control signals at the first voltage level, and the fifth control signal at an arbitrary voltage level.
摘要翻译：半导体集成电路包括：控制信号发生电路，其被配置为至少在第一状态时设定第一和第五控制信号处于第一电压电平;以及第二，第三和第四控制信号，其处于第二电压电平并且在第二状态时将第一电压电平的第一至第四控制信号和任意电压电平的第五控制信号置位。

3. 发明申请

US20060226871A1 Data input/output circuit included in semiconductor memory device 失效
标题翻译：数据输入/输出电路包括在半导体存储器件中
公开(公告)号：US20060226871A1
公开(公告)日：2006-10-12
申请号：US11391371
申请日：2006-03-29
申请人： Mikihiko Ito , Katsuki Matsudera
发明人： Mikihiko Ito , Katsuki Matsudera
IPC分类号： H03K19/173
CPC分类号： G11C7/1036 , G11C7/1039 , G11C7/1051 , G11C7/106 , H03K3/356139
摘要： A control circuit receives an external control signal in synchronism with an internal clock and generates an address signal and internal control signals. A data multiplexer has a plurality of input parallel lines and a plurality of output parallel lines and is switched to one of a first output state and a second output state in accordance with the internal control signal. In the first state, the data multiplexer outputs parallel data, which is input to the plurality of input parallel lines and read out from the memory core unit, to the plurality of output parallel lines corresponding to the plurality of input parallel lines. In the second state, the data multiplexer selects 1-bit data of the parallel data input to the plurality of input parallel lines and outputs the 1-bit data to the plurality of output parallel lines. A conversion circuit converts the parallel data into serial data.
摘要翻译：控制电路与内部时钟同步地接收外部控制信号，并产生地址信号和内部控制信号。数据多路复用器具有多个输入并行线路和多条输出并行线路，并且根据内部控制信号被切换到第一输出状态和第二输出状态之一。在第一状态下，数据多路复用器将输入到多条输入并行线并从存储器核心单元读出的并行数据输出到与多条输入并行线对应的多条输出并行线。在第二状态下，数据多路复用器选择输入到多条输入并行线的并行数据的1位数据，并将1位数据输出到多条输出并行线。 A转换电路将并行数据转换为串行数据。

4. 发明申请

US20120194225A1 DIFFERENTIAL OUTPUT BUFFER 有权
标题翻译：差分输出缓冲器
公开(公告)号：US20120194225A1
公开(公告)日：2012-08-02
申请号：US13238200
申请日：2011-09-21
申请人： Junichiro Shirai , Katsuki Matsudera
发明人： Junichiro Shirai , Katsuki Matsudera
IPC分类号： H03K3/00
CPC分类号： H03K19/018528 , H04L25/0272
摘要： According to one embodiment, a main driver is configured to shift the level of a differential signal. A bypass circuit is configured to bypass current flowing through the main driver in such a manner as to contain the change amount of current running through the main driver flowing from a high power supply potential to a low power supply potential within a fixed range upon transition between an operating state and a standby state of the main driver.
摘要翻译：根据一个实施例，主驱动器被配置为移位差分信号的电平。旁路电路被配置成以流过主驱动器的电流来旁路电流，以便包含在从主电源电位流过的主驱动器中流动的电流的变化量在固定的范围内，主驱动器的操作状态和待机状态。

5. 发明申请

US20110181321A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20110181321A1
公开(公告)日：2011-07-28
申请号：US13009032
申请日：2011-01-19
申请人： Katsuki Matsudera
发明人： Katsuki Matsudera
IPC分类号： H03K5/22
CPC分类号： H03K5/24
摘要： A semiconductor integrated circuit has a squelch circuit which has a first noninverting input terminal and a first inverting input terminal, which compares differential amplitude between a signal which is input to the first noninverting input terminal and a signal which is input to the first inverting input terminal with a preset threshold, and which outputs a signal depending upon a result of the comparison. The semiconductor integrated circuit has a first switch circuit between a first reception terminal and the first noninverting input terminal. The semiconductor integrated circuit has a second switch circuit between a second reception terminal and the first inverting input terminal. The semiconductor integrated circuit has a third switch circuit between the first reception terminal and the first inverting input terminal. The semiconductor integrated circuit has a fourth switch circuit between the second reception terminal and the first noninverting input terminal.
摘要翻译：半导体集成电路具有静噪电路，其具有第一同相输入端子和第一反相输入端子，该第一反相输入端子将输入到第一同相输入端子的信号和输入到第一反相输入端子的信号之间的差分幅度进行比较具有预设阈值，并且根据比较的结果输出信号。半导体集成电路在第一接收端和第一同相输入端之间具有第一开关电路。半导体集成电路在第二接收端和第一反相输入端之间具有第二开关电路。半导体集成电路在第一接收端和第一反相输入端之间具有第三开关电路。半导体集成电路在第二接收端子和第一同相输入端子之间具有第四开关电路。

6. 发明授权

US07368939B2 Data input/output circuit included in semiconductor memory device 失效
标题翻译：数据输入/输出电路包括在半导体存储器件中
公开(公告)号：US07368939B2
公开(公告)日：2008-05-06
申请号：US11391371
申请日：2006-03-29
申请人： Mikihiko Ito , Katsuki Matsudera
发明人： Mikihiko Ito , Katsuki Matsudera
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： G11C7/1036 , G11C7/1039 , G11C7/1051 , G11C7/106 , H03K3/356139
摘要： A control circuit receives an external control signal in synchronism with an internal clock and generates an address signal and internal control signals. A data multiplexer has a plurality of input parallel lines and a plurality of output parallel lines and is switched to one of a first output state and a second output state in accordance with the internal control signal. In the first state, the data multiplexer outputs parallel data, which is input to the plurality of input parallel lines and read out from the memory core unit, to the plurality of output parallel lines corresponding to the plurality of input parallel lines. In the second state, the data multiplexer selects 1-bit data of the parallel data input to the plurality of input parallel lines and outputs the 1-bit data to the plurality of output parallel lines. A conversion circuit converts the parallel data into serial data.
摘要翻译：控制电路与内部时钟同步地接收外部控制信号，并产生地址信号和内部控制信号。数据多路复用器具有多个输入并行线路和多条输出并行线路，并且根据内部控制信号被切换到第一输出状态和第二输出状态之一。在第一状态下，数据多路复用器将输入到多条输入并行线并从存储器核心单元读出的并行数据输出到与多条输入并行线对应的多条输出并行线。在第二状态下，数据多路复用器选择输入到多条输入并行线的并行数据的1位数据，并将1位数据输出到多条输出并行线。 A转换电路将并行数据转换为串行数据。

7. 发明申请

US20070076832A1 Semiconductor integrated circuit and correcting method of the same 审中-公开
标题翻译：半导体集成电路及其校正方法相同
公开(公告)号：US20070076832A1
公开(公告)日：2007-04-05
申请号：US11542226
申请日：2006-10-04
申请人： Katsuki Matsudera
发明人： Katsuki Matsudera
IPC分类号： H04L7/00 , H03D3/24
CPC分类号： H03L7/18 , H03L7/0995 , H04L7/033
摘要： According to an aspect of the embodiment, a semiconductor integrated circuit comprises: a multiphase clock generating circuit generating, in response to an input voltage, a first pair of clocks having reverse phases to each other and a second pair of clocks having phases which are substantially orthogonal to the phases of the first pair of clocks; a correcting circuit generating first and second output clock pairs by correcting a phase difference of the first and second clock pairs and duty cycles of the first and second clock pairs and a difference in phase between the first and second clock pairs; and a control circuit controlling the correcting circuit by detecting duty cycles of the first and second output clock pairs and a difference in phase between the first and second output clock pairs.
摘要翻译：根据实施例的一个方面，一种半导体集成电路包括：多相时钟产生电路，响应于输入电压产生彼此具有反相的第一对时钟和第二对时钟，其相位基本上是与第一对时钟的相位正交; 校正电路，通过校正第一和第二时钟对的相位差和第一和第二时钟对的占空比以及第一和第二时钟对之间的相位差来产生第一和第二输出时钟对; 以及控制电路，通过检测第一和第二输出时钟对的占空比以及第一和第二输出时钟对之间的相位差来控制校正电路。

8. 发明授权

US07808269B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07808269B2
公开(公告)日：2010-10-05
申请号：US12146804
申请日：2008-06-26
申请人： Katsuki Matsudera
发明人： Katsuki Matsudera
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/0005 , H03F1/56 , H03F3/45183 , H03F2200/222 , H03F2200/387 , H03F2203/45691
摘要： A semiconductor integrated circuit includes a control signal generating circuit which is configured to set, at least at a time of a first state, first and fifth control signals at a first voltage level, and second, third and fourth control signals at a second voltage level, and to set, at a time of a second state, the first to fourth control signals at the first voltage level, and the fifth control signal at an arbitrary voltage level.
摘要翻译：半导体集成电路包括：控制信号发生电路，其被配置为至少在第一状态时设定第一和第五控制信号处于第一电压电平;以及第二，第三和第四控制信号，其处于第二电压电平并且在第二状态时将第一电压电平的第一至第四控制信号和任意电压电平的第五控制信号置位。

9. 发明授权

US06801144B2 Semiconductor memory device inputting/outputting data synchronously with clock signal 有权
标题翻译：半导体存储器件与时钟信号同步输入/输出数据
公开(公告)号：US06801144B2
公开(公告)日：2004-10-05
申请号：US10678742
申请日：2003-10-02
申请人： Katsuki Matsudera , Masaru Koyanagi , Kazuhide Yoneya , Toshiki Hisada
发明人： Katsuki Matsudera , Masaru Koyanagi , Kazuhide Yoneya , Toshiki Hisada
IPC分类号： H03M900
CPC分类号： G11C7/1036
摘要： An input/output circuit inputs/outputs serial data. A register section comprises a first and a second register. The first register converts the serial data into parallel data. The second register converts parallel data into serial data. A first control signals supply a conversion timing for each bit when the serial data are converted into the parallel data. A second control signals supply a conversion timing for each bit when the parallel data are converted into the serial data. The signal generating circuit controls a timing of rise or fall of the first control signals and sets which of the memory cells should store a value for each bit, of the serial data, and controls a timing of rise or fall of the second control signals and sets which number of value of the serial data should be the value for each bit, of the parallel data read from the memory cells.
摘要翻译：输入/输出电路输入/输出串行数据。寄存器部分包括第一和第二寄存器。第一个寄存器将串行数据转换为并行数据。第二个寄存器将并行数据转换为串行数据。当串行数据被转换成并行数据时，第一控制信号为每个位提供转换定时。当并行数据被转换成串行数据时，第二控制信号为每个位提供转换定时。信号发生电路控制第一控制信号的上升或下降的定时，并设置哪个存储单元应存储串行数据的每个位的值，并且控制第二控制信号的上升或下降的定时，以及将串行数据的值的数量设置为从存储器单元读取的并行数据的每个位的值。

10. 发明授权

US06498741B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06498741B2
公开(公告)日：2002-12-24
申请号：US09746890
申请日：2000-12-21
申请人： Katsuki Matsudera , Kazuhide Yoneya , Toshiki Hisada , Masaru Koyanagi , Natsuki Kushiyama , Kaoru Nakagawa , Takahiko Hara
发明人： Katsuki Matsudera , Kazuhide Yoneya , Toshiki Hisada , Masaru Koyanagi , Natsuki Kushiyama , Kaoru Nakagawa , Takahiko Hara
IPC分类号： G11C506
CPC分类号： G11C5/063
摘要： A semiconductor memory device is provided which ensures the symmetry of memory data transmission time and a high-speed operation and has large write/read operation margin with no need of increasing the chip area. By placing a horizontally long peripheral circuit section in the middle in the vertical direction of a semiconductor chip, placing a vertically long shift register section above and below and perpendicularly to the peripheral circuit section, and making the memory core and shift register arrangement symmetrical in the horizontal direction, the data/signal lines between the memory core and the shift register section can be made short and the symmetry of the interconnections can be maintained, which allows the implementation of a high-speed and large-margin semiconductor memory device. In addition, a faster semiconductor memory can be obtained by forming the shift register section by stacking shift registers each corresponding to a data block and selecting the order in which the shift registers are stacked so that the length of interconnections between the peripheral circuit and the shift register is minimized.
摘要翻译：提供一种半导体存储器件，其确保存储器数据传输时间和高速操作的对称性，并且具有大的写入/读取操作裕度，而不需要增加芯片面积。通过在半导体芯片的垂直方向上的中间放置一个水平长的外围电路部分，将垂直长的移位寄存器部分设置在周边电路部分的上下方向并垂直于外围电路部分，并使存储器核心和移位寄存器装置在水平方向，可以使存储器芯和移位寄存器部分之间的数据/信号线短，并且可以保持互连的对称性，这允许实现高速和大面积的半导体存储器件。另外，通过将每个对应于数据块的移位寄存器堆叠并选择堆叠移位寄存器的顺序，使得外围电路与移位之间的互连长度可以获得更快的半导体存储器寄存器被最小化。

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