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1. 发明申请

US20040185675A1 MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) CELL PATTERNING 失效
标题翻译：磁阻随机访问存储器（MRAM）单元格格式
公开(公告)号：US20040185675A1
公开(公告)日：2004-09-23
申请号：US10677803
申请日：2003-10-02
申请人： Micron Technology, Inc.
发明人： Yong Lu , Theodore Zhu
IPC分类号： H01L021/31
CPC分类号： H01L27/222 , H01L43/12 , Y10S438/951
摘要： A process that advantageously forms MRAM cells without the application of ion beam milling processes. Unlike conventional processes that rely on ion beam milling processes to remove materials from a magnetoresistive sandwich from areas other than areas that will later form MRAM cell bodies, this process forms a layer of photoresist over areas other than those areas that correspond to MRAM cell bodies. The photoresist is lifted off after the deposition of a magnetoresistive sandwich that forms the MRAM cell bodies, thereby safely removing the magnetoresistive sandwich from undesired areas while maintaining the magnetoresistive sandwich in the areas corresponding to MRAM cell bodies.
摘要翻译：有利地形成MRAM电池而不施加离子束研磨工艺的方法。不同于依靠离子束研磨工艺从除了稍后形成MRAM单元体的区域之外的区域从磁阻三明治去除材料的常规工艺，该工艺在除了对应于MRAM单元体的那些区域之外的区域上形成光致抗蚀剂层。在形成MRAM单元体的磁阻三明治的沉积之后，光致抗蚀剂被剥离，从而从不期望的区域安全地去除磁阻三明治，同时在对应于MRAM单元体的区域中保持磁阻三明治。

2. 发明申请

US20040004878A1 Methods of increasing write selectivity in an MRAM 有权
公开(公告)号：US20040004878A1
公开(公告)日：2004-01-08
申请号：US10614709
申请日：2003-07-07
申请人： MICRON TECHNOLOGY, INC.
发明人： Shaoping Li , Theodore Zhu , Anthony S. Arrott , Harry Liu , William L. Larson , Yong Lu
IPC分类号： G11C007/00
CPC分类号： G11C11/16 , G11C11/15 , H01L27/222
摘要： MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.

3. 发明申请

US20030086321A1 Methods of increasing write selectivity in an MRAM 有权
标题翻译：增加MRAM中写入选择性的方法
公开(公告)号：US20030086321A1
公开(公告)日：2003-05-08
申请号：US10327581
申请日：2002-12-20
申请人： MICRON TECHNOLOGY, INC.
发明人： Shaoping Li , Theodore Zhu , Anthony S. Arrott , Harry Liu , William L. Larson , Yong Lu
IPC分类号： G11C007/00
CPC分类号： G11C11/16 , G11C11/15 , H01L27/222
摘要： MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.
摘要翻译：公开了在不显着降低存储器的封装密度的情况下产生增加的写入裕度和写入选择性的MRAM架构。磁阻位的主轴相对于数字线的轴线偏移，以从沿着磁阻位的长轴延伸的数字线电流产生磁场分量。

4. 发明申请

US20040082082A1 METHODS OF INCREASING WRITE SELECTIVITY IN AN MRAM 有权
标题翻译：在MRAM中增加写入选择性的方法
公开(公告)号：US20040082082A1
公开(公告)日：2004-04-29
申请号：US10614622
申请日：2003-07-07
申请人： MICRON TECHNOLOGY, INC.
发明人： Shaoping Li , Theodore Zhu , Anthony S. Arrott , Harry Liu , William L. Larson , Yong Lu
IPC分类号： H01L021/00
CPC分类号： G11C11/16 , G11C11/15 , H01L27/222
摘要： MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.
摘要翻译：公开了在不显着降低存储器的封装密度的情况下产生增加的写入裕度和写入选择性的MRAM架构。磁阻位的主轴相对于数字线的轴线偏移，以从沿着磁阻位的长轴延伸的数字线电流产生磁场分量。

5. 发明申请

US20040052105A1 BRIDGE-TYPE MAGNETIC RANDOM ACCESS MEMORY (MRAM) LATCH 有权
标题翻译： BRIDGE型磁性随机存取存储器（MRAM）LATCH
公开(公告)号：US20040052105A1
公开(公告)日：2004-03-18
申请号：US10246245
申请日：2002-09-17
申请人： Micron Technology, Inc.
发明人： David E. Fulkerson , Yong Lu
IPC分类号： G11C011/00
CPC分类号： G11C11/15
摘要： A technique to read a stored state in a magnetoresistive random access memory (MRAM) device, such as a giant magneto-resistance (GMR) MRAM device or a tunneling magneto-resistance (TMR) device uses a bit line in an MRAM device that is segmented into a first portion and a second portion. An interface circuit compares the resistance of a first portion and a second portion of a first bit line to the resistance of a first portion and a second portion of a second bit line to determine the logical state of a cell in the first bit line. The interface circuit includes a reset circuit that selectively couples the outputs of the interface circuit together. A subsequent decoupling of the outputs allows cross-coupling within the interface circuit to latch the outputs to a logical state corresponding to the stored magnetic state, thereby allowing the stored state of a cell to be read.
摘要翻译：在诸如巨磁电阻（MRM）MRAM装置或隧道磁阻（TMR）装置的磁阻随机存取存储器（MRAM）装置中读取存储状态的技术使用MRAM装置中的位线分割成第一部分和第二部分。接口电路将第一位线的第一部分和第二部分的电阻与第二位线的第一部分和第二部分的电阻进行比较，以确定第一位线中的单元的逻辑状态。接口电路包括将接口电路的输出选择性地耦合在一起的复位电路。输出的随后的去耦允许接口电路内的交叉耦合以将输出锁存到对应于存储的磁状态的逻辑状态，从而允许读取单元的存储状态。

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