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1. 发明申请

US20120105115A1 CLOCK AND DATA RECOVERY CIRCUIT 有权
标题翻译：时钟和数据恢复电路
公开(公告)号：US20120105115A1
公开(公告)日：2012-05-03
申请号：US13344201
申请日：2012-01-05
申请人： Michiyo YAMAMOTO , Kenji Murata , Kazuya Hatooka
发明人： Michiyo YAMAMOTO , Kenji Murata , Kazuya Hatooka
IPC分类号： H03L7/06
CPC分类号： H04L7/0337 , H03L7/091 , H03L7/0996
摘要： A clock and data recovery circuit includes a multiphase clock generator circuit which generates a multiphase clock having a plurality of clocks, a sampling circuit which samples a received data signal transferring serial data in synchronism with each of the plurality of clocks, and generates a plurality of data signals, a data recovery unit which generates a selection signal indicating a data signal having an appropriate phase among the plurality of data signals, and a storage unit which stores the selection signal. The data recovery unit selects one of the plurality of data signals, based on the selection signal read from the storage unit, and a clock corresponding to the selected data signal.
摘要翻译：时钟和数据恢复电路包括产生具有多个时钟的多相时钟的多相时钟发生器电路，采样电路，对与多个时钟中的每个时钟同步地传送串行数据的接收数据信号进行采样，并产生多个数据信号，数据恢复单元，其生成指示在多个数据信号中具有适当相位的数据信号的选择信号;以及存储单元，存储选择信号。数据恢复单元基于从存储单元读取的选择信号和对应于所选择的数据信号的时钟来选择多个数据信号中的一个。

2. 发明授权

US08582708B2 Clock and data recovery circuit 有权
标题翻译：时钟和数据恢复电路
公开(公告)号：US08582708B2
公开(公告)日：2013-11-12
申请号：US13344201
申请日：2012-01-05
申请人： Michiyo Yamamoto , Kenji Murata , Kazuya Hatooka
发明人： Michiyo Yamamoto , Kenji Murata , Kazuya Hatooka
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H03L7/091 , H03L7/0996
摘要： A clock and data recovery circuit includes a multiphase clock generator circuit which generates a multiphase clock having a plurality of clocks, a sampling circuit which samples a received data signal transferring serial data in synchronism with each of the plurality of clocks, and generates a plurality of data signals, a data recovery unit which generates a selection signal indicating a data signal having an appropriate phase among the plurality of data signals, and a storage unit which stores the selection signal. The data recovery unit selects one of the plurality of data signals, based on the selection signal read from the storage unit, and a clock corresponding to the selected data signal.
摘要翻译：时钟和数据恢复电路包括产生具有多个时钟的多相时钟的多相时钟发生器电路，采样电路，对与多个时钟中的每个时钟同步地传送串行数据的接收数据信号进行采样，并产生多个数据信号，数据恢复单元，其生成指示在多个数据信号中具有适当相位的数据信号的选择信号;以及存储单元，存储选择信号。数据恢复单元基于从存储单元读取的选择信号和对应于所选择的数据信号的时钟来选择多个数据信号中的一个。

3. 发明申请

US20100013692A1 A/D CONVERTER 有权
标题翻译： A / D转换器
公开(公告)号：US20100013692A1
公开(公告)日：2010-01-21
申请号：US12377989
申请日：2007-08-10
申请人： Michiyo Yamamoto , Kenji Murata , Masakazu Shigemori
发明人： Michiyo Yamamoto , Kenji Murata , Masakazu Shigemori
IPC分类号： H03M1/34
CPC分类号： H03M1/1245 , H03M1/365
摘要： An external input operation clock signal is required for operating a conventional A/D converter, and the performance of the A/D converter is undesirably determined by the characteristics of the external input operation clock.A clock generator circuit (104) for automatically generating an operation clock is provided inside an A/D converter (100) to make the A/D converter require no external input operation clock. Further, a circuit for detecting the operation times of the constituents of the A/D converter is provided to generate a clock with which the A/D converter is optimally operated, thereby realizing high-speed operation and low power consumption.
摘要翻译：操作常规A / D转换器需要外部输入操作时钟信号，并且A / D转换器的性能不合需要地由外部输入操作时钟的特性决定。在A / D转换器（100）内部设置用于自动生成操作时钟的时钟发生器电路（104），使得A / D转换器不需要外部输入操作时钟。此外，提供用于检测A / D转换器的组成部分的操作时间的电路，以产生A / D转换器被最佳操作的时钟，从而实现高速操作和低功耗。

4. 发明申请

US20100214031A1 SPECTRUM SPREAD CLOCK GENERATION DEVICE 有权
标题翻译：频谱扩展时钟发生装置
公开(公告)号：US20100214031A1
公开(公告)日：2010-08-26
申请号：US12678630
申请日：2008-10-28
申请人： Michiyo Yamamoto , Tsuyoshi Ebuchi , Kenji Murata
发明人： Michiyo Yamamoto , Tsuyoshi Ebuchi , Kenji Murata
IPC分类号： H03L7/06 , H03J7/04 , H03L7/00
CPC分类号： H03L7/183 , H03B5/1206 , H03B5/1228 , H03B5/1243 , H03B5/1265 , H03B2200/005 , H03L7/087 , H03L7/0898 , H03L7/093 , H03L7/099 , H03L7/0995 , H03L7/107 , H03L2207/06
摘要： A spread spectrum controller (20) controls a PLL (10) so that the PLL outputs a spread-spectrum processed clock signal. A loop bandwidth controller (30) controls at least one of a phase detector (11), a loop filter (12), a voltage-controlled oscillator (13), and a frequency divider (14) in the PLL (10) during operation of the spread spectrum controller (20) to change a loop bandwidth of the PLL (10).
摘要翻译：扩频控制器（20）控制PLL（10），使得PLL输出扩频处理的时钟信号。环路带宽控制器（30）在操作期间控制PLL（10）中的相位检测器（11），环路滤波器（12），压控振荡器（13）和分频器（14）中的至少一个扩展频谱控制器（20）改变PLL（10）的环路带宽。

5. 发明授权

US08085101B2 Spread spectrum clock generation device 有权
标题翻译：扩频时钟生成装置
公开(公告)号：US08085101B2
公开(公告)日：2011-12-27
申请号：US12678630
申请日：2008-10-28
申请人： Michiyo Yamamoto , Tsuyoshi Ebuchi , Kenji Murata
发明人： Michiyo Yamamoto , Tsuyoshi Ebuchi , Kenji Murata
IPC分类号： H03B29/00
CPC分类号： H03L7/183 , H03B5/1206 , H03B5/1228 , H03B5/1243 , H03B5/1265 , H03B2200/005 , H03L7/087 , H03L7/0898 , H03L7/093 , H03L7/099 , H03L7/0995 , H03L7/107 , H03L2207/06
摘要： A spread spectrum controller (20) controls a PLL (10) so that the PLL outputs a spread-spectrum processed clock signal. A loop bandwidth controller (30) controls at least one of a phase detector (11), a loop filter (12), a voltage-controlled oscillator (13), and a frequency divider (14) in the PLL (10) during operation of the spread spectrum controller (20) to change a loop bandwidth of the PLL (10).
摘要翻译：扩频控制器（20）控制PLL（10），使得PLL输出扩频处理的时钟信号。环路带宽控制器（30）在操作期间控制PLL（10）中的相位检测器（11），环路滤波器（12），压控振荡器（13）和分频器（14）中的至少一个扩展频谱控制器（20）改变PLL（10）的环路带宽。

6. 发明授权

US07986256B2 A/D converter 有权
标题翻译： A / D转换器
公开(公告)号：US07986256B2
公开(公告)日：2011-07-26
申请号：US12377989
申请日：2007-08-10
申请人： Michiyo Yamamoto , Kenji Murata , Masakazu Shigemori
发明人： Michiyo Yamamoto , Kenji Murata , Masakazu Shigemori
IPC分类号： H03M1/12
CPC分类号： H03M1/1245 , H03M1/365
摘要： An external input operation clock signal is required for operating a conventional A/D converter, and the performance of the A/D converter is undesirably determined by the characteristics of the external input operation clock. A clock generator circuit for automatically generating an operation clock is provided inside an A/D converter to make the A/D converter require no external input operation clock. Further, a circuit for detecting the operation times of the constituents of the A/D converter is provided to generate a clock with which the A/D converter is optimally operated, thereby realizing high-speed operation and low power consumption.
摘要翻译：操作常规A / D转换器需要外部输入操作时钟信号，并且A / D转换器的性能不合需要地由外部输入操作时钟的特性决定。在A / D转换器内部设置用于自动生成工作时钟的时钟发生器电路，使A / D转换器不需要外部输入操作时钟。此外，提供用于检测A / D转换器的组成部分的操作时间的电路，以产生A / D转换器被最佳操作的时钟，从而实现高速操作和低功耗。

7. 外观设计

USD599785S1 Earphone 有权
公开(公告)号：USD599785S1
公开(公告)日：2009-09-08
申请号：US29296666
申请日：2007-10-25
申请人： Takeshi Matsuda , Kenji Hatano , Masaji Komuro , Kenji Murata
设计人： Takeshi Matsuda , Kenji Hatano , Masaji Komuro , Kenji Murata

8. 发明授权

US06917856B2 Robot 有权
标题翻译：机器人
公开(公告)号：US06917856B2
公开(公告)日：2005-07-12
申请号：US10343913
申请日：2002-04-12
申请人： Kenji Murata
发明人： Kenji Murata
IPC分类号： B25J9/16 , B25J9/18 , B25J19/00 , G05B19/04 , G05B19/18
CPC分类号： B25J9/1674 , G05B2219/40218
摘要： It is constructed so as to detect a joint movement position of a robot arm by a position detector and a joint movement speed is calculated from change amounts of the joint movement position and elapsed time and is compared with an allowable movement speed and unlocking and locking of a brake are controlled so that the joint movement speed of an arm at the time of brake unlocking becomes within a constant value even when a shape, an attitude and a load condition of the robot arm vary. Therefore, movement work of the arm by the brake unlocking can be performed alone and a robot with high safety can be obtained.
摘要翻译：其结构是通过位置检测器检测机器人手臂的关节运动位置，并且根据关节运动位置和经过时间的变化量计算关节运动速度，并将其与允许的运动速度进行比较并解锁和锁定控制制动器，使得即使当机器人手臂的形状，姿态和负载条件变化时，制动器解锁时的臂的关节移动速度也变为恒定值。因此，可以单独执行通过制动器解锁的臂的移动工作，并且可以获得具有高安全性的机器人。

9. 发明授权

US06771784B2 Sub woofer system 失效
标题翻译：次低音扬声器系统
公开(公告)号：US06771784B2
公开(公告)日：2004-08-03
申请号：US09926319
申请日：2002-01-09
申请人： Kenji Murata
发明人： Kenji Murata
IPC分类号： H03G500
CPC分类号： H04R1/26 , H04R3/04 , H04R3/14
摘要： A sub woofer system is constituted of a real time digital signal processing part 5 that includes an A/D converter 5a, a low pass filter block 5b, a delay block 5c, and a D/A converter block 5d, an analog power amplifier 6 and a speaker 7. The length of delay time of the delay block 5c is set so that the length of group delay time of the digital signal processing part 5 may equal an integral multiple of the length of time corresponding to one wavelength of the crossover point frequency between the digital signal processing part 5 and a main speaker 4. The signal processing is performed under the conditions that have been set as such. In this case, a construction is made up wherein the length of a group delay time produced in the digital type real time digital signal processing part can be set to a given value. By this construction, it is possible to provide a sub woofer system which can improve the phase interference between the main speaker and the sub woofer system at the crossover point between the two.
摘要翻译：低音扬声器系统由包括A / D转换器5a，低通滤波器块5b，延迟块5c和D / A转换器块5d的实时数字信号处理部分5构成，模拟功率放大器6 和扬声器7.延迟块5c的延迟时间的长度被设置为使得数字信号处理部分5的组延迟时间的长度可以等于与交叉点的一个波长相对应的时间长度的整数倍在数字信号处理部分5和主扬声器4之间的频率。信号处理在已被设置为这样的条件下执行。在这种情况下，构成了数字型实时数字信号处理部中产生的群延迟时间的长度可以设定为给定值的结构。通过这种结构，可以提供一种可以在两者之间的交叉点改善主扬声器和次低音扬声器系统之间的相位干扰的次低音扬声器系统。

10. 发明授权

US06667075B2 Method for imparting hydrophilicity to substrate 失效
公开(公告)号：US06667075B2
公开(公告)日：2003-12-23
申请号：US10110642
申请日：2002-04-12
申请人： Toshiaki Kitazoe , Keisuke Tanaka , Kenji Murata
发明人： Toshiaki Kitazoe , Keisuke Tanaka , Kenji Murata
IPC分类号： B05D310
CPC分类号： G02B1/18 , C03C17/245 , C03C17/3417 , C03C2217/213 , C03C2218/151 , C03C2218/152 , C03C2218/32 , C23C14/10 , C23C14/5853 , C23C16/0272 , C23C16/402 , C23C16/56 , G02B1/10
摘要： The present invention relates to a method for imparting hydrophilicity to a substrate whereby high hydrophilic properties and water-holding properties can be maintained for a long period of time. According to the present invention, an SiO2 film is formed directly or through an undercoat layer on a substrate under a reduced pressure of 100 Pa or less and immediately after the SiO2 film is formed, the SiO2 film is treated with water. Before forming the SiO2 film, it is also desirable that an undercoat layer consisting of a TiO2 film, Al2O3 film, Nb2O5 film, a laminated film prepared by laminating the TiO2 film on the Al2O3 film, a laminated film prepared by laminating the TiO2 film on the Nb2O5 film, or a low emissivity film be formed on a substrate and the SiO2 film be then formed on the undercoat film to serve as an SiO2 composite film.

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