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1. 发明授权

US08782239B2 Distributed router computing at network nodes 失效
标题翻译：分布式路由器计算在网络节点
公开(公告)号：US08782239B2
公开(公告)日：2014-07-15
申请号：US13028282
申请日：2011-02-16
申请人： Michitaka Okuno , Takeki Yazaki , Yuji Tsushima , Hidetaka Aoki
发明人： Michitaka Okuno , Takeki Yazaki , Yuji Tsushima , Hidetaka Aoki
IPC分类号： G06F15/177 , G06F15/173
CPC分类号： H04L45/54 , G06F9/505 , H04L41/083 , H04L41/0833 , H04L45/02 , H04L45/38 , H04L67/34 , H04L69/22 , Y02D10/22
摘要： A system permitting alteration of the information processing position, where an existing information system is used, while minimizing alterations in configuration or the like, is to be provided. Intelligent nodes each having an information processing section and any desired address altering section are arranged on boundaries of a network where packets are likely to pass. This node has a flow table for recognizing as a flow a group of packets transmitted from each user's terminal, a flow status table for determining the connection state and the next destination address or the final destination address of each flow, and a module to observe the loaded state of its own information processing function. It rewrites the destination address of any flow not in a connection-established state in the flow status table to a less loaded one out of its own information processing function section or external information processing apparatus.
摘要翻译：提供一种允许改变信息处理位置的系统，其中使用现有的信息系统，同时最小化配置等的改变。每个具有信息处理部分和任何期望的地址改变部分的智能节点被布置在分组可能通过的网络的边界上。该节点具有流表，用于将从每个用户终端发送的一组分组识别为流，用于确定连接状态的流状态表和下一目的地地址或每个流的最终目的地地址，以及观察该加载状态自己的信息处理功能。它将流状态表中不处于连接建立状态的任何流的目的地地址重写为其自己的信息处理功能部分或外部信息处理装置中较少加载的目的地址。

2. 发明申请

US20110202658A1 INFORMATION SYSTEM, APPARATUS AND METHOD 失效
标题翻译：信息系统，装置和方法
公开(公告)号：US20110202658A1
公开(公告)日：2011-08-18
申请号：US13028282
申请日：2011-02-16
申请人： Michitaka OKUNO , Takeki Yazaki , Yuji Tsushima , Hidetaka Aoki
发明人： Michitaka OKUNO , Takeki Yazaki , Yuji Tsushima , Hidetaka Aoki
IPC分类号： G06F15/173 , G06F15/16
CPC分类号： H04L45/54 , G06F9/505 , H04L41/083 , H04L41/0833 , H04L45/02 , H04L45/38 , H04L67/34 , H04L69/22 , Y02D10/22
摘要： A system permitting alteration of the information processing position, where an existing information system is used, while minimizing alterations in configuration or the like, is to be provided. Intelligent nodes each having an information processing section and any desired address altering section are arranged on boundaries of a network where packets are likely to pass. This node has a flow table for recognizing as a flow a group of packets transmitted from each user's terminal, a flow status table for determining the connection state and the next destination address or the final destination address of each flow, and a module to observe the loaded state of its own information processing function. It rewrites the destination address of any flow not in a connection-established state in the flow status table to a less loaded one out of its own information processing function section or external information processing apparatus.
摘要翻译：提供一种允许改变信息处理位置的系统，其中使用现有的信息系统，同时最小化配置等的改变。每个具有信息处理部分和任何期望的地址改变部分的智能节点被布置在分组可能通过的网络的边界上。该节点具有流表，用于将从每个用户终端发送的一组分组识别为流，用于确定连接状态的流状态表和下一目的地地址或每个流的最终目的地地址，以及观察该加载状态自己的信息处理功能。它将流状态表中不处于连接建立状态的任何流的目的地地址重写为其自己的信息处理功能部分或外部信息处理装置中较少加载的目的地址。

3. 发明授权

US08798051B2 Information and communication processing system, method, and network node 有权
标题翻译：信息通信处理系统，方法和网络节点
公开(公告)号：US08798051B2
公开(公告)日：2014-08-05
申请号：US13579443
申请日：2010-02-18
申请人： Michitaka Okuno , Shinji Nishimura , Hidetaka Aoki , Yuji Tsushima , Takeki Yazaki , Yuji Ogata
发明人： Michitaka Okuno , Shinji Nishimura , Hidetaka Aoki , Yuji Tsushima , Takeki Yazaki , Yuji Ogata
IPC分类号： H04L12/28 , H04L12/26
CPC分类号： G06F9/546 , H04L67/10 , H04L67/2828
摘要： In a distributed information communication processing system in which a plurality of information communication devices provides a service through a network, response speed, electric power consumption, and further reliability are improved. The distributed information communication processing system which provides various services is configured by associating an entrance node (EN) which executes filtering near sensors, actuators, and terminals being information sources, an intelligent node (IN) which changes an information processing position and executes information processing and communication processing instead of a data center (DC), and a management node (MN) which manages these nodes. Thereby, real time type information processing can be realized.
摘要翻译：在多个信息通信设备通过网络提供服务的分布式信息通信处理系统中，提高了响应速度，电力消耗和进一步的可靠性。提供各种服务的分布式信息通信处理系统通过将在传感器附近执行滤波的入口节点（EN），作为信息源的终端，致动器和终端相关联，将信息处理位置改变并执行信息处理的智能节点和通信处理而不是数据中心（DC），以及管理这些节点的管理节点（MN）。由此，能够实现实时型信息处理。

4. 发明申请

US20120314608A1 INFORMATION AND COMMUNICATION PROCESSING SYSTEM, METHOD, AND NETWORK NODE 有权
标题翻译：信息与通信处理系统，方法和网络节点
公开(公告)号：US20120314608A1
公开(公告)日：2012-12-13
申请号：US13579443
申请日：2010-02-18
申请人： Michitaka Okuno , Shinji Nishimura , Hidetaka Aoki , Yuji Tsushima , Takeki Yazaki , Yuji Ogata
发明人： Michitaka Okuno , Shinji Nishimura , Hidetaka Aoki , Yuji Tsushima , Takeki Yazaki , Yuji Ogata
IPC分类号： H04L12/26
CPC分类号： G06F9/546 , H04L67/10 , H04L67/2828
摘要： In a distributed information communication processing system in which a plurality of information communication devices provides a service through a network, response speed, electric power consumption, and further reliability are improved. The distributed information communication processing system which provides various services is configured by associating an entrance node (EN) which executes filtering near sensors, actuators, and terminals being information sources, an intelligent node (IN) which changes an information processing position and executes information processing and communication processing instead of a data center (DC), and a management node (MN) which manages these nodes. Thereby, real time type information processing can be realized.
摘要翻译：在多个信息通信装置通过网络提供服务的分布式信息通信处理系统中，提高了响应速度，电力消耗和进一步的可靠性。提供各种服务的分布式信息通信处理系统通过将在传感器附近执行滤波的入口节点（EN），作为信息源的终端，致动器和终端相关联，将信息处理位置改变并执行信息处理的智能节点和通信处理而不是数据中心（DC），以及管理这些节点的管理节点（MN）。由此，能够实现实时型信息处理。

5. 发明授权

US07908604B2 Synchronization method and program for a parallel computer 失效
标题翻译：并行计算机的同步方法和程序
公开(公告)号：US07908604B2
公开(公告)日：2011-03-15
申请号：US11312345
申请日：2005-12-21
申请人： Koichi Takayama , Hidetaka Aoki
发明人： Koichi Takayama , Hidetaka Aoki
IPC分类号： G06F9/46
CPC分类号： G06F9/52 , G06F9/522
摘要： Barrier synchronization between multiprocessors is performed at high speed while reducing overhead of parallel processing without adding any special hardware mechanism. A parallel computer synchronization method is provided to synchronize threads through barrier synchronization for parallel execution of plural threads on plural processor modules. The parallel computer has plural processor modules (P0 and P1) equipped with plural processor cores (cpu0 to cpu3). The processor cores are each assigned plural threads (Th0 to Th7) to execute multithread processing. The plural threads (Th0 to Th7) are set in hierarchical groups (Gr), and barrier synchronization is performed on each group separately.
摘要翻译：多处理器之间的屏障同步以高速执行，同时减少并行处理的开销，而不增加任何特殊的硬件机制。提供了一种并行计算机同步方法，以通过屏障同步来同步线程，以并行执行多个处理器模块上的多个线程。并行计算机具有配备有多个处理器核（cpu0〜cpu3）的多个处理器模块（P0和P1）。每个处理器核心被分配多个线程（Th0到Th7）来执行多线程处理。多个线程（Th0至Th7）被设置为分层组（Gr），并且对每个组分别执行屏障同步。

6. 发明申请

US20070180198A1 Processor for multiprocessing computer systems and a computer system 审中-公开
标题翻译：用于多处理计算机系统和计算机系统的处理器
公开(公告)号：US20070180198A1
公开(公告)日：2007-08-02
申请号：US11358052
申请日：2006-02-22
申请人： Hidetaka Aoki , Naonobu Sukegawa
发明人： Hidetaka Aoki , Naonobu Sukegawa
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0862 , G06F2212/6028
摘要： When the same data is used in a multiprocessor system, cache misses are reduced to prevent a coherence request from frequently occurring between processors. Provided is a processor including: an interface for performing communication with a main memory or one of the another processor through a system control unit; a cache memory for storing data of the main memory; and a reading processing unit for reading data at an address contained in a reading instruction from the main memory to store the read data in the cache memory, in which the reading processing unit includes: a first load instruction executing unit for reading data corresponding to an address designated by a first load instruction from the main memory and the one of the another processor to store the data into the cache memory; and a second load instruction executing unit for reading data corresponding to an address designated by a second load instruction from the main memory or the one of the another processor to store the data into the cache memory and requesting the system control unit to transmit the data to the another processor
摘要翻译：当在多处理器系统中使用相同的数据时，减少高速缓存未命中，以防止在处理器之间频繁发生相干请求。提供了一种处理器，包括：用于通过系统控制单元执行与主存储器或另一处理器之一的通信的接口; 用于存储主存储器的数据的高速缓冲存储器; 以及读取处理单元，用于从包含在来自主存储器的读取指令中的地址读取数据，以将读取的数据存储在高速缓冲存储器中，读取处理单元包括：第一加载指令执行单元，用于读取对应于由来自主存储器的第一加载指令指定的地址和另一个处理器之一，将数据存储到高速缓冲存储器中; 以及第二加载指令执行单元，用于从主存储器或另一处理器中的一个处理器读取与由第二加载指令指定的地址相对应的数据，以将数据存储到高速缓冲存储器中，并请求系统控制单元将数据发送到另一个处理器

7. 发明申请

US20070124567A1 Processor system 审中-公开
标题翻译：处理器系统
公开(公告)号：US20070124567A1
公开(公告)日：2007-05-31
申请号：US11357972
申请日：2006-02-22
申请人： Aki Tomita , Hidetaka Aoki , Naonobu Sukegawa
发明人： Aki Tomita , Hidetaka Aoki , Naonobu Sukegawa
IPC分类号： G06F15/00
CPC分类号： G06F15/167
摘要： A processor system capable of improving usability and performance of an on-chip heterogeneous multiprocessor is provided. The processor system has a processor and a memory, the processor including one control unit that reads a program, a plurality of arithmetic units that transmit a SIMD instruction of the program read by the control unit, and a shared cache capable of storing the program read by the control unit from the memory and allowing the control unit and the plurality of arithmetic units to read and write data. An instruction transmitted from the control unit to the plurality of arithmetic units specifies, in a process where the plurality of arithmetic units execute instructions, whether, until receiving an external signal from an arithmetic unit different from the arithmetic unit that is executing the instruction, execution of the instruction is to be suspended.
摘要翻译：提供了一种能够提高片上异构多处理器的可用性和性能的处理器系统。处理器系统具有处理器和存储器，处理器包括读取程序的一个控制单元，发送由控制单元读取的程序的SIMD指令的多个运算单元，以及能够存储程序读取的共享高速缓存并且允许控制单元和多个运算单元读取和写入数据。从所述控制单元发送到所述多个算术单元的指令，在所述多个算术单元执行指令的处理中，在从与所述指令执行的运算单元不同的运算单元接收到外部信号之前，的指示将被暂停。

8. 发明申请

US20090016332A1 Parallel computer system 审中-公开
标题翻译：并行计算机系统
公开(公告)号：US20090016332A1
公开(公告)日：2009-01-15
申请号：US12010687
申请日：2008-01-29
申请人： Hidetaka Aoki , Yoshiko Nagasaka
发明人： Hidetaka Aoki , Yoshiko Nagasaka
IPC分类号： H04L12/50
CPC分类号： G06F15/173 , H04L49/1515
摘要： To exchange data between adjacent nodes at high speed while using an existing network including a fat tree and a multistage crossbar switch. This invention provides a parallel computer system including: a plurality of nodes each of which includes a processor and a communication unit; a switch for connecting the plurality of nodes with each other; a first network for connecting each of the plurality of nodes and the switch; and a second network for partially connecting the plurality of nodes with each other. Further, the first network is comprised of one of a fat tree and a multistage crossbar network. Further, the second network partially connects predetermined nodes among the plurality of nodes directly with each other.
摘要翻译：在使用包括胖树和多级交叉开关的现有网络的同时高速交换相邻节点之间的数据。本发明提供了一种并行计算机系统，包括：多个节点，每个节点包括处理器和通信单元; 用于将所述多个节点彼此连接的开关; 用于连接所述多个节点和所述交换机中的每一个的第一网络; 以及用于将所述多个节点彼此部分地连接的第二网络。此外，第一网络由胖树和多级交叉网络之一组成。此外，第二网络将多个节点中的预定节点直接彼此部分地连接。

9. 发明授权

US06792498B2 Memory system with mechanism for assisting a cache memory 失效
标题翻译：具有辅助缓存存储器的机制的存储器系统
公开(公告)号：US06792498B2
公开(公告)日：2004-09-14
申请号：US09923339
申请日：2001-08-08
申请人： Tomohiro Nakamura , Hidetaka Aoki
发明人： Tomohiro Nakamura , Hidetaka Aoki
IPC分类号： G06F1200
CPC分类号： G06F12/0897
摘要： Disclosed is a memory system which comprises a first cache memory of a high rank close to a processor; a second cache memory or a main memory device of a lower rank; a first table for storing a line address when there is no line data in the first cache memory at a time of making a transfer request for the line data and the transfer request for the line data is made to the second cache memory or the main memory device; and means for comparing a line address registered in the first table with a line address of a transfer destination every time the transfer request is made. When a result of comparison of the line address in the first table is a miss-hit, the line address of the transfer destination is registered in the first table and it is indicated whether the result of comparison of the line address in the first table is a hit or miss-hit.
摘要翻译：公开了一种存储系统，其包括靠近处理器的高级别的第一高速缓存存储器; 第二高速缓冲存储器或较低等级的主存储器件; 在对行数据进行转移请求时对第一高速缓存存储器中没有行数据的行地址进行存储的线路数据的第一表和对第二高速缓冲存储器或主存储器设备; 以及用于在每次进行转移请求时将在第一表中注册的行地址与转移目的地的行地址进行比较的装置。当第一表中的行地址的比较结果是未命中时，将转移目的地的行地址登记在第一表中，并且指示第一表中的行地址的比较结果是否是命中或未命中。

10. 发明申请

US20090106499A1 Processor with prefetch function 审中-公开
标题翻译：具有预取功能的处理器
公开(公告)号：US20090106499A1
公开(公告)日：2009-04-23
申请号：US12071022
申请日：2008-02-14
申请人： Hidetaka Aoki , Naonobu Sukegawa
发明人： Hidetaka Aoki , Naonobu Sukegawa
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F9/383 , G06F12/126 , G06F2212/1016
摘要： Non-speculatively prefetched data is prevented from being discarded from a cache memory before being accessed. In a cache memory including a cache control unit for reading data from a main memory into the cache memory and registering the data in the cache memory upon reception of a fill request from a processor and for accessing the data in the cache memory upon reception of a memory instruction from the processor, a cache line of the cache memory includes a registration information storage unit for storing information indicating whether the registered data is written into the cache line in response to the fill request and whether the registered data is accessed by the memory instruction. The cache control unit sets information in the registration information storage unit for performing a prefetch based on the fill request and resets the information for accessing the cache line based on the memory instruction.
摘要翻译：非推测性预取数据被阻止在被访问之前被从高速缓冲存储器中丢弃。一种高速缓冲存储器，包括：高速缓存控制单元，用于从主存储器读取数据到高速缓冲存储器中，并且在接收到来自处理器的填充请求时将数据登记在高速缓冲存储器中，并且在接收到高速缓冲存储器时访问数据来自处理器的存储器指令，高速缓冲存储器的高速缓存行包括注册信息存储单元，用于存储指示是否将注册数据写入高速缓存行中的信息，以及是否通过存储器指令访问注册数据。高速缓存控制单元在注册信息存储单元中设置用于基于填充请求执行预取的信息，并且基于存储器指令重新设置用于访问高速缓存行的信息。

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