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1. 发明申请

US20070124567A1 Processor system 审中-公开
标题翻译：处理器系统
公开(公告)号：US20070124567A1
公开(公告)日：2007-05-31
申请号：US11357972
申请日：2006-02-22
申请人： Aki Tomita , Hidetaka Aoki , Naonobu Sukegawa
发明人： Aki Tomita , Hidetaka Aoki , Naonobu Sukegawa
IPC分类号： G06F15/00
CPC分类号： G06F15/167
摘要： A processor system capable of improving usability and performance of an on-chip heterogeneous multiprocessor is provided. The processor system has a processor and a memory, the processor including one control unit that reads a program, a plurality of arithmetic units that transmit a SIMD instruction of the program read by the control unit, and a shared cache capable of storing the program read by the control unit from the memory and allowing the control unit and the plurality of arithmetic units to read and write data. An instruction transmitted from the control unit to the plurality of arithmetic units specifies, in a process where the plurality of arithmetic units execute instructions, whether, until receiving an external signal from an arithmetic unit different from the arithmetic unit that is executing the instruction, execution of the instruction is to be suspended.
摘要翻译：提供了一种能够提高片上异构多处理器的可用性和性能的处理器系统。处理器系统具有处理器和存储器，处理器包括读取程序的一个控制单元，发送由控制单元读取的程序的SIMD指令的多个运算单元，以及能够存储程序读取的共享高速缓存并且允许控制单元和多个运算单元读取和写入数据。从所述控制单元发送到所述多个算术单元的指令，在所述多个算术单元执行指令的处理中，在从与所述指令执行的运算单元不同的运算单元接收到外部信号之前，的指示将被暂停。

2. 发明申请

US20080059715A1 Computer system and control method for controlling processor 有权
标题翻译：用于控制处理器的计算机系统和控制方法
公开(公告)号：US20080059715A1
公开(公告)日：2008-03-06
申请号：US11705410
申请日：2007-02-13
申请人： Aki Tomita , Naonobu Sukegawa
发明人： Aki Tomita , Naonobu Sukegawa
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A processor reads a program including a prefetch command and a load command and data from a main memory, and executes the program. The processor includes: a processor core that executes the program; a L2 cache that stores data on the main memory for each predetermined unit of data storage; and a prefetch unit that pre-reads the data into the L2 cache from the main memory on the basis of a request for prefetch from the processor core. The prefetch unit includes: a L2 cache management table including an area in which a storage state is held for each position in the unit of data storage of the L2 cache and an area in which a request for prefetch is reserved; and a prefetch control unit that instructs, the L2 cache to perform the request for prefetch reserved or the request for prefetch from the processor core.
摘要翻译：处理器从主存储器读取包括预取命令和加载命令以及数据的程序，并执行该程序。处理器包括：执行程序的处理器核心; L2缓存，用于在每个预定的数据存储单元上存储主存储器上的数据; 以及预取单元，其基于来自处理器核的预取请求，从主存储器预读取数据到L2高速缓存中。预取单元包括：L2高速缓存管理表，其包括以L2缓存的数据存储为单位的每个位置保持存储状态的区域以及保留预取请求的区域; 以及预取控制单元，其指示L2高速缓存从所述处理器核心执行预取请求或预取请求。

3. 发明授权

US07895399B2 Computer system and control method for controlling processor execution of a prefetech command 有权
标题翻译：用于控制预取命令的处理器执行的计算机系统和控制方法
公开(公告)号：US07895399B2
公开(公告)日：2011-02-22
申请号：US11705410
申请日：2007-02-13
申请人： Aki Tomita , Naonobu Sukegawa
发明人： Aki Tomita , Naonobu Sukegawa
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A processor reads a program including a prefetch command and a load command and data from a main memory, and executes the program. The processor includes: a processor core that executes the program; a L2 cache that stores data on the main memory for each predetermined unit of data storage; and a prefetch unit that pre-reads the data into the L2 cache from the main memory on the basis of a request for prefetch from the processor core. The prefetch unit includes: a L2 cache management table including an area in which a storage state is held for each position in the unit of data storage of the L2 cache and an area in which a request for prefetch is reserved; and a prefetch control unit that instructs, the L2 cache to perform the request for prefetch reserved or the request for prefetch from the processor core.
摘要翻译：处理器从主存储器读取包括预取命令和加载命令以及数据的程序，并执行该程序。处理器包括：执行程序的处理器核心; L2缓存，用于在每个预定的数据存储单元上存储主存储器上的数据; 以及预取单元，其基于来自处理器核的预取请求，从主存储器预读取数据到L2高速缓存中。预取单元包括：L2高速缓存管理表，其包括以L2缓存的数据存储为单位的每个位置保持存储状态的区域以及保留预取请求的区域; 以及预取控制单元，其指示L2高速缓存从所述处理器核心执行预取请求或预取请求。

4. 发明申请

US20090106499A1 Processor with prefetch function 审中-公开
标题翻译：具有预取功能的处理器
公开(公告)号：US20090106499A1
公开(公告)日：2009-04-23
申请号：US12071022
申请日：2008-02-14
申请人： Hidetaka Aoki , Naonobu Sukegawa
发明人： Hidetaka Aoki , Naonobu Sukegawa
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F9/383 , G06F12/126 , G06F2212/1016
摘要： Non-speculatively prefetched data is prevented from being discarded from a cache memory before being accessed. In a cache memory including a cache control unit for reading data from a main memory into the cache memory and registering the data in the cache memory upon reception of a fill request from a processor and for accessing the data in the cache memory upon reception of a memory instruction from the processor, a cache line of the cache memory includes a registration information storage unit for storing information indicating whether the registered data is written into the cache line in response to the fill request and whether the registered data is accessed by the memory instruction. The cache control unit sets information in the registration information storage unit for performing a prefetch based on the fill request and resets the information for accessing the cache line based on the memory instruction.
摘要翻译：非推测性预取数据被阻止在被访问之前被从高速缓冲存储器中丢弃。一种高速缓冲存储器，包括：高速缓存控制单元，用于从主存储器读取数据到高速缓冲存储器中，并且在接收到来自处理器的填充请求时将数据登记在高速缓冲存储器中，并且在接收到高速缓冲存储器时访问数据来自处理器的存储器指令，高速缓冲存储器的高速缓存行包括注册信息存储单元，用于存储指示是否将注册数据写入高速缓存行中的信息，以及是否通过存储器指令访问注册数据。高速缓存控制单元在注册信息存储单元中设置用于基于填充请求执行预取的信息，并且基于存储器指令重新设置用于访问高速缓存行的信息。

5. 发明申请

US20070180198A1 Processor for multiprocessing computer systems and a computer system 审中-公开
标题翻译：用于多处理计算机系统和计算机系统的处理器
公开(公告)号：US20070180198A1
公开(公告)日：2007-08-02
申请号：US11358052
申请日：2006-02-22
申请人： Hidetaka Aoki , Naonobu Sukegawa
发明人： Hidetaka Aoki , Naonobu Sukegawa
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0862 , G06F2212/6028
摘要： When the same data is used in a multiprocessor system, cache misses are reduced to prevent a coherence request from frequently occurring between processors. Provided is a processor including: an interface for performing communication with a main memory or one of the another processor through a system control unit; a cache memory for storing data of the main memory; and a reading processing unit for reading data at an address contained in a reading instruction from the main memory to store the read data in the cache memory, in which the reading processing unit includes: a first load instruction executing unit for reading data corresponding to an address designated by a first load instruction from the main memory and the one of the another processor to store the data into the cache memory; and a second load instruction executing unit for reading data corresponding to an address designated by a second load instruction from the main memory or the one of the another processor to store the data into the cache memory and requesting the system control unit to transmit the data to the another processor
摘要翻译：当在多处理器系统中使用相同的数据时，减少高速缓存未命中，以防止在处理器之间频繁发生相干请求。提供了一种处理器，包括：用于通过系统控制单元执行与主存储器或另一处理器之一的通信的接口; 用于存储主存储器的数据的高速缓冲存储器; 以及读取处理单元，用于从包含在来自主存储器的读取指令中的地址读取数据，以将读取的数据存储在高速缓冲存储器中，读取处理单元包括：第一加载指令执行单元，用于读取对应于由来自主存储器的第一加载指令指定的地址和另一个处理器之一，将数据存储到高速缓冲存储器中; 以及第二加载指令执行单元，用于从主存储器或另一处理器中的一个处理器读取与由第二加载指令指定的地址相对应的数据，以将数据存储到高速缓冲存储器中，并请求系统控制单元将数据发送到另一个处理器

6. 发明申请

US20080222434A1 Method of power-aware job management and computer system 有权
标题翻译：功率感知工作管理和计算机系统的方法
公开(公告)号：US20080222434A1
公开(公告)日：2008-09-11
申请号：US12068086
申请日：2008-02-01
申请人： Masaaki Shimizu , Naonobu Sukegawa
发明人： Masaaki Shimizu , Naonobu Sukegawa
IPC分类号： G06F9/46 , G06F1/26
CPC分类号： G06F1/3203 , G06F1/329 , G06F9/5027 , Y02D10/22 , Y02D10/24
摘要： Provided is a method used in a computer system which includes at least one host computer, the method including managing a job to be executed by the host computer and a power supply of the host computer, the method including the procedures of: receiving the job; storing the received job; scheduling an execution plan for the stored job; determining, based on the execution plan of the job, a timing to execute power control of the host computer; determining a host computer to execute the power control when the determined timing to execute the power control is reached; controlling the power supply of the determined host computer; and executing the scheduled job.
摘要翻译：提供了一种在计算机系统中使用的方法，其包括至少一个主计算机，所述方法包括管理由主计算机执行的作业和主计算机的电源，所述方法包括以下过程：接收作业; 存储所接收的作业; 调度存储作业的执行计划; 基于作业的执行计划确定执行主计算机的功率控制的定时; 当达到确定的执行功率控制的定时时，确定主计算机执行功率控制; 控制所确定的主机的电源; 并执行预定作业。

7. 发明授权

US07159079B2 Multiprocessor system 有权
标题翻译：多处理器系统
公开(公告)号：US07159079B2
公开(公告)日：2007-01-02
申请号：US10886036
申请日：2004-07-08
申请人： Naonobu Sukegawa
发明人： Naonobu Sukegawa
IPC分类号： G06F13/00
CPC分类号： G06F12/0817 , G06F12/0813 , G06F12/0831
摘要： A splittable/connectible bus 140 and a network 1000 for transmitting coherence transactions between CPUs are provided between the CPUs, and a directory 160 and a group setup register 170 for storing bus-splitting information are provided in a directory control circuit 150 that controls cache invalidation. The bus is dynamically set to a split or connected state to fit a particular execution form of a job, and the directory control circuit uses the directory in order to manage all inter-CPU coherence control sequences in response to the above setting, while at the same time, in accordance with information of the group setup register, omitting dynamically bus-connected CPU-to-CPU cache coherence control, and conducting only bus-split CPU-to-CPU cache coherence control through the network.Thus, decreases in performance scalability due to an inter-CPU coherence-processing overhead are relieved in a system having multiple CPUs and guaranteeing inter-CPU cache coherence by use of hardware.
摘要翻译：在CPU之间提供可拆卸/可连接总线140和用于在CPU之间传输相干事务的网络1000，并且在目录控制电路150中提供用于存储总线分解信息的目录160和组设置寄存器170，其控制高速缓存无效。总线被动态设置为分割或连接状态以适合作业的特定执行形式，并且目录控制电路使用该目录以便响应于上述设置来管理所有CPU间相干控制序列，而在同时，根据组设置寄存器的信息，省略动态总线连接的CPU到CPU缓存一致性控制，并通过网络进行总线分割CPU到CPU缓存一致性控制。因此，在具有多个CPU的系统中减轻了由于CPU间相干处理开销引起的性能可扩展性的降低，并且通过使用硬件来保证CPU间高速缓存的一致性。

8. 发明授权

US06295579B1 Parallel processor system including a cache memory subsystem that has independently addressable local and remote data areas 失效
标题翻译：并行处理器系统包括具有可独立寻址的本地和远程数据区的高速缓存存储器子系统
公开(公告)号：US06295579B1
公开(公告)日：2001-09-25
申请号：US09070851
申请日：1998-05-01
申请人： Naonobu Sukegawa , Tshiaki Tarui , Hiroaki Fujii , Hideya Akashi
发明人： Naonobu Sukegawa , Tshiaki Tarui , Hiroaki Fujii , Hideya Akashi
IPC分类号： G06F1200
CPC分类号： G06F12/0813 , G06F12/0848 , G06F2212/272
摘要： A parallel processor system controls access to a distributed shared memory and to plural cache memories to prevent frequently-used local data from being flushed out of a cache memory. The parallel processor system includes a plurality of nodes each including a processor and a shared memory in a distributed shared memory arrangement, and a local-remote divided cache memory system, wherein local data and remote data are controlled separately. Each local-remote divided cache memory system includes a local data area, a remote data area, and a cache memory controller by which either the local data area or the remote data area is accessed according to the contents of an access request.
摘要翻译：并行处理器系统控制对分布式共享存储器和多个高速缓冲存储器的访问，以防止频繁使用的本地数据被从高速缓冲存储器中冲出。并行处理器系统包括多个节点，每个节点包括分布式共享存储器布置中的处理器和共享存储器，以及本地远程分割高速缓存存储器系统，其中本地数据和远程数据被单独控制。每个本地远程分割高速缓冲存储器系统包括根据访问请求的内容访问本地数据区域或远程数据区域的本地数据区域，远程数据区域和高速缓存存储器控制器。

9. 发明申请

US20070124523A1 Heterogeneous multiprocessor system and OS configuration method thereof 有权
标题翻译：异构多处理器系统及其OS配置方法
公开(公告)号：US20070124523A1
公开(公告)日：2007-05-31
申请号：US11357088
申请日：2006-02-21
申请人： Masaaki Shimizu , Naonobu Sukegawa
发明人： Masaaki Shimizu , Naonobu Sukegawa
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： Interrupt process generated in a processor for arithmetic operation is offloaded onto a system control processor, thereby reducing disturbance to the processor for arithmetic operation. A heterogeneous multiprocessor system includes: means which accepts an interrupt in each CPU; means which inquires the accepted interrupt of an interrupt destination management table to select an interrupt destination CPU; means which queues the accepted interrupt; means which generates an inter-CPU interrupt to the selected interrupt destination CPU; each means which receives the inter-CPU interrupt in the interrupt source CPU, performs interrupt process of the interrupt source CPU, and generates the inter-CPU interrupt to the interrupt source CPU in the interrupt destination CPU; means which performs an interrupt end process; and means which performs interrupt process in its own CPU when the interrupt destination CPU selected as a result of the inquiry to the interrupt destination management table is its own CPU.
摘要翻译：在用于算术运算的处理器中产生的中断处理被卸载到系统控制处理器上，从而减少对处理器的干扰以进行算术运算。异构多处理器系统包括：在每个CPU中接受中断的装置; 查询中断目的地管理表的接受中断以选择中断目的地CPU的装置; 意味着对接受的中断进行排队; 为所选择的中断目标CPU产生CPU间中断的装置; 在中断源CPU中接收到CPU间中断的各种方式，执行中断源CPU的中断处理，并在中断目标CPU中产生中断源CPU中断CPU中断; 执行中断结束过程的手段; 以及当作为对中断目的地管理表的查询结果而选择的中断目的地CPU是其自己的CPU时，在其自己的CPU中执行中断处理的装置。

10. 发明授权

US06466988B1 Multiprocessor synchronization and coherency control system 有权
标题翻译：多处理器同步和一致性控制系统
公开(公告)号：US06466988B1
公开(公告)日：2002-10-15
申请号：US09473276
申请日：1999-12-28
申请人： Naonobu Sukegawa , Kouki Uwano , Shigeko Hashimoto , Masakazu Fukagawa , Eiki Kamada
发明人： Naonobu Sukegawa , Kouki Uwano , Shigeko Hashimoto , Masakazu Fukagawa , Eiki Kamada
IPC分类号： G06F1300
CPC分类号： G06F12/0815 , G06F12/0822
摘要： A shared main memory type multiprocessor is arranged to have a switch connection type. The multiprocessor prepares an instruction for outputting a synchronization transaction. When each CPU executes this instruction, after all the transactions of the preceding instructions are output, the synchronization transaction is output to the main memory and the coherence controller. By the synchronization transaction, the main memory serializes the memory accesses and the coherence controller guarantees the completion of the cache coherence control. This makes it possible to serialize the memory accesses and guarantee the completion of the cache coherence control at the same time.
摘要翻译：共享的主存储器型多处理器被布置成具有开关连接类型。多处理器准备用于输出同步事务的指令。当每个CPU执行该指令时，在输出上述指令的所有事务之后，将同步事务输出到主存储器和相干控制器。通过同步事务，主存储器将存储器访问序列化，并且相干控制器保证高速缓存一致性控制的完成。这使得可以同时序列化存储器访问并保证高速缓存一致性控制的完成。

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