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1. 发明授权

US6081035A Microelectronic bond ribbon design 失效
标题翻译：微电子键带设计
公开(公告)号：US6081035A
公开(公告)日：2000-06-27
申请号：US736415
申请日：1996-10-24
申请人： Michael Warner , Thomas H. Distefano , David Gibson
发明人： Michael Warner , Thomas H. Distefano , David Gibson
IPC分类号： H01L23/495 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/50 , H01L23/49541 , H01L23/49558 , H01L23/49572 , H01L23/49586 , H01L2924/01027 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/12042 , H01L2924/14
摘要： An improved bond ribbon design, said bond ribbon having a dual taper that functions to localize the bending along a predetermined distribution of the bond ribbon during the bonding of the bond ribbon to an associated contact of a semiconductor chip. Use of the dual-tapered bond ribbons during bonding provides a bonded bond ribbon having a form that is substantially s-shaped. The radii of curvature making out the curves of the s-shaped configuration can be predetermined and controlled by the length and taper of the individual tapered section. The improved bond ribbon further comprises an anchor pad, said anchor pad characterized by a large surface area that decreases the likelihood of delamination of it from a supporting dielectric structure. A multiplicity of these improved bond ribbons can be fabricated in an external connection component so as to facilitate the alignment and bonding process of multiple bond ribbons to corresponding contacts of the semiconductor chip and can be designed, configured or placed such that the corner contact of the semiconductor chip are accessible for bonding. With respect to the problems associated with accessing the corner contacts of a semiconductor chip when using the connection component, three approaches are offered as solutions.
摘要翻译：改进的粘结带设计，所述粘结带具有双锥度，其功能是在粘结带与半导体芯片的相关联的接合处期间沿着粘合带的预定分布定位弯曲。在接合期间使用双锥形粘结带提供具有基本上S形的形式的粘结粘结带。形成s形构造曲线的曲率半径可以由单个锥形部分的长度和锥度来预定和控制。改进的粘结带还包括锚垫，所述锚垫的特征在于大的表面积减小了其从支撑介质结构分层的可能性。可以在外部连接部件中制造多个这些改进的接合带，以便于将多个接合带对准和接合处理到半导体芯片的对应接点，并且可以被设计，配置或放置，使得半导体芯片可用于接合。关于在使用连接部件时访问半导体芯片的角接触相关的问题，提供三种方案作为解决方案。

2. 发明授权

US06191473B1 Bonding lead structure with enhanced encapsulation 失效
标题翻译：结合引线结构增强封装
公开(公告)号：US06191473B1
公开(公告)日：2001-02-20
申请号：US09315252
申请日：1999-05-20
申请人： Thomas H. Distefano
发明人： Thomas H. Distefano
IPC分类号： H01L2352
CPC分类号： H01L24/50 , H01L23/49572 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/12042 , H01L2924/00
摘要： A connection component for a semiconductor chip includes a support structure having a top surface including a dielectric material and a bottom surface. The support structure includes a central portion, a peripheral portion and one or more gaps extending substantially between the central portion and the peripheral portion. A bus overlies the top surface of the support structure. The each bus has an outer edge which overlies the peripheral portion of the support structure and an inner edge which overlies the one or more gaps. The support structure also includes one or more electrically conductive leads having first ends secured to the central portion and second ends overlying the gaps and being secured to the inner edge of the bus. The second ends of the leads are displaceable relative to the bus in response to bonding forces being applied to the leads for engaging contacts on a semiconductor chip.
摘要翻译：用于半导体芯片的连接部件包括具有包括电介质材料和底面的顶表面的支撑结构。支撑结构包括中心部分，周边部分和基本上在中心部分和周边部分之间延伸的一个或多个间隙。公共汽车覆盖在支撑结构的顶面上。每个总线具有覆盖支撑结构的周边部分的外边缘和覆盖在一个或多个间隙上的内边缘。支撑结构还包括一个或多个导电引线，其具有固定到中心部分的第一端和覆盖间隙的第二端并固定到总线的内边缘。引线的第二端可以响应于施加到引线上的接合力而相对于母线移位，以接合半导体芯片上的触点。

3. 发明授权

US6133639A Compliant interface for semiconductor chip and method therefor 失效
标题翻译：用于半导体芯片的兼容接口及其方法
公开(公告)号：US6133639A
公开(公告)日：2000-10-17
申请号：US842313
申请日：1997-04-24
申请人： Zlata Kovac , Craig Mitchell , Thomas H. Distefano , John W. Smith
发明人： Zlata Kovac , Craig Mitchell , Thomas H. Distefano , John W. Smith
IPC分类号： H01L23/12 , H01L21/56 , H01L21/60 , H01L23/28 , H01L23/48 , H01L23/498 , H05K1/11 , H05K3/36 , H05K3/40 , H01L23/52 , H01L29/40
CPC分类号： H01L24/81 , H01L21/56 , H01L21/563 , H01L23/49811 , H01L23/49827 , H01L23/4985 , H01L24/72 , H01L24/75 , H05K3/4084 , H01L2224/16 , H01L2224/73203 , H01L2224/73204 , H01L2224/75 , H01L2224/75301 , H01L2224/81801 , H01L2224/83136 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/15311 , H01L2924/1532 , H01L2924/16152 , H01L2924/19041 , H01L2924/19043 , H05K1/118 , H05K2201/0133 , H05K2201/0394 , H05K2201/0397 , H05K2201/09081 , H05K2201/091 , H05K2203/063 , H05K3/361 , Y10T29/4913 , Y10T29/49144 , Y10T29/49174
摘要： A method and an apparatus for providing a planar and compliant interface between a semiconductor chip and its supporting substrate to accommodate for the thermal coefficient of expansion mismatch therebetween. The complaint interface is comprised of a plurality of compliant pads defining channels between adjacent pads. The pads are typically compressed between a flexible film chip carrier and the chip. A compliant filler is further disposed within the channels to form a uniform encapsulation layer having a controlled thickness.
摘要翻译：一种用于在半导体芯片和其支撑衬底之间提供平面和兼容接口以适应其间的热膨胀失配的方法和装置。投诉界面由在相邻的焊盘之间限定通道的多个柔性焊盘构成。垫通常在柔性膜芯片载体和芯片之间被压缩。在通道内进一步布置柔顺填料以形成具有受控厚度的均匀包封层。

4. 发明授权

US5852326A Face-up semiconductor chip assembly 失效
标题翻译：面朝上半导体芯片组装
公开(公告)号：US5852326A
公开(公告)日：1998-12-22
申请号：US110527
申请日：1998-07-06
申请人： Igor Y. Khandros , Thomas H. Distefano
发明人： Igor Y. Khandros , Thomas H. Distefano
IPC分类号： H01L21/60 , H01L21/822 , H01L21/98 , H01L23/13 , H01L23/31 , H01L23/485 , H01L23/498 , H01L23/58 , H01L25/065 , H01L25/16 , H01L23/48 , H01L23/52
CPC分类号： H01L21/6836 , H01L21/822 , H01L22/32 , H01L23/13 , H01L23/3107 , H01L23/3164 , H01L23/485 , H01L23/49805 , H01L23/49827 , H01L23/4985 , H01L23/49861 , H01L24/27 , H01L24/81 , H01L25/0657 , H01L25/16 , H01L25/50 , H01L2221/68327 , H01L2224/16145 , H01L2224/274 , H01L2224/48091 , H01L2224/4824 , H01L2224/4911 , H01L2224/73265 , H01L2224/81801 , H01L2225/0651 , H01L2225/06517 , H01L2225/0652 , H01L2225/06579 , H01L2225/06596 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/351
摘要： A semiconductor assembly having contacts on a peripheral region of the top surface of a chip and a backing element overlying the bottom surface of the chip. The backing element has terminals such that at least some of the terminals overlie the bottom surface of the chip. Leads including bonding wires extending alongside the edges of the chip connect the contacts and the terminals. The terminals of the assembly are movable with respect to the chip.
摘要翻译：一种半导体组件，其在芯片顶表面的周边区域和覆盖芯片底表面的背衬元件上具有触点。背衬元件具有端子，使得端子中的至少一些覆盖在芯片的底表面上。包括沿芯片边缘延伸的接合线的引线连接触点和端子。组件的端子可相对于芯片移动。

5. 发明授权

US5834339A Methods for providing void-free layers for semiconductor assemblies 失效
标题翻译：为半导体组件提供无空隙层的方法
公开(公告)号：US5834339A
公开(公告)日：1998-11-10
申请号：US610610
申请日：1996-03-07
申请人： Thomas H. Distefano , Joseph Fjelstad
发明人： Thomas H. Distefano , Joseph Fjelstad
IPC分类号： H01L21/56 , H01L21/68 , H01L23/31 , H01L23/495 , H01L21/44
CPC分类号： H01L21/568 , H01L21/561 , H01L21/565 , H01L21/6835 , H01L23/3107 , H01L23/3114 , H01L23/49572 , H01L24/32 , H01L24/80 , H01L24/81 , H01L24/92 , H01L24/97 , H01L2224/08225 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/80203 , H01L2224/80207 , H01L2224/81192 , H01L2224/81904 , H01L2224/83209 , H01L2224/9212 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01018 , H01L2924/01033 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/15311
摘要： A method for the removal of voids and gas bubbles within uncured or partially cured microelectronic component encapsulants and adhesive/chip attach layers. A sealed void or gas bubble within a gap between a microelectronic component and a supporting substrate is substantially eliminated through the application of a uniform pressure (isostatic or hydrostatic) and energy such that a substantially void/bubble free interposer layer is created.
摘要翻译：在未固化或部分固化的微电子部件密封剂和粘合剂/芯片附着层中去除空隙和气泡的方法。通过施加均匀的压力（等静压或静水压）和能量使得产生基本上无空隙/无气泡的中间层，基本上消除了微电子部件和支撑基板之间的间隙内的密封的空隙或气泡。

6. 发明授权

US5794330A Microelectronics unit mounting with multiple lead bonding 失效
公开(公告)号：US5794330A
公开(公告)日：1998-08-18
申请号：US436649
申请日：1995-05-08
申请人： Thomas H. Distefano , John W. Smith, Jr.
发明人： Thomas H. Distefano , John W. Smith, Jr.
IPC分类号： H01L21/48 , H01L21/60 , H01L23/49 , H01L23/498 , H05K3/34
CPC分类号： H01L24/10 , H01L21/486 , H01L21/4885 , H01L23/49827 , H01L24/13 , H01L24/81 , H01L2224/13 , H01L2224/13099 , H01L2224/45144 , H01L2224/78301 , H01L2224/81801 , H01L2224/85205 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12042 , H01L2924/19041 , H01L2924/19042 , Y10T29/49126 , Y10T29/49144 , Y10T29/49146 , Y10T29/49208
摘要： A component for mounting semiconductor chips or other microelectronic units includes a flexible top sheet with an array of terminals on it, and with flexible leads extending downwardly from the terminals. A compliant dielectric support layer surrounds the leads, holding the lead tips in precise locations. The leads are desirably formed from wire such as gold wire, and have eutectic bonding alloy on their tips. The component can be laminated to a chip or other unit under heat and pressure to form a complete subassembly with no need for individual bonding to the contacts of the chip. The subassembly can be tested readily and provides compensation for thermal expansion.

7. 发明授权

US5766987A Microelectronic encapsulation methods and equipment 失效
标题翻译：微电子封装方法和设备
公开(公告)号：US5766987A
公开(公告)日：1998-06-16
申请号：US532235
申请日：1995-09-22
申请人： Craig Mitchell , Thomas H. Distefano
发明人： Craig Mitchell , Thomas H. Distefano
IPC分类号： H01L21/56 , H01L21/44
CPC分类号： H01L21/565 , H01L2924/0002
摘要： Microelectronic assemblies such as semiconductor chip assemblies are encapsulated. During encapsulation, the terminals carried by a dielectric layer in each assembly, and the bottom surface of the semiconductor chip in each assembly are protected by covering layers. The covering layers confine the liquid encapsulant and prevent contamination of the terminals and chip bottom surfaces. The encapsulation process may be conducted by using a tilting fixture. The liquid encapsulant and the assemblies are placed into the fixture, the fixture is closed and evacuated, and the encapsulant is then poured onto the assemblies while maintaining the fixture under vacuum. The fixture is then pressurized and maintained under pressure during cure of the encapsulant.
摘要翻译：诸如半导体芯片组件的微电子组件被封装。在封装期间，每个组件中由介电层承载的端子和每个组件中的半导体芯片的底表面由覆盖层保护。覆盖层限制液体密封剂，并防止端子和芯片底面的污染。封装过程可以通过使用倾斜夹具进行。将液体密封剂和组件放入固定装置中，将固定装置关闭并抽真空，然后将密封剂倒入组件上，同时将固定装置保持在真空状态。然后将固定装置加压并在密封剂固化期间保持压力。

8. 发明授权

US5632631A Microelectronic contacts with asperities and methods of making same 失效
标题翻译：微电子接触与粗糙及其制作方法
公开(公告)号：US5632631A
公开(公告)日：1997-05-27
申请号：US306205
申请日：1994-09-14
申请人： Joseph Fjelstad , John W. Smith , Thomas H. Distefano , James Zaccardi , A. Christian Walton
发明人： Joseph Fjelstad , John W. Smith , Thomas H. Distefano , James Zaccardi , A. Christian Walton
IPC分类号： B23K1/19 , G01R1/04 , G01R1/067 , G01R1/073 , G01R3/00 , G01R31/28 , H01L21/48 , H01L23/48 , H01L23/498 , H01R4/02 , H01R12/00 , H01R12/52 , H01R12/57 , H01R12/70 , H01R12/71 , H01R13/24 , H01R43/16 , H05K1/11 , H05K3/32 , H05K3/34 , H05K3/40 , H05K7/08 , H05K7/10 , H01R9/09
CPC分类号： H05K7/1084 , G01R1/0466 , G01R1/06744 , G01R1/07357 , H01L21/4853 , H01L23/49816 , H01L23/49827 , H01R13/2485 , H05K3/326 , H05K3/3436 , H05K7/1069 , G01R1/06711 , G01R1/06727 , G01R1/06733 , G01R3/00 , H01L2224/16237 , H01L2224/45144 , H01L2224/8114 , H01L2224/81385 , H01L2224/81899 , H01L24/81 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01074 , H01L2924/01075 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/12042 , H01L2924/14 , H01L2924/30107 , H01R12/7076 , H05K1/118 , H05K2201/0382 , H05K2201/0397 , H05K2201/1059 , H05K2201/10734 , H05K3/3431 , H05K3/4092 , Y02P70/613 , Y10T29/49117 , Y10T29/49126 , Y10T29/49155 , Y10T29/49156 , Y10T29/49204 , Y10T29/4921 , Y10T29/49222 , Y10T29/49224
摘要： Microelectronic contacts, such as flexible, tab-like, cantilever contacts, are provided with asperities disposed in a regular pattern. Each asperity has a sharp feature at its tip remote from the surface of the contact. As mating microelectronic elements are engaged with the contacts, a wiping action causes the sharp features of the asperities to scrape the mating element, so as to provide effective electrical interconnection and, optionally, effective metallurgical bonding between the contact and the mating element upon activation of a bonding material.
摘要翻译：诸如柔性的，片状的悬臂触点之类的微电子触点具有以规则图案设置的凹凸。每个粗糙部分的尖端具有远离接触表面的尖端特征。当配合的微电子元件与触点接合时，擦拭动作导致粗糙的尖锐特征刮擦配合元件，以便在触发和配合元件激活时提供有效的电互连以及可选的有效的冶金结合接合材料。

9. 发明授权

US06780747B2 Methods for providing void-free layers for semiconductor assemblies 有权
标题翻译：为半导体组件提供无空隙层的方法
公开(公告)号：US06780747B2
公开(公告)日：2004-08-24
申请号：US10097032
申请日：2002-03-13
申请人： Thomas H. Distefano , Joseph Fjelstad
发明人： Thomas H. Distefano , Joseph Fjelstad
IPC分类号： H01L2144
CPC分类号： H01L21/568 , H01L21/561 , H01L21/565 , H01L21/6835 , H01L23/3107 , H01L23/3114 , H01L23/49572 , H01L24/32 , H01L24/80 , H01L24/81 , H01L24/92 , H01L24/97 , H01L2224/08225 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/80203 , H01L2224/80207 , H01L2224/81192 , H01L2224/81904 , H01L2224/83209 , H01L2224/9212 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01018 , H01L2924/01033 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/15311 , H01L2924/00 , H01L2924/3512 , H01L2924/00014 , H01L2224/80001 , H01L2224/81
摘要： A method of providing a substantially void free layer for one or more flip chip assemblies, or one or more microelectronic components, utilizing a curable encapsulant. Also disclosed is a method of injecting an encapsulant into an assembly and a method of treating a microelectronic component to form a void free layer.
摘要翻译：一种利用可固化密封剂为一个或多个倒装芯片组件或一个或多个微电子部件提供基本无空隙的方法。还公开了将密封剂注入到组件中的方法以及处理微电子部件以形成无空隙层的方法。

10. 发明授权

US06709895B1 Packaged microelectronic elements with enhanced thermal conduction 有权
标题翻译：封装的微电子元件具有增强的热传导
公开(公告)号：US06709895B1
公开(公告)日：2004-03-23
申请号：US09628049
申请日：2000-07-27
申请人： Thomas H. Distefano
发明人： Thomas H. Distefano
IPC分类号： H01L2144
CPC分类号： H01L24/73 , H01L23/16 , H01L23/3128 , H01L23/4334 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/16225 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/48465 , H01L2224/49109 , H01L2224/73257 , H01L2224/73265 , H01L2224/83194 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01019 , H01L2924/01028 , H01L2924/01029 , H01L2924/01042 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H01L2924/351 , H01L2924/00 , H01L2924/00012 , H01L2224/0401
摘要： A semiconductor chip is mounted in face-up disposition on a dielectric element, with thermally conductive but flexible elements disposed between the chip bottom surface and the top surface of the dielectric element so as to provide a compliant but thermally conductive path from the chip to a substrate which is bonded to the terminals. A spreader having coefficient of thermal expansion substantially equal to that of the chip overlies the front surface and constrains an encapsulant surrounding the leads so as to minimize shear deformation of the encapsulant.
摘要翻译：半导体芯片以面朝上的布置安装在电介质元件上，其中导热但柔性的元件设置在芯片底表面和电介质元件的顶表面之间，从而提供从芯片到与端子接合的基板。具有基本上等于芯片的热膨胀系数的扩展器覆盖在前表面上，并且限制围绕引线的密封剂，以便最小化密封剂的剪切变形。

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