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1. 发明授权

US06400631B1 Circuit, system and method for executing a refresh in an active memory bank 有权
标题翻译：用于在活动存储体中执行刷新的电路，系统和方法
公开(公告)号：US06400631B1
公开(公告)日：2002-06-04
申请号：US09662728
申请日：2000-09-15
申请人： Michael W. Williams , Jim M. Dodd
发明人： Michael W. Williams , Jim M. Dodd
IPC分类号： G11C1304
CPC分类号： G11C11/406
摘要： A memory containing a plurality of memory banks and a plurality of sense amplifiers. Also, the memory device contains a multiplexer and logic. The logic receives a refresh request for one of the plurality of memory banks and instructs the multiplexer to select one of the plurality of sense amplifiers in response to the refresh request.
摘要翻译：一种包含多个存储体和多个读出放大器的存储器。此外，存储器件包含多路复用器和逻辑。逻辑接收对多个存储器组中的一个的刷新请求，并且指示多路复用器响应于刷新请求选择多个读出放大器之一。

2. 发明授权

US06553450B1 Buffer to multiply memory interface 有权
标题翻译：缓冲区来乘以内存接口
公开(公告)号：US06553450B1
公开(公告)日：2003-04-22
申请号：US09664985
申请日：2000-09-18
申请人： Jim M. Dodd , Michael W. Williams , John B. Halbert , Randy M. Bonella , Chung Lam
发明人： Jim M. Dodd , Michael W. Williams , John B. Halbert , Randy M. Bonella , Chung Lam
IPC分类号： G06F1202
CPC分类号： G06F13/16 , Y02D10/14
摘要： Providing electrical isolation between the chipset and the memory data is disclosed. The disclosure includes providing at least one buffer in a memory interface between a chipset and memory modules. Each memory module includes a plurality of memory ranks. The at least one buffer allows the memory interface to be split into first and second sub-interfaces. The first sub-interface is between the chipset and the buffer. The second sub-interface is between the buffer and the memory modules. The method also includes interleaving output of the memory ranks in the memory modules, and configuring the at least one buffer to properly latch data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.
摘要翻译：公开了在芯片组和存储器数据之间提供电隔离。本公开包括在芯片组和存储器模块之间的存储器接口中提供至少一个缓冲器。每个存储器模块包括多个存储器等级。至少一个缓冲器允许将存储器接口拆分成第一和第二子接口。第一个子接口位于芯片组和缓冲区之间。第二个子接口位于缓冲区和内存模块之间。该方法还包括交织存储器模块中的存储器级别的输出，以及配置至少一个缓冲器以适当地锁存正在芯片组和存储器模块之间传输的数据。第一子接口和第二子接口彼此独立地操作，但是彼此同步。

3. 发明申请

US20150032941A1 NON-VOLATILE MEMORY INTERFACE 有权
标题翻译：非易失性存储器接口
公开(公告)号：US20150032941A1
公开(公告)日：2015-01-29
申请号：US14128669
申请日：2013-07-25
申请人： Eng Hun Ooi , Robert J. Royer, JR. , Michael W. Williams , Jeffrey R. Wilcox , Ritesh B. Trivedi , Blaise Fanning
发明人： Eng Hun Ooi , Robert J. Royer, JR. , Michael W. Williams , Jeffrey R. Wilcox , Ritesh B. Trivedi , Blaise Fanning
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F3/0679 , G06F12/02 , G06F13/12 , G06F13/16 , G06F13/1668 , G06F13/38 , G06F13/4234 , G06F2212/7202
摘要： In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.
摘要翻译：在一个实施例中，存储器接口可以发送请求被发送的指示。该指示可以经由存储器接口和非易失性存储器之间的点对点总线发送到非易失性存储器。存储器接口可以经由总线将请求发送到非易失性存储器。请求可以包括可用于标识用于存储或读取数据的位置的地址。非易失性存储器可以从总线获取请求并处理请求。在处理请求之后，非易失性存储器可以向存储器接口发送指示非易失性存储器具有发送到存储器接口的响应的指示。存储器接口可以向总线授予对非易失性存储器的访问。在被允许访问总线之后，非易失性存储器可以将响应发送到存储器接口。

4. 发明授权

US06618791B1 System and method for controlling power states of a memory device via detection of a chip select signal 有权
标题翻译：用于通过芯片选择信号的检测来控制存储器件的电源状态的系统和方法
公开(公告)号：US06618791B1
公开(公告)日：2003-09-09
申请号：US09677138
申请日：2000-09-29
申请人： James M. Dodd , Michael W. Williams
发明人： James M. Dodd , Michael W. Williams
IPC分类号： G06F1200
CPC分类号： G11C5/143 , G06F1/3225 , G06F1/3275 , Y02D10/14 , Y02D50/20
摘要： A memory system and a method for controlling power states of a memory device, or a portion thereof, are provided. The memory system includes memory devices, such as DRAMs, a memory controller, chip select lines, and logic for detecting chip select signals from the chip select lines. Each memory device, or a portion therein, is connected to the memory controller by a chip select line. Each chip select line allows the transmission of a chip select signal to a corresponding memory device, or a corresponding portion of the memory device, to select the corresponding memory device, or a portion thereof, to receive commands. Logic is provided to detect the chip select signal. When the logic detects a chip select signal provided to a corresponding memory device, or a portion thereof, that is in a power state lower than its idle state, the memory device, or a portion thereof, is automatically moved from the lower power state to a higher power state.
摘要翻译：提供了一种用于控制存储器件或其一部分的电源状态的存储器系统和方法。存储器系统包括诸如DRAM的存储器件，存储器控制器，芯片选择线以及用于检测来自芯片选择线的芯片选择信号的逻辑。每个存储器件或其中的部分通过芯片选择线连接到存储器控制器。每个芯片选择线允许将芯片选择信号传输到对应的存储器件或存储器件的相应部分，以选择相应的存储器件或其一部分来接收命令。提供逻辑来检测芯片选择信号。当逻辑检测到提供给处于低于其空闲状态的功率状态的相应存储器件或其一部分的芯片选择信号时，存储器件或其一部分自动从较低功率状态移动到更高的功率状态。

5. 发明授权

US06226730B1 Achieving page hit memory cycles on a virtual address reference 失效
标题翻译：实现虚拟地址引用上的页面命中内存循环
公开(公告)号：US06226730B1
公开(公告)日：2001-05-01
申请号：US09092426
申请日：1998-06-05
申请人： Robert N. Murdoch , Michael W. Williams
发明人： Robert N. Murdoch , Michael W. Williams
IPC分类号： G06F1210
CPC分类号： G06F12/0215
摘要： An apparatus and method for accessing a memory. A source address that includes a page address and a page offset is received. The page address requires translation in order to form a first address that can be used to transfer data from a row of memory cells into a sense amplifier array in a memory. The page address is compared to contents of one or more page registers to determine if the data is present in the sense amplifier array as a result of a previous memory access. A second address is asserted to access a portion of the data if the data is determined to be present in the sense amplifier array.
摘要翻译：一种用于访问存储器的装置和方法。接收包含页面地址和页面偏移的源地址。页面地址需要转换以形成可以用于将数据从一行存储器单元传送到存储器中的读出放大器阵列的第一地址。将页面地址与一个或多个页面寄存器的内容进行比较，以确定数据是否作为先前存储器访问的结果存在于读出放大器阵列中。如果数据被确定为存在于读出放大器阵列中，则第二地址被断言以访问数据的一部分。

6. 发明申请

US20090316800A1 Low speed access to dram 失效
标题翻译：低速接入电话
公开(公告)号：US20090316800A1
公开(公告)日：2009-12-24
申请号：US12583920
申请日：2009-08-24
申请人： David J. Zimmerman , Michael W. Williams
发明人： David J. Zimmerman , Michael W. Williams
IPC分类号： H04B3/00 , G06F12/06
CPC分类号： G06F13/28 , G11C5/066 , G11C7/10 , G11C7/1078 , G11C7/1084 , G11C7/109 , G11C11/4076 , G11C11/4096
摘要： Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.
摘要翻译：实施例通过高速串行链路以比高速串行链路常规操作更慢的速度提供对存储器的访问。实施例可以包括具有耦合到协议识别电路的差分接收器的存储器设备，具有与差分接收器的第一输入端耦合的第一接收器的低速接收电路和与差分接收器的第二输入端耦合的第二接收器其中低速接收电路与协议识别电路耦合，允许第一和第二接收机以与差分接收机不同的频率访问协议识别块。

7. 发明授权

US06976121B2 Apparatus and method to track command signal occurrence for DRAM data transfer 失效
标题翻译：用于跟踪DRAM数据传输的命令信号发生的装置和方法
公开(公告)号：US06976121B2
公开(公告)日：2005-12-13
申请号：US10058838
申请日：2002-01-28
申请人： Narendra S. Khandekar , Michael W. Williams , Howard S. David
发明人： Narendra S. Khandekar , Michael W. Williams , Howard S. David
IPC分类号： G06F13/16 , G11C7/10
CPC分类号： G11C7/1063 , G06F13/1668 , G11C7/1051
摘要： An apparatus and a method to track command signal occurrence for DRAM data transfer have been disclosed. In one embodiment, the apparatus includes an interface to couple to a data bus, the data bus to transfer data between the interface and one or more memory devices, and a logic unit to generate a command occurrence signal to identify when a command signal is issued, wherein a set of data transfer operations on one of the one or more memory devices are completed in response to the command occurrence signal, a transition of a flag signal, and a chip select signal corresponding to the one memory device. Other embodiments have been claimed and described.
摘要翻译：已经公开了用于跟踪用于DRAM数据传送的命令信号发生的装置和方法。在一个实施例中，该装置包括耦合到数据总线的接口，该数据总线在接口和一个或多个存储器件之间传送数据，以及一个逻辑单元，以产生命令发生信号，以识别何时发出命令信号其中响应于所述命令发生信号，标志信号的转换和对应于所述一个存储器件的片选信号而完成所述一个或多个存储器件之一上的一组数据传送操作。已经要求和描述了其它实施例。

8. 发明授权

US06928494B1 Method and apparatus for timing-dependant transfers using FIFOs 失效
标题翻译：使用FIFO进行定时相关传输的方法和装置
公开(公告)号：US06928494B1
公开(公告)日：2005-08-09
申请号：US09538386
申请日：2000-03-29
申请人： Andrew M. Volk , Michael W. Williams , David J. McDonnell
发明人： Andrew M. Volk , Michael W. Williams , David J. McDonnell
IPC分类号： G11C7/10 , G06F3/00
CPC分类号： G11C7/10
摘要： A method and apparatus for communicating commands and/or data between two different time domains. In one embodiment, multiple memory commands are placed into one or more FIFOs in a manner that specifies the delays that must take place between execution of the different commands. Along with the commands, delay information is placed into the FIFOs, specifying the number of clock cycles, or other form of time delay, that must elapse between execution of a command and execution of a subsequent command. This delay information is used to delay the execution of the subsequent command for the specified time period, while minimizing or eliminating any excess delays. Cue information can also be placed into the FIFOs with the commands to specify which commands must wait for other commands before beginning execution. The delay and cue information is determined and created in the time domain that initiates the transfers. The delays and cueing are executed in the other time domain. Although the different commands may be delivered through different FIFOs and can therefore have unpredictable arrival times with respect to each other, the delay and cueing information maintains the proper execution order and timing between the commands. Interactive control logic at the output of each FIFO uses the timing data to maintain execution in the proper order and with the proper inter-command delays.
摘要翻译：一种用于在两个不同时域之间传送命令和/或数据的方法和装置。在一个实施例中，多个存储器命令以指定在不同命令的执行之间必须发生的延迟的方式被放置到一个或多个FIFO中。与命令一起，将延迟信息放入FIFO中，指定执行命令和执行后续命令之间必须经过的时钟周期数量或其他形式的时间延迟。该延迟信息用于在指定的时间段内延迟后续命令的执行，同时最小化或消除任何多余的延迟。提示信息也可以放在FIFO中，其命令用于指定哪些命令在开始执行之前必须等待其他命令。在启动传输的时域中确定和创建延迟和提示信息。延迟和提示在其他时间域执行。虽然不同的命令可以通过不同的FIFO传递，并且因此可以相对于彼此具有不可预测的到达时间，但延迟和提示信息保持命令之间的正确的执行顺序和定时。每个FIFO的输出端的交互控制逻辑使用定时数据来维持正确顺序的执行和适当的指令间延迟。

9. 发明授权

US06925013B2 Obtaining data mask mapping information 有权
公开(公告)号：US06925013B2
公开(公告)日：2005-08-02
申请号：US10786940
申请日：2004-02-24
申请人： Robert J. Riesenman , James M. Dodd , Michael W. Williams
发明人： Robert J. Riesenman , James M. Dodd , Michael W. Williams
IPC分类号： G06F12/04 , G06F12/06 , G06F13/16 , G11C16/04
CPC分类号： G06F13/1626 , G06F12/04
摘要： A data mask map may be programmed into a storage device in various ways. In one embodiment, the data mask is hardwired into a selection device to reorder either the data mask bits or the data chunks. In another embodiment, a data mask map is retrieved from a location in memory. In still another embodiment, the data mask map is determined through an algorithm.

10. 发明授权

US06829184B2 Apparatus and method for encoding auto-precharge 有权
标题翻译：用于编码自动预充电的装置和方法
公开(公告)号：US06829184B2
公开(公告)日：2004-12-07
申请号：US10058567
申请日：2002-01-28
申请人： Narendra S. Khandekar , Michael W. Williams
发明人： Narendra S. Khandekar , Michael W. Williams
IPC分类号： G11C700
CPC分类号： G11C7/22 , G11C7/1072 , G11C11/4076
摘要： A technique to encode a precharge command on a flag signal used to execute data transfer to and from a DRAM.
摘要翻译：用于对用于执行到DRAM的数据传送的标志信号对预充电命令进行编码的技术。

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