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1. 发明授权

US06957307B2 Mapping data masks in hardware by controller programming 有权
标题翻译：通过控制器编程在硬件中映射数据掩码
公开(公告)号：US06957307B2
公开(公告)日：2005-10-18
申请号：US10104412
申请日：2002-03-22
申请人： Robert J. Riesenman , James M. Dodd , Michael W. Williams
发明人： Robert J. Riesenman , James M. Dodd , Michael W. Williams
IPC分类号： G06F13/16 , G06F12/00
CPC分类号： G06F13/1668
摘要： A memory controller or other device may be programmed with a data mask mapping scheme. A selection device within the memory controller may be set with the data mask mapping scheme between data and a data mask. In one embodiment, a storage device may be included and programmed with the data mask mapping scheme.
摘要翻译：存储器控制器或其他设备可以用数据掩模映射方案来编程。存储器控制器内的选择设备可以用数据掩码映射方案设置在数据和数据掩码之间。在一个实施例中，可以使用数据掩模映射方案来包含存储设备并对其进行编程。

2. 发明授权

US06952367B2 Obtaining data mask mapping information 有权
标题翻译：获取数据掩码映射信息
公开(公告)号：US06952367B2
公开(公告)日：2005-10-04
申请号：US10701025
申请日：2003-11-03
申请人： Robert J. Riesenman , James M. Dodd , Michael W. Williams
发明人： Robert J. Riesenman , James M. Dodd , Michael W. Williams
IPC分类号： G06F12/04 , G06F12/06 , G06F13/16 , G11C16/04
CPC分类号： G06F13/1626 , G06F12/04
摘要： A data mask map may be programmed into a storage device in various ways. In one embodiment, the data mask is hardwired into a selection device to reorder either the data mask bits or the data chunks. In another embodiment, a data mask map is retrieved from a location in memory. In still another embodiment, the data mask map is determined through an algorithm.
摘要翻译：数据掩模图可以以各种方式编程到存储设备中。在一个实施例中，将数据掩码硬连接到选择设备中以重新排序数据掩码位或数据块。在另一个实施例中，从存储器中的位置检索数据掩码图。在另一个实施例中，通过算法确定数据掩码图。

3. 发明授权

US06925013B2 Obtaining data mask mapping information 有权
公开(公告)号：US06925013B2
公开(公告)日：2005-08-02
申请号：US10786940
申请日：2004-02-24
申请人： Robert J. Riesenman , James M. Dodd , Michael W. Williams
发明人： Robert J. Riesenman , James M. Dodd , Michael W. Williams
IPC分类号： G06F12/04 , G06F12/06 , G06F13/16 , G11C16/04
CPC分类号： G06F13/1626 , G06F12/04
摘要： A data mask map may be programmed into a storage device in various ways. In one embodiment, the data mask is hardwired into a selection device to reorder either the data mask bits or the data chunks. In another embodiment, a data mask map is retrieved from a location in memory. In still another embodiment, the data mask map is determined through an algorithm.

4. 发明授权

US06618791B1 System and method for controlling power states of a memory device via detection of a chip select signal 有权
标题翻译：用于通过芯片选择信号的检测来控制存储器件的电源状态的系统和方法
公开(公告)号：US06618791B1
公开(公告)日：2003-09-09
申请号：US09677138
申请日：2000-09-29
申请人： James M. Dodd , Michael W. Williams
发明人： James M. Dodd , Michael W. Williams
IPC分类号： G06F1200
CPC分类号： G11C5/143 , G06F1/3225 , G06F1/3275 , Y02D10/14 , Y02D50/20
摘要： A memory system and a method for controlling power states of a memory device, or a portion thereof, are provided. The memory system includes memory devices, such as DRAMs, a memory controller, chip select lines, and logic for detecting chip select signals from the chip select lines. Each memory device, or a portion therein, is connected to the memory controller by a chip select line. Each chip select line allows the transmission of a chip select signal to a corresponding memory device, or a corresponding portion of the memory device, to select the corresponding memory device, or a portion thereof, to receive commands. Logic is provided to detect the chip select signal. When the logic detects a chip select signal provided to a corresponding memory device, or a portion thereof, that is in a power state lower than its idle state, the memory device, or a portion thereof, is automatically moved from the lower power state to a higher power state.
摘要翻译：提供了一种用于控制存储器件或其一部分的电源状态的存储器系统和方法。存储器系统包括诸如DRAM的存储器件，存储器控制器，芯片选择线以及用于检测来自芯片选择线的芯片选择信号的逻辑。每个存储器件或其中的部分通过芯片选择线连接到存储器控制器。每个芯片选择线允许将芯片选择信号传输到对应的存储器件或存储器件的相应部分，以选择相应的存储器件或其一部分来接收命令。提供逻辑来检测芯片选择信号。当逻辑检测到提供给处于低于其空闲状态的功率状态的相应存储器件或其一部分的芯片选择信号时，存储器件或其一部分自动从较低功率状态移动到更高的功率状态。

5. 发明授权

US06862653B1 System and method for controlling data flow direction in a memory system 有权
标题翻译：用于控制存储系统中数据流方向的系统和方法
公开(公告)号：US06862653B1
公开(公告)日：2005-03-01
申请号：US09664516
申请日：2000-09-18
申请人： James M. Dodd , Michael W. Williams
发明人： James M. Dodd , Michael W. Williams
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/1673
摘要： A system and method for controlling the direction of data flow in a memory system is provided. The system comprising memory devices, a memory controller, a buffering structure, and a data flow director. The memory controller sends data, such as read-data, write-data, address information and command information, to the memory devices and receives data from the memory devices. The buffering structure interconnects the memory device and the memory controller. The buffering structure is adapted to operate in a bi-directional manner for the direction of data flow therethrough. The data flow director, which may reside in the buffering structure, the memory controller, the memory devices, or an external device, controls the direction of data flow through the buffering structure based on the data transmitted from the memory controller or the memory device.
摘要翻译：提供了一种用于控制存储器系统中的数据流的方向的系统和方法。该系统包括存储器件，存储器控制器，缓冲结构和数据流导向器。存储器控制器将诸如读取数据，写入数据，地址信息和命令信息的数据发送到存储器件并从存储器件接收数据。缓冲结构将存储器件和存储器控制器互连。缓冲结构适于以双向方式操作数据流动的方向。可以驻留在缓冲结构中的数据流导向器，存储器控制器，存储器件或外部设备基于从存储器控制器或存储器件发送的数据来控制通过缓冲结构的数据流的方向。

6. 发明授权

US06772352B1 Method and apparatus for reducing the rate of commands being issued if the rate exceeds a threshold which is based upon a temperature curve 有权
标题翻译：如果速率超过基于温度曲线的阈值，则降低发出命令速率的方法和装置
公开(公告)号：US06772352B1
公开(公告)日：2004-08-03
申请号：US09677137
申请日：2000-09-29
申请人： Michael W. Williams , James M. Dodd
发明人： Michael W. Williams , James M. Dodd
IPC分类号： G06F1200
CPC分类号： G11C11/406
摘要： A method of issuing activate commands to a memory device includes issuing the activate commands to the memory device. A number of activate commands issued within a time period is counted. A determination is made as to whether the number of activate commands issued within the time period exceeds a threshold. The rate at which the activate commands are being issued is lowered if the number of activate commands being issued exceeds the threshold within the time period.
摘要翻译：向存储器件发出激活命令的方法包括向存储器件发出激活命令。对一段时间内发出的激活命令进行计数。确定在该时间段内发出的激活命令的数量是否超过阈值。如果发出的激活命令的数量在该时间段内超过阈值，则降低激活命令的发出速率。

7. 发明授权

US06553449B1 System and method for providing concurrent row and column commands 有权
标题翻译：提供并发行和列命令的系统和方法
公开(公告)号：US06553449B1
公开(公告)日：2003-04-22
申请号：US09675348
申请日：2000-09-29
申请人： James M. Dodd , Michael W. Williams
发明人： James M. Dodd , Michael W. Williams
IPC分类号： G06F1200
CPC分类号： G06F13/1684 , Y02D10/14
摘要： A system and method for providing concurrent column and row operations in a memory system is provided. The memory system includes a memory controller, a plurality of memory devices, and communication paths between the memory controller and the plurality of memory devices. The memory controller is coupled to each memory device through a communication path that provides a column chip select signal to the memory device and a communication path that provides a row chip select signal to the memory device. The dual chip select signals allow a column operation to be carried out in the memory device simultaneously with a row operation in the memory device. The communication paths further include a column command communication path that provides column commands to the memory devices, a column address communication path that provides column addresses for the column commands to the memory devices, a row command communication path that provides row commands to the memory devices, and a row address communication path that provides row addresses for the row commands to the memory device.
摘要翻译：提供了一种用于在存储器系统中提供并行列和行操作的系统和方法。存储器系统包括存储器控制器，多个存储器件以及存储器控制器和多个存储器件之间的通信路径。存储器控制器通过将存储器件提供列选择信号的通信路径和向存储器件提供行片选信号的通信路径耦合到每个存储器件。双芯片选择信号允许在存储设备中与行操作同时执行列操作。通信路径还包括向存储器件提供列命令的列命令通信路径，向存储器件提供列命令的列地址的列地址通信路径，向存储器件提供行命令的行命令通信路径以及行地址通信路径，其向行存储器设备提供行命令的行地址。

8. 发明授权

US06530006B1 System and method for providing reliable transmission in a buffered memory system 有权
标题翻译：用于在缓冲存储器系统中提供可靠传输的系统和方法
公开(公告)号：US06530006B1
公开(公告)日：2003-03-04
申请号：US09664982
申请日：2000-09-18
申请人： James M. Dodd , Michael W. Williams , John Halbert , Randy M. Bonella
发明人： James M. Dodd , Michael W. Williams , John Halbert , Randy M. Bonella
IPC分类号： G06F1200
CPC分类号： G06F13/4239
摘要： The present invention provides a system and method for providing reliable transmission in a buffered memory system. The system includes memory devices, a memory controller, data buffers, an address/command buffer, and a clock circuit. The memory controller sends data, address information, status information and command information, to the memory devices and receives data from the memory devices. The buffers interconnect the memory devices and the memory controller. The clock circuit is embedded in the addr/cmd buffer. The clock circuit takes an input clock and outputs an output clock to the data buffers and/or the memory devices to control clock-skew to the data buffers and/or the memory devices.
摘要翻译：本发明提供了一种用于在缓冲存储器系统中提供可靠传输的系统和方法。该系统包括存储器件，存储器控制器，数据缓冲器，地址/命令缓冲器和时钟电路。存储器控制器向存储器件发送数据，地址信息，状态信息和命令信息，并从存储器件接收数据。缓冲器互连存储器件和存储器控制器。时钟电路嵌入到addr / cmd缓冲区中。时钟电路接收输入时钟，并将输出时钟输出到数据缓冲器和/或存储器件，以控制数据缓冲器和/或存储器件的时钟偏移。

9. 发明授权

US06507530B1 Weighted throttling mechanism with rank based throttling for a memory system 有权
标题翻译：用于内存系统的基于级别的节流的加权节流机制
公开(公告)号：US06507530B1
公开(公告)日：2003-01-14
申请号：US09967642
申请日：2001-09-28
申请人： Michael W. Williams , James M. Dodd , Lloyd L Pollard, II , Nitin B Gupte
发明人： Michael W. Williams , James M. Dodd , Lloyd L Pollard, II , Nitin B Gupte
IPC分类号： G11C700
CPC分类号： G11C11/4078 , G11C7/04
摘要： A memory system includes a plurality of memory device ranks. A memory controller having a connection with the plurality of memory device ranks is adapted to obtain command information being issued to one of the plurality of memory device ranks. The memory controller is also adapted to generate a power weight value based on a command type from the command information. The memory controller increments a power count of the one of the plurality of memory device ranks by the power weight value generated. The memory controller then compares the power count of the one of the plurality of memory device ranks to a threshold value set for the one of the plurality of memory device ranks. If it is determined that the power count exceeds the threshold value, the memory controller is adapted to throttle the one of the plurality of memory device ranks.
摘要翻译：存储器系统包括多个存储器件等级。具有与多个存储器装置等级的连接的存储器控制器适于获得被发布到多个存储器件等级之一的命令信息。存储器控制器还适于基于来自命令信息的命令类型来生成功率权重值。存储器控制器通过生成的功率权重值来增加多个存储器件等级中的一个的功率计数。存储器控制器然后将多个存储器件等级中的一个的功率计数与为多个存储器件等级中的一个设置的阈值进行比较。如果确定功率计数超过阈值，则存储器控制器适于调节多个存储器件等级中的一个。

10. 发明授权

US06449213B1 Memory interface having source-synchronous command/address signaling 有权
标题翻译：具有源同步命令/地址信令的存储器接口
公开(公告)号：US06449213B1
公开(公告)日：2002-09-10
申请号：US09664192
申请日：2000-09-18
申请人： James M. Dodd , Michael W. Williams , John B. Halbert , Randy M. Bonella
发明人： James M. Dodd , Michael W. Williams , John B. Halbert , Randy M. Bonella
IPC分类号： G11C800
CPC分类号： G11C7/109 , G11C5/063 , G11C7/1087 , G11C8/00 , G11C8/06
摘要： A memory interface scheme reduces propagation delay by utilizing source-synchronous signaling to transmit address/command information to memory devices. A memory module in accordance with the present invention may include an address/command buffer that samples address/command information responsive to an address/command strobe signal and then passes the address/command information to a memory device on the module. A retiming circuit may be used to control the timing of read-return data from a memory device on the module.
摘要翻译：存储器接口方案通过利用源同步信令将地址/命令信息发送到存储器件来减少传播延迟。根据本发明的存储器模块可以包括地址/命令缓冲器，其响应于地址/命令选通信号对地址/命令信息进行采样，然后将地址/命令信息传递到模块上的存储器件。可以使用重新定时电路来控制来自模块上的存储器件的读取数据的定时。

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