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1. 发明授权

US06788563B2 Sensing device for a passive matrix memory and a read method for use therewith 有权
标题翻译：无源矩阵存储器的检测装置和与其一起使用的读取方法
公开(公告)号：US06788563B2
公开(公告)日：2004-09-07
申请号：US10088096
申请日：2002-07-02
申请人： Michael Thompson , Richard Womack
发明人： Michael Thompson , Richard Womack
IPC分类号： G11C1122
CPC分类号： G11C11/22 , G11C27/026
摘要： A sensing device for reading data stored in a passive matrix memory including memory cells in the form of ferroelectric capacitors, includes an integrator circuit for sensing the current response and a device for storing and comparing two consecutive read values, one of which is a reference value. In a read method for use with the sensing device a bit line is connected to the sensing device for sensing a charge flowing therebetween and a memory cell at the crossing of the former and activated word line, whereafter two consecutive reads of the memory cell are performed and integrated over predetermined time periods in order to generate first and second read values which are compared for determining a logical value dependent on the sensed charge.
摘要翻译：用于读取存储在包括铁电电容器形式的存储单元的无源矩阵存储器中的数据的感测装置包括用于感测当前响应的积分器电路和用于存储和比较两个连续读取值的装置，其中一个读取值是参考值。在与感测装置一起使用的读取方法中，位线连接到用于感测在其间流动的电荷的感测装置和在前者和激活字线交叉处的存储器单元，然后执行存储器单元的两个连续读取并且在预定时间段内积分，以便产生第一和第二读取值，所述第一和第二读取值被比较以确定取决于感测到的电荷的逻辑值。

2. 发明申请

US20050248979A1 Non-switching pre- and post- disturb compensational pulses 失效
标题翻译：非切换前和后干扰补偿脉冲
公开(公告)号：US20050248979A1
公开(公告)日：2005-11-10
申请号：US11053905
申请日：2005-02-10
申请人： Christer Karlsson , Per Hamberg , Staffan Bjorklid , Michael Thompson , Richard Womack
发明人： Christer Karlsson , Per Hamberg , Staffan Bjorklid , Michael Thompson , Richard Womack
IPC分类号： G11C11/22 , G11C11/14
CPC分类号： G11C11/22
摘要： In a method for operating a passive matrix-addessable ferroelectric or electret memory device comprising memory cells in the form of a ferroelectric or electret thin-film polarizable memory material exhibiting hysteresis, particularly a ferroelectric or electret polymer thin film, and a first set of parallel electrodes forming word line electrodes in the device and a second set of parallel electrodes forming bit lines in the device, the word lines being oriented orthogonally to the bit lines, such that the word lines and bit lines are in direct contact with the memory cells, which can be set to either of two polarization states or switched between these by applying a switching voltage larger than a coercive voltage of the memory material between a word line and a bit line, a voltage pulse protocol with at least one disturb generating operation cycle is applied for switching selected addressed cells to determined polarization state. The voltage pulse protocol further comprises a pre-disturb and/or post-disturb cycle before and after the disturb generating operation cycle respectively in order to minimize the effect of disturb voltages on non-addressed memory cells, when such voltages are generated thereto in the operation cycle when it is applied for either a write or read operation.
摘要翻译：在一种用于操作无源矩阵可加性铁电或驻极体存储器件的方法中，该器件包括呈现滞后性的铁电或驻极体薄膜可极化存储材料形式的存储单元，特别是铁电或驻极体聚合物薄膜，以及第一组平行在器件中形成字线电极的电极和在器件中形成位线的第二组并联电极，字线与位线正交定向，使得字线和位线与存储器单元直接接触，通过施加大于字线和位线之间的存储材料的矫顽电压的开关电压，可将其设置为两个极化状态中的任一个或在其之间切换，具有至少一个干扰产生操作周期的电压脉冲协议是用于将所选择的寻址单元切换到确定的极化状态。电压脉冲协议还包括在干扰产生操作周期之前和之后的预先干扰和/或干扰后周期，以便最小化干扰电压对非寻址存储器单元的影响，当在其中产生这样的电压时当它被应用于写入或读取操作时的操作周期。

3. 发明授权

US5923583A Ferromagnetic memory based on torroidal elements 失效
标题翻译：基于环形元件的铁磁记忆
公开(公告)号：US5923583A
公开(公告)日：1999-07-13
申请号：US956405
申请日：1997-10-23
申请人： Richard Womack
发明人： Richard Womack
IPC分类号： G11C11/15 , G11C11/16 , G11C13/00
CPC分类号： G11C11/15 , G11C11/16
摘要： A magnetic memory cell for storing binary encoded data and a memory constructed from these memory cells. The memory cell stores information in the direction of magnetization of a torroidal layer of magnetic material. The memory cell is constructed from a structure having a top electrode, a soft layer which includes a planar sheet of a soft magnetic material, a hard layer which includes a planar sheet of a hard magnetic material, and a bottom electrode, the soft and hard layers being sandwiched between the top and bottom electrodes. The various layers are torroids. The hard and soft materials are chosen such that the magnitude to the magnetic field needed to magnetize the hard magnetic material is greater than the magnitude of the magnetic field needed to magnetize the soft magnetic material. The memory cell also includes a write circuit that generates first and second magnetic fields. The first is generated by passing a current between the top and bottom electrodes of a memory cell in a direction that determines the data state to be written. The magnitudes of the first and second magnetic fields are less than that needed to magnetize the soft magnetic material. However, the magnitude of the vector sum of the first and second magnetic fields is greater than the magnetic field needed to magnetize the soft magnetic material but less than the magnetic field needed to magnetize the hard magnetic material.
摘要翻译：用于存储二进制编码数据的磁存储单元和由这些存储单元构成的存储器。存储单元存储磁性材料的环形层的磁化方向的信息。存储单元由具有顶部电极，软层的软层构成，该软层包括软磁性材料的平面片，包括硬磁性材料的平板的硬质层和底部电极，软和硬层被夹在顶部和底部电极之间。各层是电筒。选择硬和软材料使得磁化磁性材料所需的磁场的大小大于磁化磁性材料所需的磁场的大小。存储单元还包括产生第一和第二磁场的写入电路。第一种是通过在确定要写入的数据状态的方向上通过存储器单元的顶部和底部电极之间的电流来产生的。第一和第二磁场的大小小于磁化软磁材料所需的大小。然而，第一和第二磁场的矢量和的大小大于磁化磁性材料但是小于磁化磁性材料所需的磁场所需的磁场。

4. 发明申请

US20060062042A1 Read method and sensing device 有权
标题翻译：读取方法和感测装置
公开(公告)号：US20060062042A1
公开(公告)日：2006-03-23
申请号：US11231895
申请日：2005-09-22
申请人： Christer Karlsson , Niklas Lovgren , Richard Womack
发明人： Christer Karlsson , Niklas Lovgren , Richard Womack
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C7/062
摘要： In a method for reading the memory cell in a passive matrix-addressable ferroelectric or electret memory array with memory cells in the form of ferroelectric or electret capacitors, sensing means connected to the bit line of memory cell is activated in order to initiate a charge measurement and a first charge value is registered, whereafter a switching voltage is applied to the memory cell and a second charge value is registered. A readout value is obtained by subtracting the first charge value from the second charge value. A sensing device for performing the method of the invention comprises a first amplifier stage (A1) with an integrator circuit (715) and connected with a second amplifier stage (A2) following the first amplifier stage and with an integrator circuit (725), and a sampling capacitor (720) connected between an output (716) of the first amplifier stage (A1) and an input (722) of the second amplifier stage (A2).
摘要翻译：在以铁电或驻极体电容器的形式存储存储单元的无源矩阵寻址铁电或驻极体存储器阵列中读取存储单元的方法中，连接到存储器单元的位线的感测装置被激活以启动电荷测量并且注册第一充电值，之后将开关电压施加到存储单元并且登记第二充电值。通过从第二充电值减去第一充电值获得读出值。用于执行本发明的方法的感测装置包括：具有积分器电路（715）的第一放大器级（A 1）和与第一放大器级之后的第二放大级（A 2）连接的积分器电路（725），以及连接在第一放大级（A 1）的输出（716）和第二放大级（A 2）的输入端（722）之间的采样电容器（720）。

5. 发明授权

US5872739A Sense amplifier for low read-voltage memory cells 失效
标题翻译：用于低读取电压存储单元的读出放大器
公开(公告)号：US5872739A
公开(公告)日：1999-02-16
申请号：US841905
申请日：1997-04-17
申请人： Richard Womack
发明人： Richard Womack
IPC分类号： G11C7/06 , G11C7/14 , G11C7/02
CPC分类号： G11C7/06 , G11C11/2273 , G11C7/14
摘要： A sense amplifier for comparing the resistance of a reference cell connected to a reference bit line to the resistance of a data cell connected to a data bit line. The amplifier includes a first terminal for connecting the sense amplifier to the reference bit line and a second terminal for connecting the sense amplifier to the data bit line. A reference current to voltage amplifier is connected to the first terminal for generating a reference voltage related to the current flowing through the reference bit line and for maintaining the first terminal at a reference potential when the current flowing through the reference bit line is less than a first current value. A data current to voltage amplifier is connected to the second terminal for generating a data voltage related to the current flowing through the data bit line and for maintaining the second terminal at the reference potential when the current flowing through the data bit line is less than a second current value. A comparitor compares the reference and data voltages. The data current to voltage amplifier includes an operational amplifier for measuring the difference between a potential on a first conductor and the potential on the data bit line. The operational amplifier allows the reference potential to be set at a lower voltage than is available in prior art designs. The invention utilizes a capacitive dividing scheme for pre-charging the bit lines prior to connecting the sense amplifier.
摘要翻译：读出放大器，用于将连接到参考位线的参考单元的电阻与连接到数据位线的数据单元的电阻进行比较。放大器包括用于将读出放大器连接到参考位线的第一端子和用于将读出放大器连接到数据位线的第二端子。参考电流到电压放大器连接到第一端子，用于产生与流过参考位线的电流相关的参考电压，并且当流过参考位线的电流小于一个时，将第一端子保持在参考电位第一个当前值。数据电流到电压放大器连接到第二端子，用于产生与流过数据位线的电流相关的数据电压，并且当流过数据位线的电流小于一个时，将第二端子保持在参考电位第二个当前值。比较器比较参考电压和数据电压。数据电流到电压放大器包括用于测量第一导体上的电位与数据位线上的电位之间的差的运算放大器。运算放大器允许将参考电位设置在比现有技术设计中更低的电压。本发明利用电容分配方案在连接读出放大器之前对位线进行预充电。

6. 发明授权

US5789775A High density memory and double word ferroelectric memory cell for constructing the same 失效
标题翻译：高密度存储器和双字铁电存储单元构造相同
公开(公告)号：US5789775A
公开(公告)日：1998-08-04
申请号：US592629
申请日：1996-01-26
申请人： Joseph T. Evans, Jr. , Richard Womack
发明人： Joseph T. Evans, Jr. , Richard Womack
IPC分类号： G11C11/22 , G11C11/56 , H01L27/115 , H01L29/792
CPC分类号： H01L27/11502 , G11C11/22 , G11C11/5657
摘要： A high density non-volatile ferroelectric-based memory based on a ferroelectric FET operated in a two terminal write mode. Storage words may be constructed either from one or two bit storage cells based on a ferroelectric FET. A memory using either the one or two bit storage cells includes a plurality of word storage cells organized into a rectangular array including a plurality of columns and rows. Each of the word storage cells includes N single bit memory cells. Each of the single bit memory cells includes a pass transistor and a ferroelectric storage element. All of the gate electrodes in the circuit are connected to a common gate electrode, and all of the source electrodes are connected to a common source electrode. If the memory is built from two bit storage cells as described herein, each storage cell is one half of a two bit storage cell. All of the common source electrodes in each one of the columns are connected electrically to a column electrode corresponding to that column and all of the pass gates in each of the rows are connected electrically to a row electrode corresponding to that row. A memory address includes a plurality of bits divided into first and second groups of bits. The column and row electrodes are selected by the first and second groups of bits, respectively.
摘要翻译：基于以两端写入模式操作的铁电FET的高密度非易失性铁电体存储器。存储字可以由基于铁电FET的一个或两个位存储单元构成。使用一个或两个位存储单元的存储器包括组织成包括多个列和行的矩形阵列的多个字存储单元。每个字存储单元包括N个单位存储单元。单个位存储器单元中的每一个包括传输晶体管和铁电存储元件。电路中的所有栅电极连接到公共栅电极，并且所有源极连接到公共源电极。如果这里描述的存储器是由两位存储单元构建的，则每个存储单元是两位存储单元的一半。每列中的所有公共源电极电连接到对应于该列的列电极，并且每行中的所有通孔都电连接到与该行对应的行电极。存储器地址包括分成第一和第二组位的多个位。列和行电极分别由第一和第二组位选择。

7. 发明申请

US20060002178A1 Cross-point ferroelectric memory that reduces the effects of bit line to word line shorts 有权
标题翻译：交叉点铁电存储器，可减少位线对字线短路的影响
公开(公告)号：US20060002178A1
公开(公告)日：2006-01-05
申请号：US10884762
申请日：2004-07-01
申请人： Richard Womack
发明人： Richard Womack
IPC分类号： G11C11/00
CPC分类号： G11C29/832 , G11C11/22 , G11C29/04
摘要： A memory constructed from a dielectric layer sandwiched between a plurality of word conductors and a plurality of bit line conductors is disclosed. The dielectric layer includes a layer of ferroelectric material, and has first and second surfaces. The word conductors are located on the first surface. Each word conductor is connected to a corresponding word line driving circuit. The bit line conductors are located on the second surface. Each bit line conductor is connected to a corresponding bit line driving circuit and a corresponding sense amplifier by one or more disconnect switches. A disconnect switch is set to an open state if the bit line conductor connected to that disconnect switch is shorted to one of the word conductors.
摘要翻译：公开了一种由夹在多个字导体和多个位线导体之间的电介质层构成的存储器。电介质层包括铁电材料层，并且具有第一表面和第二表面。字导体位于第一表面上。每个字导体连接到相应的字线驱动电路。位线导体位于第二表面上。每个位线导体通过一个或多个断开开关连接到对应的位线驱动电路和对应的读出放大器。如果连接到该断开开关的位线导体短接到一个字导体，则断开开关设置为断开状态。

8. 发明授权

US5864498A Ferromagnetic memory using soft magnetic material and hard magnetic material 失效
标题翻译：铁磁记忆采用软磁材料和硬磁材料
公开(公告)号：US5864498A
公开(公告)日：1999-01-26
申请号：US943080
申请日：1997-10-01
申请人： Richard Womack
发明人： Richard Womack
IPC分类号： G11C11/15
CPC分类号： G11C11/15
摘要： A magnetic memory cell for storing binary encoded data and a memory constructed from these memory cells. A memory cell according to the present invention stores information in the direction of magnetization of a layer of magnetic material. The memory cell is constructed from a structure having a top electrode, a soft layer which includes a planar sheet of a soft magnetic material, a hard layer which includes a planar sheet of a hard magnetic material, and a bottom electrode, the soft and hard layers being sandwiched between the top and bottom electrodes. The hard and soft materials are chosen such that the magnitude to the magnetic field needed to magnetize the hard magnetic material is greater than the magnitude of the magnetic field needed to magnetize the soft magnetic material. The memory cell also includes a write circuit that generates first and second magnetic fields. The first and second magnetic fields are parallel to the planar sheet of the soft layer. The magnitudes of the first and second magnetic fields are less than that needed to magnetize the soft magnetic material. However, the magnitude of the vector sum of the first and second magnetic fields is greater than the magnetic field needed to magnetize the soft magnetic material but less than the magnetic field needed to magnetize the hard magnetic material.
摘要翻译：用于存储二进制编码数据的磁存储单元和由这些存储单元构成的存储器。根据本发明的存储单元按照磁性材料层的磁化方向存储信息。存储单元由具有顶部电极，软层的软层构成，该软层包括软磁性材料的平面片，包括硬磁性材料的平板的硬质层和底部电极，软和硬层被夹在顶部和底部电极之间。选择硬和软材料使得磁化磁性材料所需的磁场的大小大于磁化磁性材料所需的磁场的大小。存储单元还包括产生第一和第二磁场的写入电路。第一和第二磁场平行于软层的平面片。第一和第二磁场的大小小于磁化软磁材料所需的大小。然而，第一和第二磁场的矢量和的大小大于磁化磁性材料但是小于磁化磁性材料所需的磁场所需的磁场。

9. 发明授权

US5804850A Ferroelectric based capacitor cell for use in memory systems 失效
标题翻译：用于存储器系统的基于铁电的电容器单元
公开(公告)号：US5804850A
公开(公告)日：1998-09-08
申请号：US633853
申请日：1996-04-16
申请人： Joseph T. Evans, Jr. , Richard Womack
发明人： Joseph T. Evans, Jr. , Richard Womack
IPC分类号： H01L21/02 , H01L21/8246 , H01L27/115 , H01L29/92 , H01L31/119
CPC分类号： H01L27/11502 , H01L27/11585 , H01L27/1159 , H01L28/55 , H01L28/60 , H01L28/75
摘要： A ferroelectric based capacitor structure and method for making the same. The capacitor includes a bottom electrode having a layer of Pt in contact with a first layer of an ohmic material. The capacitor dielectric is constructed from a layer of lead zirconium titanate doped with an element having an oxidation state greater than +4. The top electrode of the capacitor is constructed from a second layer of ohmic material in contact with a layer of Pt. The preferred ohmic material is LSCO; although RuO.sub.2 may also be utilized. The capacitor is preferably constructed over the drain of an FET such that the bottom electrode of the capacitor is connected to the drain of the FET. The resulting capacitor structure has both low imprint and low fatigue.
摘要翻译：一种铁电体电容器结构及其制造方法。电容器包括具有与第一欧姆材料层接触的Pt层的底部电极。电容器电介质由掺杂有大于+4的氧化态的元素的钛酸铅锆层构成。电容器的顶部电极由与Pt层接触的第二层欧姆材料构成。优选的欧姆材料是LSCO; 尽管也可以使用RuO 2。电容器优选地构造在FET的漏极上，使得电容器的底部电极连接到FET的漏极。所得到的电容器结构具有低压印和低疲劳。

10. 发明授权

US07345906B2 Read method and sensing device 有权
标题翻译：读取方法和感测装置
公开(公告)号：US07345906B2
公开(公告)日：2008-03-18
申请号：US11231895
申请日：2005-09-22
申请人： Christer Karlsson , Niklas Lövgren , Richard Womack
发明人： Christer Karlsson , Niklas Lövgren , Richard Womack
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C7/062
摘要： In a method for reading the memory cell in a passive matrix-addressable ferroelectric or electret memory array with memory cells in the form of ferroelectric or electret capacitors, sensing means connected to the bit line of memory cell is activated in order to initiate a charge measurement and a first charge value is registered, whereafter a switching voltage is applied to the memory cell and a second charge value is registered. A readout value is obtained by subtracting the first charge value from the second charge value. A sensing device for performing an embodiment of the method comprises a first amplifier stage with an integrator circuit and connected with a second amplifier stage (A2) following the first amplifier stage and with an integrator circuit, and a sampling capacitor connected between an output of the first amplifier stage and an input of the second amplifier stage.
摘要翻译：在以铁电或驻极体电容器的形式存储存储单元的无源矩阵寻址铁电或驻极体存储器阵列中读取存储单元的方法中，连接到存储器单元的位线的感测装置被激活以启动电荷测量并且注册第一充电值，之后将开关电压施加到存储单元并且登记第二充电值。通过从第二充电值减去第一充电值获得读出值。用于执行该方法的实施例的感测装置包括具有积分器电路并与第一放大器级之后的第二放大器级（A 2）连接的第一放大器级和与积分器电路连接的采样电容器，以及连接在第一放大器级和第二放大级的输入。

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