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1. 发明授权

US5804850A Ferroelectric based capacitor cell for use in memory systems 失效
标题翻译：用于存储器系统的基于铁电的电容器单元
公开(公告)号：US5804850A
公开(公告)日：1998-09-08
申请号：US633853
申请日：1996-04-16
申请人： Joseph T. Evans, Jr. , Richard Womack
发明人： Joseph T. Evans, Jr. , Richard Womack
IPC分类号： H01L21/02 , H01L21/8246 , H01L27/115 , H01L29/92 , H01L31/119
CPC分类号： H01L27/11502 , H01L27/11585 , H01L27/1159 , H01L28/55 , H01L28/60 , H01L28/75
摘要： A ferroelectric based capacitor structure and method for making the same. The capacitor includes a bottom electrode having a layer of Pt in contact with a first layer of an ohmic material. The capacitor dielectric is constructed from a layer of lead zirconium titanate doped with an element having an oxidation state greater than +4. The top electrode of the capacitor is constructed from a second layer of ohmic material in contact with a layer of Pt. The preferred ohmic material is LSCO; although RuO.sub.2 may also be utilized. The capacitor is preferably constructed over the drain of an FET such that the bottom electrode of the capacitor is connected to the drain of the FET. The resulting capacitor structure has both low imprint and low fatigue.
摘要翻译：一种铁电体电容器结构及其制造方法。电容器包括具有与第一欧姆材料层接触的Pt层的底部电极。电容器电介质由掺杂有大于+4的氧化态的元素的钛酸铅锆层构成。电容器的顶部电极由与Pt层接触的第二层欧姆材料构成。优选的欧姆材料是LSCO; 尽管也可以使用RuO 2。电容器优选地构造在FET的漏极上，使得电容器的底部电极连接到FET的漏极。所得到的电容器结构具有低压印和低疲劳。

2. 发明授权

US6117688A Method for constructing ferroelectric based capacitor for use in memory systems 失效
标题翻译：用于存储系统中使用的铁电电容器的方法
公开(公告)号：US6117688A
公开(公告)日：2000-09-12
申请号：US75011
申请日：1998-05-08
申请人： Joseph T. Evans, Jr. , Richard Womack
发明人： Joseph T. Evans, Jr. , Richard Womack
IPC分类号： H01L21/02 , H01L21/8246 , H01L27/115 , H01L29/92 , H01L21/8242 , H01G7/06
CPC分类号： H01L27/11502 , H01L27/11585 , H01L27/1159 , H01L28/55 , H01L28/60 , H01L28/75
摘要： A ferroelectric based capacitor structure and method for making the same. The capacitor includes a bottom electrode having a layer of Pt in contact with a first layer of an ohmic material. The capacitor dielectric is constructed from a layer of lead zirconium titanate doped with an element having an oxidation state greater than +4. The top electrode of the capacitor is constructed from a second layer of ohmic material in contact with a layer of Pt. The preferred ohmic material is LSCO; although RuO.sub.2 may also be utilized. The capacitor is preferably constructed over the drain of a FET such that the bottom electrode of the capacitor is connected to the drain of the FET. The resulting capacitor structure has both low imprint and low fatigue.
摘要翻译：一种铁电体电容器结构及其制造方法。电容器包括具有与第一欧姆材料层接触的Pt层的底部电极。电容器电介质由掺杂有大于+4的氧化态的元素的钛酸铅锆层构成。电容器的顶部电极由与Pt层接触的第二层欧姆材料构成。优选的欧姆材料是LSCO; 尽管也可以使用RuO 2。电容器优选地构造在FET的漏极上，使得电容器的底部电极连接到FET的漏极。所得到的电容器结构具有低压印和低疲劳。

3. 发明授权

US5757042A High density ferroelectric memory with increased channel modulation and double word ferroelectric memory cell for constructing the same 失效
标题翻译：高密度铁电存储器具有增加的通道调制和双字铁电存储单元的构造
公开(公告)号：US5757042A
公开(公告)日：1998-05-26
申请号：US663675
申请日：1996-06-14
申请人： Joseph T. Evans, Jr. , Richard Womack
发明人： Joseph T. Evans, Jr. , Richard Womack
IPC分类号： G11C11/22 , H01L27/115 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L27/11502 , G11C11/22 , H01L29/78391
摘要： A memory based on a ferroelectric FET, the ferroelectric FET includes a gate electrode, a layer of ferroelectric material, layer of semiconducting material, a source electrode and a drain electrode. The layer of ferroelectric material is sandwiched between the gate electrode and the layer of semiconducting material, the source and drain electrodes being in contact with the layer of semiconducting material and spaced apart from one another. The memory includes a circuit for setting the ferroelectric FET to one of two states. The first state is set by applying a first voltage to the source and drain electrodes and a second voltage to the gate electrode. The second state is set by applying a third voltage to the gate and drain electrodes and fourth voltage to the source electrode. This arrangement reduces the number of pass transistors needed per ferroelectric FET to one plus a simple pulsing circuit that must be included with each word of memory.
摘要翻译：基于铁电FET的存储器，铁电FET包括栅电极，铁电材料层，半导体材料层，源电极和漏电极。铁电材料层夹在栅电极和半导体材料层之间，源电极和漏电极与半导体材料层接触并彼此间隔开。存储器包括用于将铁电FET设置为两种状态之一的电路。通过向源极和漏极施加第一电压并将第二电压施加到栅电极来设定第一状态。通过向栅极和漏极施加第三电压并将第四电压施加到源电极来设定第二状态。这种布置将每个铁电FET所需的通过晶体管的数量减少到一个必须包含在每个字存储器中的简单脉冲电路。

4. 发明授权

US5789775A High density memory and double word ferroelectric memory cell for constructing the same 失效
标题翻译：高密度存储器和双字铁电存储单元构造相同
公开(公告)号：US5789775A
公开(公告)日：1998-08-04
申请号：US592629
申请日：1996-01-26
申请人： Joseph T. Evans, Jr. , Richard Womack
发明人： Joseph T. Evans, Jr. , Richard Womack
IPC分类号： G11C11/22 , G11C11/56 , H01L27/115 , H01L29/792
CPC分类号： H01L27/11502 , G11C11/22 , G11C11/5657
摘要： A high density non-volatile ferroelectric-based memory based on a ferroelectric FET operated in a two terminal write mode. Storage words may be constructed either from one or two bit storage cells based on a ferroelectric FET. A memory using either the one or two bit storage cells includes a plurality of word storage cells organized into a rectangular array including a plurality of columns and rows. Each of the word storage cells includes N single bit memory cells. Each of the single bit memory cells includes a pass transistor and a ferroelectric storage element. All of the gate electrodes in the circuit are connected to a common gate electrode, and all of the source electrodes are connected to a common source electrode. If the memory is built from two bit storage cells as described herein, each storage cell is one half of a two bit storage cell. All of the common source electrodes in each one of the columns are connected electrically to a column electrode corresponding to that column and all of the pass gates in each of the rows are connected electrically to a row electrode corresponding to that row. A memory address includes a plurality of bits divided into first and second groups of bits. The column and row electrodes are selected by the first and second groups of bits, respectively.
摘要翻译：基于以两端写入模式操作的铁电FET的高密度非易失性铁电体存储器。存储字可以由基于铁电FET的一个或两个位存储单元构成。使用一个或两个位存储单元的存储器包括组织成包括多个列和行的矩形阵列的多个字存储单元。每个字存储单元包括N个单位存储单元。单个位存储器单元中的每一个包括传输晶体管和铁电存储元件。电路中的所有栅电极连接到公共栅电极，并且所有源极连接到公共源电极。如果这里描述的存储器是由两位存储单元构建的，则每个存储单元是两位存储单元的一半。每列中的所有公共源电极电连接到对应于该列的列电极，并且每行中的所有通孔都电连接到与该行对应的行电极。存储器地址包括分成第一和第二组位的多个位。列和行电极分别由第一和第二组位选择。

5. 发明授权

US06225654B1 Static ferrolectric memory transistor having improved data retention 失效
标题翻译：静态铁电存储晶体管具有改进的数据保留
公开(公告)号：US06225654B1
公开(公告)日：2001-05-01
申请号：US08640572
申请日：1996-05-01
申请人： Joseph T. Evans, Jr. , William L. Warren , Bruce A. Tuttle
发明人： Joseph T. Evans, Jr. , William L. Warren , Bruce A. Tuttle
IPC分类号： B05D512
CPC分类号： H01L29/516 , G11C11/223
摘要： An improved ferroelectric FET structure in which the ferroelectric layer is doped to reduce retention loss. A ferroelectric FET according to the present invention includes a semiconductor layer having first and second contacts thereon, the first and second contacts being separated from one another. The ferroelectric FET also includes a bottom electrode and a ferroelectric layer which is sandwiched between the semiconductor layer and the bottom electrode. The ferroelectric layer is constructed from a perovskite structure of the chemical composition ABO3 wherein the B site comprises first and second elements and a dopant element that has an oxidation state greater than +4 in sufficient concentration to impede shifts in the resistance measured between the first and second contacts with time. The ferroelectric FET structure preferably comprises Pb in the A-site. The first and second elements are preferably Zr and Ti, respectively. The preferred B-site dopants are Niobium, Tantalum, and Tungsten at concentrations between 1% and 8%.
摘要翻译：改进的铁电FET结构，其中掺杂铁电层以减少保留损耗。根据本发明的铁电FET包括其上具有第一和第二触点的半导体层，第一和第二触点彼此分离。铁电FET还包括夹在半导体层和底部电极之间的底部电极和铁电体层。铁电层由化学组成ABO 3的钙钛矿结构构成，其中B位置包含第一和第二元素以及具有足够浓度的大于+4的氧化态的掺杂剂元素，以阻止在第一和第二元素之间测量的电阻的偏移第二次接触时间。铁电FET结构优选在A位置包含Pb。第一和第二元素分别优选为Zr和Ti。优选的B位掺杂剂是浓度在1％和8％之间的铌，钽和钨。

6. 发明授权

US06194751B1 Ferroelectric based memory devices utilizing low Curie point ferroelectrics and encapsulation 失效
标题翻译：采用低居里点铁电体和封装的铁电存储器件
公开(公告)号：US06194751B1
公开(公告)日：2001-02-27
申请号：US09015373
申请日：1998-01-29
申请人： Joseph T. Evans, Jr.
发明人： Joseph T. Evans, Jr.
IPC分类号： H01L2976
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/75 , H01L29/516
摘要： A ferroelectric memory cell for storing information. The information is stored in the remnant polarization of a ferroelectric dielectric layer by setting the direction of the remnant polarization. The ferroelectric memory cell is designed to store the information at a temperature less than a first temperature. The memory cell includes top and bottom contacts that sandwich the dielectric layer which includes a ferroelectric material having a Curie point greater than the first temperature and less than 400° C. The dielectric layer is encapsulated in an oxygen impermeable material such that the encapsulating layer prevents oxygen from entering or leaving the dielectric layer. One of the contacts typically includes a platinum electrode. The other contact may include a similar electrode or a semiconductor layer having electrodes spaced apart thereon.
摘要翻译：用于存储信息的铁电存储单元。通过设定残留极化的方向，将信息存储在铁电介质层的剩余极化中。铁电存储器单元被设计成在小于第一温度的温度下存储信息。存储单元包括夹住电介质层的顶部和底部触点，该电介质层包括具有大于第一温度且小于400℃的居里点的铁电材料。介电层被封装在不透氧材料中，使得封装层防止氧气进入或离开电介质层。触点之一通常包括铂电极。另一个接触可以包括具有间隔开的电极的类似电极或半导体层。

7. 发明授权

US5679969A Ferroelectric based capacitor for use in memory systems and method for fabricating the same 失效
标题翻译：用于存储器系统的铁电电容器及其制造方法
公开(公告)号：US5679969A
公开(公告)日：1997-10-21
申请号：US661597
申请日：1996-06-11
申请人： Joseph T. Evans, Jr. , Richard H. Womack
发明人： Joseph T. Evans, Jr. , Richard H. Womack
IPC分类号： H01L21/02 , H01L21/8246 , H01L27/115 , H01L29/92 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/62
CPC分类号： H01L27/11502 , H01L27/11585 , H01L27/1159 , H01L28/55 , H01L28/60 , H01L28/75
摘要： A ferroelectric based capacitor structure and method for making the same. The capacitor includes a bottom electrode having a layer of Pt in contact with a first layer of an ohmic material. The capacitor dielectric is constructed from a layer of lead zirconium titanate doped with an element having an oxidation state greater than +4. The top electrode of the capacitor is constructed from a second layer of ohmic material in contact with a layer of Pt. The preferred ohmic material is LSCO; although RuO.sub.2 may also be utilized. The capacitor is preferably constructed over the drain of an FET such that the bottom electrode of the capacitor is connected to the drain of the FET. The resulting capacitor structure has both low imprint and low fatigue.
摘要翻译：一种铁电体电容器结构及其制造方法。电容器包括具有与第一欧姆材料层接触的Pt层的底部电极。电容器电介质由掺杂有大于+4的氧化态的元素的钛酸铅锆层构成。电容器的顶部电极由与Pt层接触的第二层欧姆材料构成。优选的欧姆材料是LSCO; 尽管也可以使用RuO 2。电容器优选地构造在FET的漏极上，使得电容器的底部电极连接到FET的漏极。所得到的电容器结构具有低压印和低疲劳。

8. 发明授权

US5453347A Method for constructing ferroelectric capacitors on integrated circuit substrates 失效
标题翻译：在集成电路基板上构造铁电电容器的方法
公开(公告)号：US5453347A
公开(公告)日：1995-09-26
申请号：US255066
申请日：1994-06-07
申请人： Jeff A. Bullington , Carl E. Montross, Jr. , Joseph T. Evans, Jr.
发明人： Jeff A. Bullington , Carl E. Montross, Jr. , Joseph T. Evans, Jr.
IPC分类号： H01L21/02 , G03F7/26 , H01L21/00
CPC分类号： H01L28/60
摘要： A ferroelectric capacitor and method for making the same are disclosed. The ferroelectric capacitor may be constructed on a silicon substrate such as SiO.sub.2 or Si.sub.3 N.sub.4. The ferroelectric capacitor includes a bottom electrode, a layer of ferroelectric material, and a top electrode. The bottom electrode is constructed from a layer of platinum which is bonded to the silicon substrate by a layer of metallic oxide. The metallic oxide does not diffuse into the platinum; hence, a thinner layer of platinum may be utilized for the electrode. This reduces the vertical height of the capacitor and other problems associated with diffusion of the layer used to bond the bottom electrode to the substrate surface.
摘要翻译：公开了一种铁电电容器及其制造方法。铁电电容器可以构造在诸如SiO 2或Si 3 N 4的硅衬底上。铁电体电容器包括底部电极，铁电体层和顶部电极。底部电极由铂层构成，其通过一层金属氧化物结合到硅衬底。金属氧化物不会扩散到铂中; 因此，可以将较薄的铂层用于电极。这降低了电容器的垂直高度以及与用于将底部电极结合到衬底表面的层的扩散相关的其它问题。

9. 发明授权

US4654586A Digital phase meter apparatus 失效
标题翻译：数字式相位计仪表
公开(公告)号：US4654586A
公开(公告)日：1987-03-31
申请号：US742826
申请日：1985-06-10
申请人： Joseph T. Evans, Jr. , Stacy M. Munechika , Michael C. Norris , Alisa M. Hren , Kevin M. Heck , Suzanne M. Zulka
发明人： Joseph T. Evans, Jr. , Stacy M. Munechika , Michael C. Norris , Alisa M. Hren , Kevin M. Heck , Suzanne M. Zulka
IPC分类号： G01R25/08
CPC分类号： G01R25/08
摘要： A digital phase meter to measure the phase difference between an input signal and a reference signal and output this phase information in the form of an eight bit number. The input signal and the reference signal, which are sinusoidal, are conditioned to a more defined leading edge by a high speed differential voltage comparator and a dual/differential line receiver. A series of uniquely configured D flip-flops are used to detect the leading edge of both the signal input and the reference input. An AND gate then acts as a switch that is activated on the leading edge of the signal input. The time interval between the two positive leading edges of the input signal and reference signal specifies the phase difference. The AND gate is in the high state for this duration. The phase difference is converted into an 8-bit binary number via two 4-bit cascaded counters. The high output of the AND gate is used to enable the counters for the duration of the phase difference.
摘要翻译：数字相位计，用于测量输入信号和参考信号之间的相位差，并以8位数字的形式输出该相位信息。正弦曲线的输入信号和参考信号由高速差分电压比较器和双路/差分线路接收器调节到更确定的前沿。一系列独特配置的D触发器用于检测信号输入和参考输入的前沿。然后，与门作为在信号输入的前沿被激活的开关。输入信号和参考信号的两个正前沿之间的时间间隔指定相位差。在这个持续时间内，与门处于高电平状态。通过两个4位级联计数器将相位差转换为8位二进制数。与门的高输出用于在相位差的持续时间内使能计数器。

10. 发明授权

US08787063B2 Analog memories utilizing ferroelectric capacitors 有权
标题翻译：使用铁电电容器的模拟存储器
公开(公告)号：US08787063B2
公开(公告)日：2014-07-22
申请号：US13559531
申请日：2012-07-26
申请人： Joseph T. Evans, Jr. , Calvin B. Ward
发明人： Joseph T. Evans, Jr. , Calvin B. Ward
IPC分类号： G11C11/22
CPC分类号： G11C11/221 , G11C11/2259 , G11C11/2273 , G11C11/2275 , G11C11/2293 , G11C11/5657 , G11C27/005
摘要： A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes a value determined by a data value having at least three states to be stored in the ferroelectric memory cell currently connected to the write line. A read circuit measures the charge stored in the ferroelectric memory cell currently connected to the read line.
摘要翻译：公开了具有多个铁电存储单元的铁电存储器，每个强电介质存储单元包括铁电电容器。铁电存储器包括读写线和多个铁电存储器单元选择总线，每个铁电存储单元相应的一个选择总线。每个铁电存储单元包括用于响应于与该铁电存储单元相对应的强电介质存储单元选择总线上的信号而分别将铁电存储单元连接到读取线和写入线的第一和第二栅极。写入电路使由具有至少三个状态的数据值确定的值存储在当前连接到写入线的铁电存储单元中。读取电路测量存储在当前连接到读取线的铁电存储器单元中的电荷。

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