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1. 发明授权

US07160775B2 Method of discharging a semiconductor device 有权
标题翻译：放电半导体器件的方法
公开(公告)号：US07160775B2
公开(公告)日：2007-01-09
申请号：US10912825
申请日：2004-08-06
申请人： Erwin J. Prinz , Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Robert F. Steimle , Craig T. Swift , Bruce E. White
发明人： Erwin J. Prinz , Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Robert F. Steimle , Craig T. Swift , Bruce E. White
IPC分类号： H01L21/336
CPC分类号： B82Y10/00 , G11C16/0475 , G11C16/14 , G11C2216/06 , H01L21/28273 , H01L21/28282 , H01L29/42332
摘要： In one embodiment, a method for discharging a semiconductor device includes providing a semiconductor substrate, forming a hole blocking dielectric layer over the semiconductor substrate, forming nanoclusters over the hole blocking dielectric layer, forming a charge trapping layer over the nanoclusters, and applying an electric field to the nanoclusters to discharge the semiconductor device. Applying the electric field may occur while applying ultraviolet (UV) light. In one embodiment, the hole blocking dielectric layer comprises forming the hole blocking dielectric layer having a thickness greater than approximately 50 Angstroms.
摘要翻译：在一个实施例中，一种用于放电半导体器件的方法包括提供半导体衬底，在半导体衬底上形成空穴阻挡电介质层，在空穴阻挡介电层上形成纳米团簇，在纳米团簇上形成电荷俘获层，并施加电场到纳米团簇放电半导体器件。施加紫外线（UV）光时可能会发生电场。在一个实施例中，空穴阻挡介电层包括形成厚度大于约50埃的空穴阻挡介电层。

2. 发明授权

US07800164B2 Nanocrystal non-volatile memory cell and method therefor 有权
标题翻译：纳米晶体非挥发性记忆体及其方法
公开(公告)号：US07800164B2
公开(公告)日：2010-09-21
申请号：US12397849
申请日：2009-03-04
申请人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
发明人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
IPC分类号： H01L29/792
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L29/513 , H01L29/7881 , Y10S977/773
摘要： A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.
摘要翻译：一种形成半导体器件的方法包括在半导体衬底上形成第一电介质层，在第一介电层上形成多个离散存储元件，热氧化多个离散的存储元件，以在多个离散存储器上形成第二电介质元件，并且在所述第二介电层上形成栅电极，其中所述栅电极的重要部分位于所述多个离散存储元件的对之间。在一个实施例中，栅电极的部分位于离散存储元件之间的空间中并且延伸到空间深度的一半以上。

3. 发明授权

US07517747B2 Nanocrystal non-volatile memory cell and method therefor 有权
标题翻译：纳米晶体非挥发性记忆体及其方法
公开(公告)号：US07517747B2
公开(公告)日：2009-04-14
申请号：US11530053
申请日：2006-09-08
申请人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
发明人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
IPC分类号： H01L21/8238
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L29/513 , H01L29/7881 , Y10S977/773
摘要： A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.
摘要翻译：一种形成半导体器件的方法包括在半导体衬底上形成第一电介质层，在第一介电层上形成多个离散存储元件，热氧化多个离散的存储元件，以在多个离散存储器上形成第二电介质元件，并且在所述第二介电层上形成栅电极，其中所述栅电极的重要部分位于所述多个离散存储元件的对之间。在一个实施例中，栅电极的部分位于离散存储元件之间的空间中并且延伸到空间深度的一半以上。

4. 发明申请

US20080121967A1 NANOCRYSTAL NON-VOLATILE MEMORY CELL AND METHOD THEREFOR 审中-公开
标题翻译： NANOCRYSTAL非易失性记忆细胞及其方法
公开(公告)号：US20080121967A1
公开(公告)日：2008-05-29
申请号：US11530054
申请日：2006-09-08
申请人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
发明人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L29/42332 , B82Y10/00 , H01L29/40114 , H01L29/513 , H01L29/7881
摘要： A method of forming a semiconductor device, which is preferably a memory cell, includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, wherein each of the plurality of discrete storage elements has a diameter value that is approximately equal to each other, and forming a second dielectric layer over the plurality of discrete storage elements, wherein the second dielectric layer has a thickness, wherein the ratio of the thickness of the second dielectric to the diameter value is less than approximately 0.8. The spacing between the plurality of discrete storage elements may be greater than or equal to approximately the thickness of the second dielectric layer.
摘要翻译：形成半导体器件的方法，其优选地是存储单元，包括在半导体衬底上形成第一介电层，在第一介电层上形成多个离散存储元件，其中多个离散存储元件中的每一个具有并且在所述多个分立存储元件上形成第二电介质层，其中所述第二电介质层具有厚度，其中所述第二电介质的厚度与所述直径值的比值小于约0.8。多个离散存储元件之间的间隔可以大于或等于第二电介质层的厚度。

5. 发明申请

US20080121966A1 Nanocrystal non-volatile memory cell and method therefor 有权
标题翻译：纳米晶体非挥发性记忆体及其方法
公开(公告)号：US20080121966A1
公开(公告)日：2008-05-29
申请号：US11530053
申请日：2006-09-08
申请人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
发明人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L29/513 , H01L29/7881 , Y10S977/773
摘要： A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.
摘要翻译：一种形成半导体器件的方法包括在半导体衬底上形成第一电介质层，在第一介电层上形成多个离散存储元件，热氧化多个离散的存储元件，以在多个离散存储器上形成第二电介质元件，并且在所述第二介电层上形成栅电极，其中所述栅电极的重要部分位于所述多个离散存储元件的对之间。在一个实施例中，栅电极的部分位于离散存储元件之间的空间中并且延伸到空间深度的一半以上。

6. 发明申请

US20090166712A1 NANOCRYSTAL NON-VOLATILE MEMORY CELL AND METHOD THEREFOR 有权
标题翻译： NANOCRYSTAL非易失性记忆细胞及其方法
公开(公告)号：US20090166712A1
公开(公告)日：2009-07-02
申请号：US12397849
申请日：2009-03-04
申请人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
发明人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
IPC分类号： H01L29/78
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L29/513 , H01L29/7881 , Y10S977/773
摘要： A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.
摘要翻译：一种形成半导体器件的方法包括在半导体衬底上形成第一电介质层，在第一介电层上形成多个离散存储元件，热氧化多个离散的存储元件，以在多个离散存储器上形成第二电介质元件，并且在所述第二介电层上形成栅电极，其中所述栅电极的重要部分位于所述多个离散存储元件的对之间。在一个实施例中，栅电极的部分位于离散存储元件之间的空间中并且延伸到空间深度的一半以上。

7. 发明授权

US07456465B2 Split gate memory cell and method therefor 有权
标题翻译：分闸存储单元及其方法
公开(公告)号：US07456465B2
公开(公告)日：2008-11-25
申请号：US11240240
申请日：2005-09-30
申请人： Erwin J. Prinz , Michael A. Sadd , Robert F. Steimle
发明人： Erwin J. Prinz , Michael A. Sadd , Robert F. Steimle
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42328 , H01L29/42332
摘要： A split gate memory cell has a select gate, a control gate, and a charge storage structure. The select gate includes a first portion located over the control gate and a second portion not located over the control gate. In one example, the first portion of the select gate has a sidewall aligned with a sidewall of the control gate and aligned with a sidewall of the charge storage structure. In one example, the control gate has a p-type conductivity. In one example, the gate can be programmed by a hot carrier injection operation and can be erased by a tunneling operation.
摘要翻译：分离栅极存储单元具有选择栅极，控制栅极和电荷存储结构。选择栅极包括位于控制栅极上方的第一部分和不位于控制栅极上方的第二部分。在一个示例中，选择栅极的第一部分具有与控制栅极的侧壁对齐并与电荷存储结构的侧壁对准的侧壁。在一个示例中，控制栅极具有p型导电性。在一个示例中，门可以通过热载流子注入操作来编程，并且可以通过隧道操作来擦除。

8. 发明申请

US20090042349A1 SPLIT GATE MEMORY CELL AND METHOD THEREFOR 有权
标题翻译：分离栅格存储单元及其方法
公开(公告)号：US20090042349A1
公开(公告)日：2009-02-12
申请号：US12254294
申请日：2008-10-20
申请人： Erwin J. Prinz , Michael A. Sadd , Robert F. Steimle
发明人： Erwin J. Prinz , Michael A. Sadd , Robert F. Steimle
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42328 , H01L29/42332
摘要： A split gate memory cell has a select gate, a control gate, and a charge storage structure. The select gate includes a first portion located over the control gate and a second portion not located over the control gate. In one example, the first portion of the select gate has a sidewall aligned with a sidewall of the control gate and aligned with a sidewall of the charge storage structure. In one example, the control gate has a p-type conductivity. In one example, the gate can be programmed by a hot carrier injection operation and can be erased by a tunneling operation.
摘要翻译：分离栅极存储单元具有选择栅极，控制栅极和电荷存储结构。选择栅极包括位于控制栅极上方的第一部分和不位于控制栅极上方的第二部分。在一个示例中，选择栅极的第一部分具有与控制栅极的侧壁对齐并与电荷存储结构的侧壁对准的侧壁。在一个示例中，控制栅极具有p型导电性。在一个示例中，门可以通过热载流子注入操作来编程，并且可以通过隧道操作来擦除。

9. 发明授权

US07732278B2 Split gate memory cell and method therefor 有权
标题翻译：分闸存储单元及其方法
公开(公告)号：US07732278B2
公开(公告)日：2010-06-08
申请号：US12254294
申请日：2008-10-20
申请人： Erwin J. Prinz , Michael A. Sadd , Robert F. Steimle
发明人： Erwin J. Prinz , Michael A. Sadd , Robert F. Steimle
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42328 , H01L29/42332
摘要： A split gate memory cell has a select gate, a control gate, and a charge storage structure. The select gate includes a first portion located over the control gate and a second portion not located over the control gate. In one example, the first portion of the select gate has a sidewall aligned with a sidewall of the control gate and aligned with a sidewall of the charge storage structure. In one example, the control gate has a p-type conductivity. In one example, the gate can be programmed by a hot carrier injection operation and can be erased by a tunneling operation.
摘要翻译：分离栅极存储单元具有选择栅极，控制栅极和电荷存储结构。选择栅极包括位于控制栅极上方的第一部分和不位于控制栅极上方的第二部分。在一个示例中，选择栅极的第一部分具有与控制栅极的侧壁对齐并与电荷存储结构的侧壁对准的侧壁。在一个示例中，控制栅极具有p型导电性。在一个示例中，门可以通过热载流子注入操作来编程，并且可以通过隧道操作来擦除。

10. 发明授权

US06297095B1 Memory device that includes passivated nanoclusters and method for manufacture 有权
标题翻译：包含钝化纳米簇的记忆体装置及其制造方法
公开(公告)号：US06297095B1
公开(公告)日：2001-10-02
申请号：US09596399
申请日：2000-06-16
申请人： Ramachandran Muralidhar , Chitra K. Subramanian , Sucharita Madhukar , Bruce E. White , Michael A. Sadd , Sufi Zafar , David L. O'Meara , Bich-Yen Nguyen
发明人： Ramachandran Muralidhar , Chitra K. Subramanian , Sucharita Madhukar , Bruce E. White , Michael A. Sadd , Sufi Zafar , David L. O'Meara , Bich-Yen Nguyen
IPC分类号： H01L21336
CPC分类号： H01L21/28282 , B82Y10/00 , H01L21/28273 , H01L29/66439 , H01L29/7888
摘要： A semiconductor memory device with a floating gate that includes a plurality of nanoclusters (21) and techniques useful in the manufacturing of such a device are presented. The device is formed by first providing a semiconductor substrate (12) upon which a tunnel dielectric layer (14) is formed. A plurality of nanoclusters (19) is then grown on the tunnel dielectric layer (14). After growth of the nanoclusters (21), a control dielectric layer (20) is formed over the nanoclusters (21). In order to prevent oxidation of the formed nanoclusters (21), the nanoclusters (21) may be encapsulated using various techniques prior to formation of the control dielectric layer (20). A gate electrode (24) is then formed over the control dielectric (20), and portions of the control dielectric, the plurality of nanoclusters, and the gate dielectric that do not underlie the gate electrode are selectively removed. After formation of spacers (35), source and drain regions (32, 34) are then formed by implantation in the semiconductor layer (12) such that a channel region is formed between the source and drain regions (32, 34) underlying the gate electrode (24).
摘要翻译：提出了一种具有浮动栅极的半导体存储器件，其包括多个纳米团簇（21）和用于制造这种器件的技术。该器件通过首先提供其上形成有隧道介电层（14）的半导体衬底（12）形成。然后在隧道介电层（14）上生长多个纳米团簇（19）。在纳米团簇（21）生长之后，在纳米团簇（21）上形成控制电介质层（20）。为了防止形成的纳米团簇（21）的氧化，可以在形成控制电介质层（20）之前使用各种技术将纳米团簇（21）进行封装。然后在控制电介质（20）上形成栅极（24），并且选择性地去除不在栅电极下面的控制电介质，多个纳米团簇和栅极电介质的部分。在形成间隔物（35）之后，然后通过注入在半导体层（12）中形成源极和漏极区域（32,34），使得沟道区域形成在栅极下面的源极和漏极区域（32,34）之间电极（24）。

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