专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07340550B2 USB schedule prefetcher for low power 有权
标题翻译： USB调度预取器，用于低功耗
公开(公告)号：US07340550B2
公开(公告)日：2008-03-04
申请号：US11004011
申请日：2004-12-02
申请人： Michael N. Derr , John Howard , Darren Abramson , Leslie E. Cline , Rob Strong
发明人： Michael N. Derr , John Howard , Darren Abramson , Leslie E. Cline , Rob Strong
IPC分类号： G06F13/36 , G06F1/00
CPC分类号： G06F13/28 , G06F2213/0042 , Y02D10/14
摘要： A circuit for monitoring future Universal Serial Bus (USB) activities is described. Specifically, the circuit may comprise a Direct Memory Access (DMA) engine schedule prefetcher. The DMA engine schedule prefetcher accesses linked list schedule structures in main memory. The structures are checked for future frames where the linked list has USB activity scheduled. A periodic DMA engine subsequently accesses main memory only during frames where USB traffic is scheduled.
摘要翻译：描述了用于监控未来通用串行总线（USB）活动的电路。具体地，电路可以包括直接存储器访问（DMA）引擎调度预取器。 DMA引擎调度预取器访问主内存中的链表列表调度结构。对结构进行检查，以便链接列表安排USB活动的将来帧。周期性DMA引擎随后仅在安排USB流量的帧期间访问主存储器。

2. 发明授权

US07523327B2 System and method of coherent data transfer during processor idle states 有权
标题翻译：处理器空闲状态期间相干数据传输的系统和方法
公开(公告)号：US07523327B2
公开(公告)日：2009-04-21
申请号：US11074233
申请日：2005-03-05
申请人： Leslie E. Cline , Siripong Sritanyaratana , Alon Naveh , Shai Rotem , Eric C. Samson , Michael N. Derr
发明人： Leslie E. Cline , Siripong Sritanyaratana , Alon Naveh , Shai Rotem , Eric C. Samson , Michael N. Derr
IPC分类号： G06F1/32
CPC分类号： G06F12/0835 , G06F2212/1028 , Y02D10/13
摘要： Systems and methods of managing power provide for placing a processor in a non-snoopable state, where the processor is associated with a system memory. One or more data transfers between a controller and the system memory can be serviced while the processor is in the non-snoopable state. In one embodiment, it is determined that the processor has flushed an internal cache of the processor to the system memory before placing the processor in the non-snoopable state.
摘要翻译：管理电源的系统和方法提供将处理器置于不可窥探状态，其中处理器与系统存储器相关联。当处理器处于非可窥探状态时，可以在控制器和系统存储器之间进行一个或多个数据传输。在一个实施例中，在将处理器置于非可窥探状态之前，确定处理器将处理器的内部高速缓冲器刷新到系统存储器。

3. 发明申请

US20090193274A1 System And Method of Coherent Data Transfer During Processor Idle States 审中-公开
标题翻译：处理器空闲状态期间相干数据传输的系统和方法
公开(公告)号：US20090193274A1
公开(公告)日：2009-07-30
申请号：US12419090
申请日：2009-04-06
申请人： Leslie E. Cline , Siripong Sritanyaratana , Alon Naveh , Shai Rotem , Eric C. Samson , Michael N. Derr
发明人： Leslie E. Cline , Siripong Sritanyaratana , Alon Naveh , Shai Rotem , Eric C. Samson , Michael N. Derr
IPC分类号： G06F1/32 , G06F12/00 , G06F13/00
CPC分类号： G06F12/0835 , G06F2212/1028 , Y02D10/13
摘要： Systems and methods of managing power provide for placing a processor in a non-snoopable state, where the processor is associated with a system memory. One or more data transfers between a controller and the system memory can be serviced while the processor is in the non-snoopable state. In one embodiment, it is determined that the processor has flushed an internal cache of the processor to the system memory before placing the processor in the non-snoopable state.
摘要翻译：管理电源的系统和方法提供将处理器置于不可窥探状态，其中处理器与系统存储器相关联。当处理器处于非可窥探状态时，可以在控制器和系统存储器之间进行一个或多个数据传输。在一个实施例中，在将处理器置于非可窥探状态之前，确定处理器将处理器的内部高速缓冲器刷新到系统存储器。

4. 发明授权

US07069367B2 Method and apparatus for avoiding race condition with edge-triggered interrupts 失效
公开(公告)号：US07069367B2
公开(公告)日：2006-06-27
申请号：US09752042
申请日：2000-12-29
申请人： David I. Poisner , Leslie E. Cline
发明人： David I. Poisner , Leslie E. Cline
IPC分类号： G06F13/24
CPC分类号： G06F1/3228 , G06F13/24
摘要： An embodiment of a system for avoiding race conditions when using edge-triggered interrupts includes a processor that asserts an interrupt pending signal in response to the receipt of an edge-triggered interrupt. A power management device receives the interrupt pending signal. If the processor is in a low power state when it asserts the interrupt pending signal, then the power management device causes the processor to enter a high power state to allow the processor to service the pending interrupt.

5. 发明授权

US5655145A Peripheral interface circuit which snoops commands to determine when to perform DMA protocol translation 失效
标题翻译：外围接口电路侦听命令来确定何时执行DMA协议转换
公开(公告)号：US5655145A
公开(公告)日：1997-08-05
申请号：US329554
申请日：1994-10-25
申请人： Edward J. Chejlava, Jr. , Leslie E. Cline , Kenneth C. Curt
发明人： Edward J. Chejlava, Jr. , Leslie E. Cline , Kenneth C. Curt
IPC分类号： G06F13/12 , G06F3/06 , G06F13/36 , G06F13/38 , G06F13/00
CPC分类号： G06F3/0601 , G06F13/385 , G06F3/061 , G06F3/0656 , G06F3/0689 , G06F2003/0692 , G06F3/0638 , Y02B60/1228 , Y02B60/1235
摘要： A high performance Local Bus Peripheral Interface (LBPI) for a computer local bus and its high performance peripheral interface(s), using a pipelined architecture to increase the use of the available data transfer bandwidth. To accomplish the above, the LBPI, which is coupled between the computer local bus and the peripheral interface(s), is provided a pipelined architecture which includes a Read Ahead Buffer, a Read Ahead Counter, a Data Out Latch, and a Controlling State Machine with a Configuration Register. In one embodiment, the LBPI can be selectably configured to couple on the host side to either a VL bus or PCI bus. Efficiency of Read-Ahead operations is further enhanced by maintaining a countdown of the number of words of a data sector already transferred and/or "snooping" the peripheral device commands from the computer to intelligently predict the occurrence of subsequent read data transfers commands. The Controlling State Machine also "snoops" the peripheral device commands to maintain its record of the operating parameters of the peripheral devices and also keeps track of which of the devices is currently active. In one embodiment, the LBPI supports DMA and PIO data transfers on the peripheral side. In another embodiment, the LBPI translates memory data transfers into IO data transfers to improve efficiency of IO data transfers. A DMA Timeout Counter is used during DMA mode data transfer operations to prevent the system from indefinitely waiting for an appropriate DMA Request Signal from a selected peripheral. During a DMA mode data transfer operation, forced interrupts may be generated and transmitted to the host in order to emulate a PIO mode data transfer operation. During a DMA mode data transfer operation, an imposed status or "Fake 3F6" register is utilized to transmit status information to the host system.
摘要翻译：用于计算机本地总线的高性能本地总线外设接口（LBPI）及其高性能外设接口，使用流水线架构来增加可用数据传输带宽的使用。为了实现上述目的，耦合在计算机本地总线和外围接口之间的LBPI被提供为流水线架构，其包括预读缓冲器，预读计数器，数据输出锁存器和控制状态机器配置寄存器。在一个实施例中，LBPI可以可选择地配置成在主机侧耦合到VL总线或PCI总线。通过保持已经传送的数据扇区的字数和/或从计算机“窥探”外围设备命令以智能地预测随后的读取数据传输命令的发生，来进一步提高读取前进操作的效率。控制状态机还“窥探”外围设备命令以保持其对外围设备的操作参数的记录，并且还跟踪哪些设备当前处于活动状态。在一个实施例中，LBPI支持外围方面的DMA和PIO数据传输。在另一个实施例中，LBPI将存储器数据传输转换成IO数据传输以提高IO数据传输的效率。在DMA模式数据传输操作期间使用DMA超时计数器，以防止系统无限期地等待来自所选外设的适当的DMA请求信号。在DMA模式数据传输操作期间，可以产生强制中断并将其发送到主机以便模拟PIO模式数据传送操作。在DMA模式数据传输操作期间，利用强制状态或“伪3F6”寄存器将状态信息传送到主机系统。

6. 发明授权

US06871252B1 Method and apparatus for logical detach for a hot-plug-in data bus 失效
标题翻译：用于热插拔数据总线的逻辑分离的方法和装置
公开(公告)号：US06871252B1
公开(公告)日：2005-03-22
申请号：US09540676
申请日：2000-03-31
申请人： Leslie E. Cline
发明人： Leslie E. Cline
IPC分类号： G06F11/00 , G06F13/20 , G06F13/38 , G06F13/40 , H03K17/18
CPC分类号： G06F13/4081
摘要： A method and apparatus for performing logical attachments and detachments in a hot-plug-in data bus is described. A hot-plug-in data bus may utilize pull-down resistors to keep bus signals near a low voltage level when bus units are physically detached. Active pull-up resistors may then raise the bus signals away from ground when the bus units are physically attached via cabling or other forms of interconnection. The pull-up resistors may be switched away from the pull-up voltage source, which allows the remaining pull-down resistors to pull the bus signals down to the voltage levels corresponding to physical detachment of the cabling.
摘要翻译：描述用于在热插拔数据总线中执行逻辑附件和拆卸的方法和装置。当总线单元物理分离时，热插拔数据总线可以利用下拉电阻器将总线信号保持在低电压电平附近。然后，当总线单元通过布线或其他形式的互连物理连接时，主动上拉电阻可以将总线信号提升离地。上拉电阻可以从上拉电压源切换，这允许剩余的下拉电阻将总线信号拉至与布线的物理分离相对应的电压电平。

7. 发明授权

US5603052A Interface circuit for transferring data between host and mass storage by assigning address in the host memory space and placing the address on the bus 失效
标题翻译：接口电路，用于通过在主机存储器空间中分配地址并将地址放置在总线上来在主机和大容量存储之间传送数据
公开(公告)号：US5603052A
公开(公告)日：1997-02-11
申请号：US451877
申请日：1995-05-26
申请人： Edward J. Chejlava, Jr. , Leslie E. Cline , Kenneth C. Curt
发明人： Edward J. Chejlava, Jr. , Leslie E. Cline , Kenneth C. Curt
IPC分类号： G06F13/12 , G06F3/06 , G06F13/36 , G06F13/38 , G06F15/02
CPC分类号： G06F3/0601 , G06F13/385 , G06F3/061 , G06F3/0656 , G06F3/0689 , G06F2003/0692 , G06F3/0638 , Y02B60/1228 , Y02B60/1235
摘要： A high performance Local Bus Peripheral Interface (LBPI) for a computer local bus and its high performance peripheral interface(s) uses a pipelined architecture to increase the use of the available data transfer bandwidth. In one embodiment, the LBPI can be selectably configured to couple on the host side to either a VL bus or PCI bus. The LBPI maintains a countdown of the number of words of a data sector already transferred and/or "snoops" the peripheral device commands from the computer to predict the occurrence of subsequent read data transfers commands. The Controlling State Machine also "snoops" the peripheral device commands to maintain its record of the operating parameters of the peripheral devices and also keeps track of which of the devices is currently active. In one embodiment, the LBPI supports DMA and PIO data transfers on the peripheral side. In another embodiment, the LBPI translates memory data transfers into IO data transfers to improve efficiency of IO data transfers. A DMA Timeout Counter is used during DMA mode data transfer operations to prevent the system from indefinitely waiting for an appropriate DMA Request Signal from a selected peripheral. During a DMA mode data transfer operation, forced interrupts may be generated and transmitted to the host in order to emulate a PIO mode data transfer operation. During a DMA mode data transfer operation, an imposed status or "Fake 3F6" register is utilized to transmit status information to the host system.
摘要翻译：用于计算机本地总线的高性能本地总线外设接口（LBPI）及其高性能外设接口使用流水线架构来增加可用数据传输带宽的使用。在一个实施例中，LBPI可以可选择地配置成在主机侧耦合到VL总线或PCI总线。 LBPI维护已经传送的数据扇区的字数和/或从计算机“窥探”外围设备命令的倒数，以预测后续读取数据传输命令的发生。控制状态机还“窥探”外围设备命令以保持其对外围设备的操作参数的记录，并且还跟踪哪些设备当前处于活动状态。在一个实施例中，LBPI支持外围方面的DMA和PIO数据传输。在另一个实施例中，LBPI将存储器数据传输转换成IO数据传输以提高IO数据传输的效率。在DMA模式数据传输操作期间使用DMA超时计数器，以防止系统无限期地等待来自所选外设的适当的DMA请求信号。在DMA模式数据传输操作期间，可以产生强制中断并将其发送到主机以便模拟PIO模式数据传送操作。在DMA模式数据传输操作期间，利用强制状态或“伪3F6”寄存器将状态信息传送到主机系统。

8. 发明授权

US09170626B2 Performance reduction limit for power consumption device 有权
标题翻译：功耗设备性能下限
公开(公告)号：US09170626B2
公开(公告)日：2015-10-27
申请号：US13023355
申请日：2011-02-08
申请人： Leslie E. Cline , Sitaram Yadavalli , Ishmael Santos , Jim Hermerding
发明人： Leslie E. Cline , Sitaram Yadavalli , Ishmael Santos , Jim Hermerding
IPC分类号： H02J3/12 , G06F1/32 , G06F1/20
CPC分类号： G06F1/3203 , G06F1/206 , Y02D10/16 , Y10T307/438
摘要： For one disclosed embodiment, a lower limit for a power consumption device may be identified. Performance of the power consumption device may be reduced in response to a determination that a temperature corresponding to the power consumption device exceeds a threshold. Performance reduction may be limited based on the lower limit. Other embodiments are also disclosed.
摘要翻译：对于一个公开的实施例，可以识别功耗装置的下限。响应于与功率消耗装置相对应的温度超过阈值的确定，可以降低功耗装置的性能。性能下降可能受限于下限。还公开了其他实施例。

9. 发明授权

US07472289B2 Audio noise mitigation for power state transitions 失效
标题翻译：功率状态转换的音频噪声抑制
公开(公告)号：US07472289B2
公开(公告)日：2008-12-30
申请号：US11019791
申请日：2004-12-21
申请人： Jorge P. Rodriguez , Leslie E. Cline , Barnes Cooper
发明人： Jorge P. Rodriguez , Leslie E. Cline , Barnes Cooper
IPC分类号： G06F1/00 , H04B15/00
CPC分类号： G06F1/3203
摘要： An audio noise mitigation approach. For one aspect, a first voltage associated with a first power management state is provided. A signal responsive to an indication associated with at least a first type of periodic exit event is received and responsive to the signal, a transition to a second voltage associated with a second state is initiated, a rate of the transition to the second voltage being slower than a similar voltage transition initiated in response to a non-periodic exit event.
摘要翻译：音频噪声缓解方法。一方面，提供与第一电源管理状态相关联的第一电压。接收响应于与至少第一类型的周期性退出事件相关联的指示的信号并且响应于该信号，开始向与第二状态相关联的第二电压的转变，到第二电压的转变的速率较慢而不是响应于非周期性退出事件而发起的类似电压转换。

10. 发明授权

US07373534B2 Reducing storage data transfer interference with processor power management 有权
标题翻译：减少存储数据传输干扰与处理器电源管理
公开(公告)号：US07373534B2
公开(公告)日：2008-05-13
申请号：US11165157
申请日：2005-06-23
申请人： Leslie E. Cline
发明人： Leslie E. Cline
IPC分类号： G06F1/00
CPC分类号： G06F1/3215
摘要： Systems and methods of managing power consumption provide for placing a processor in a non-snoopable state while a storage interface associated with the processor is enabled for bus mastering. In one embodiment, the bus mastering results in traffic between the storage interface and a storage device, where the traffic is monitored and the processor is placed a snoopable state when traffic is moving, and in the non-snoopable idle state if the traffic ceases for a period of time.
摘要翻译：管理功耗的系统和方法提供了将处理器置于不可窥探状态，而与处理器相关联的存储接口能够用于总线主控。在一个实施例中，总线主控导致存储接口和存储设备之间的业务，其中监视业务，并且当业务正在移动时将处理器置于可窥探状态，并且处于不可窥探空闲状态，如果业务停止一段时间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式