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1. 发明授权

US5655145A Peripheral interface circuit which snoops commands to determine when to perform DMA protocol translation 失效
标题翻译：外围接口电路侦听命令来确定何时执行DMA协议转换
公开(公告)号：US5655145A
公开(公告)日：1997-08-05
申请号：US329554
申请日：1994-10-25
申请人： Edward J. Chejlava, Jr. , Leslie E. Cline , Kenneth C. Curt
发明人： Edward J. Chejlava, Jr. , Leslie E. Cline , Kenneth C. Curt
IPC分类号： G06F13/12 , G06F3/06 , G06F13/36 , G06F13/38 , G06F13/00
CPC分类号： G06F3/0601 , G06F13/385 , G06F3/061 , G06F3/0656 , G06F3/0689 , G06F2003/0692 , G06F3/0638 , Y02B60/1228 , Y02B60/1235
摘要： A high performance Local Bus Peripheral Interface (LBPI) for a computer local bus and its high performance peripheral interface(s), using a pipelined architecture to increase the use of the available data transfer bandwidth. To accomplish the above, the LBPI, which is coupled between the computer local bus and the peripheral interface(s), is provided a pipelined architecture which includes a Read Ahead Buffer, a Read Ahead Counter, a Data Out Latch, and a Controlling State Machine with a Configuration Register. In one embodiment, the LBPI can be selectably configured to couple on the host side to either a VL bus or PCI bus. Efficiency of Read-Ahead operations is further enhanced by maintaining a countdown of the number of words of a data sector already transferred and/or "snooping" the peripheral device commands from the computer to intelligently predict the occurrence of subsequent read data transfers commands. The Controlling State Machine also "snoops" the peripheral device commands to maintain its record of the operating parameters of the peripheral devices and also keeps track of which of the devices is currently active. In one embodiment, the LBPI supports DMA and PIO data transfers on the peripheral side. In another embodiment, the LBPI translates memory data transfers into IO data transfers to improve efficiency of IO data transfers. A DMA Timeout Counter is used during DMA mode data transfer operations to prevent the system from indefinitely waiting for an appropriate DMA Request Signal from a selected peripheral. During a DMA mode data transfer operation, forced interrupts may be generated and transmitted to the host in order to emulate a PIO mode data transfer operation. During a DMA mode data transfer operation, an imposed status or "Fake 3F6" register is utilized to transmit status information to the host system.
摘要翻译：用于计算机本地总线的高性能本地总线外设接口（LBPI）及其高性能外设接口，使用流水线架构来增加可用数据传输带宽的使用。为了实现上述目的，耦合在计算机本地总线和外围接口之间的LBPI被提供为流水线架构，其包括预读缓冲器，预读计数器，数据输出锁存器和控制状态机器配置寄存器。在一个实施例中，LBPI可以可选择地配置成在主机侧耦合到VL总线或PCI总线。通过保持已经传送的数据扇区的字数和/或从计算机“窥探”外围设备命令以智能地预测随后的读取数据传输命令的发生，来进一步提高读取前进操作的效率。控制状态机还“窥探”外围设备命令以保持其对外围设备的操作参数的记录，并且还跟踪哪些设备当前处于活动状态。在一个实施例中，LBPI支持外围方面的DMA和PIO数据传输。在另一个实施例中，LBPI将存储器数据传输转换成IO数据传输以提高IO数据传输的效率。在DMA模式数据传输操作期间使用DMA超时计数器，以防止系统无限期地等待来自所选外设的适当的DMA请求信号。在DMA模式数据传输操作期间，可以产生强制中断并将其发送到主机以便模拟PIO模式数据传送操作。在DMA模式数据传输操作期间，利用强制状态或“伪3F6”寄存器将状态信息传送到主机系统。

2. 发明授权

US5826107A Method and apparatus for implementing a DMA timeout counter feature 失效
标题翻译：用于实现DMA超时计数器功能的方法和装置
公开(公告)号：US5826107A
公开(公告)日：1998-10-20
申请号：US329360
申请日：1994-10-25
申请人： Leslie E. Cline , Edward J. Chejlava, Jr. , Anh L. Pham
发明人： Leslie E. Cline , Edward J. Chejlava, Jr. , Anh L. Pham
IPC分类号： G06F13/12 , G06F3/06 , G06F13/36 , G06F13/38 , G06F3/00
CPC分类号： G06F3/0601 , G06F13/385 , G06F3/061 , G06F3/0656 , G06F3/0689 , G06F2003/0692 , G06F3/0638 , Y02B60/1228 , Y02B60/1235
摘要： A high performance Local Bus Peripheral Interface (LBPI) for a computer local bus and high performance peripheral interface(s) uses a pipelined architecture to increase use of available data transfer bandwidth. The LBPI coupled between the computer local bus and peripheral interface(s) is provided a pipelined architecture including a Read Ahead Buffer, a Read Ahead Counter, a Data Out Latch, and a controlling State Machine with a Configuration Register. The LBPI supports DMA and PIO data transfers on the peripheral side. In another embodiment, the LBPI translates memory data transfers into IO data transfers to improve efficiency of IO data transfers. A DMA Timeout Counter is used during DMA mode data transfer operations to prevent the system from indefinitely waiting for an appropriate DMA Request Signal from a selected peripheral. During a DMA mode data transfer operation, forced interrupts may be generated and transmitted to the host in order to emulate a PIO mode data transfer operation. During a DMA mode data transfer operation, an imposed status or "Fake 3F6" register is utilized to transmit status information to the host system.
摘要翻译：用于计算机本地总线和高性能外设接口的高性能本地总线外设接口（LBPI）使用流水线架构来增加可用数据传输带宽的使用。耦合在计算机本地总线和外设接口之间的LBPI被提供流水线架构，其包括预读缓冲器，预读计数器，数据输出锁存器以及具有配置寄存器的控制状态机。 LBPI支持外设端的DMA和PIO数据传输。在另一个实施例中，LBPI将存储器数据传输转换成IO数据传输以提高IO数据传输的效率。在DMA模式数据传输操作期间使用DMA超时计数器，以防止系统无限期地等待来自所选外设的适当的DMA请求信号。在DMA模式数据传输操作期间，可以产生强制中断并将其发送到主机以便模拟PIO模式数据传送操作。在DMA模式数据传输操作期间，利用强制状态或“伪3F6”寄存器将状态信息传送到主机系统。

3. 发明授权

US5630171A Translating from a PIO protocol to DMA protocol with a peripheral interface circuit 失效
标题翻译：使用外设接口电路从PIO协议转换为DMA协议
公开(公告)号：US5630171A
公开(公告)日：1997-05-13
申请号：US667914
申请日：1996-06-20
申请人： Edward J. Chejlava, Jr. , Leslie E. Cline , Kenneth C. Curt
发明人： Edward J. Chejlava, Jr. , Leslie E. Cline , Kenneth C. Curt
IPC分类号： G06F13/12 , G06F3/06 , G06F13/36 , G06F13/38 , G06F13/00
CPC分类号： G06F3/0601 , G06F13/385 , G06F3/061 , G06F3/0656 , G06F3/0689 , G06F2003/0692 , G06F3/0638 , Y02B60/1228 , Y02B60/1235
摘要： A high performance Local Bus Peripheral Interface (LBPI) for a computer local bus and its high performance peripheral interface(s) uses a pipelined architecture to increase the use of the available data transfer bandwidth. In one embodiment, the LBPI can be selectably configured to couple on the host side to either a VL bus or PCI bus. The LBPI maintains a countdown of the number of words of a data sector already transferred and/or "snoops" the peripheral device commands from the computer to predict the occurrence of subsequent read data transfers commands. The Controlling State Machine also "snoops" the peripheral device commands to maintain its record of the operating parameters of the peripheral devices and also keeps track of which of the devices is currently active. In one embodiment, the LBPI supports DMA and PIO data transfers on the peripheral side. In another embodiment, the LBPI translates memory data transfers into IO data transfers to improve efficiency of IO data transfers. A DMA Timeout Counter is used during DMA mode data transfer operations to prevent the system from indefinitely waiting for an appropriate DMA Request Signal from a selected peripheral. During a DMA mode data transfer operation, forced interrupts may be generated and transmitted to the host in order to emulate a PIO mode data transfer operation. During a DMA mode data transfer operation, an imposed status or "Fake 3F6" register is utilized to transmit status information to the host system.
摘要翻译：用于计算机本地总线的高性能本地总线外设接口（LBPI）及其高性能外设接口使用流水线架构来增加可用数据传输带宽的使用。在一个实施例中，LBPI可以可选择地配置成在主机侧耦合到VL总线或PCI总线。 LBPI维护已经传送的数据扇区的字数和/或从计算机“窥探”外围设备命令的倒数，以预测后续读取数据传输命令的发生。控制状态机还“窥探”外围设备命令以保持其对外围设备的操作参数的记录，并且还跟踪哪些设备当前处于活动状态。在一个实施例中，LBPI支持外围方面的DMA和PIO数据传输。在另一个实施例中，LBPI将存储器数据传输转换成IO数据传输以提高IO数据传输的效率。在DMA模式数据传输操作期间使用DMA超时计数器，以防止系统无限期地等待来自所选外设的适当的DMA请求信号。在DMA模式数据传输操作期间，可以产生强制中断并将其发送到主机以便模拟PIO模式数据传送操作。在DMA模式数据传输操作期间，利用强制状态或“伪3F6”寄存器将状态信息传送到主机系统。

4. 发明授权

US6131132A High performance peripheral interface 失效
标题翻译：高性能外设接口
公开(公告)号：US6131132A
公开(公告)日：2000-10-10
申请号：US459561
申请日：1995-06-02
申请人： Kenneth C. Curt , Edward J. Chejlava, Jr. , Anthony Kozaczuk
发明人： Kenneth C. Curt , Edward J. Chejlava, Jr. , Anthony Kozaczuk
IPC分类号： G06F13/12 , G06F3/06 , G06F13/36 , G06F13/38 , G06F13/00
CPC分类号： G06F3/0601 , G06F13/385 , G06F3/061 , G06F3/0656 , G06F3/0689 , G06F2003/0692 , G06F3/0638 , Y02B60/1228 , Y02B60/1235
摘要： A high performance peripheral interface device is coupled to a computer via a computer bus and is coupled to a peripheral via a peripheral bus. To speed accessing of consecutively addressed data (the nth datum and the n+1th datum) from the peripheral, the interface device reads the n+1th datum from the peripheral: 1) before the computer has requested the n+1th datum from the interface device, and 2) while the computer is accessing the nth datum from the interface device.
摘要翻译：高性能外围接口设备经由计算机总线耦合到计算机，并通过外围总线耦合到外围设备。为了加速从外设访问连续寻址的数据（第n个数据和第n + 1个数据），接口设备从外设读取第n + 1个数据：1）在计算机从接口请求第n + 1个数据之前设备，2）当计算机从接口设备访问第n个数据时。

5. 发明授权

US5603052A Interface circuit for transferring data between host and mass storage by assigning address in the host memory space and placing the address on the bus 失效
标题翻译：接口电路，用于通过在主机存储器空间中分配地址并将地址放置在总线上来在主机和大容量存储之间传送数据
公开(公告)号：US5603052A
公开(公告)日：1997-02-11
申请号：US451877
申请日：1995-05-26
申请人： Edward J. Chejlava, Jr. , Leslie E. Cline , Kenneth C. Curt
发明人： Edward J. Chejlava, Jr. , Leslie E. Cline , Kenneth C. Curt
IPC分类号： G06F13/12 , G06F3/06 , G06F13/36 , G06F13/38 , G06F15/02
CPC分类号： G06F3/0601 , G06F13/385 , G06F3/061 , G06F3/0656 , G06F3/0689 , G06F2003/0692 , G06F3/0638 , Y02B60/1228 , Y02B60/1235
摘要： A high performance Local Bus Peripheral Interface (LBPI) for a computer local bus and its high performance peripheral interface(s) uses a pipelined architecture to increase the use of the available data transfer bandwidth. In one embodiment, the LBPI can be selectably configured to couple on the host side to either a VL bus or PCI bus. The LBPI maintains a countdown of the number of words of a data sector already transferred and/or "snoops" the peripheral device commands from the computer to predict the occurrence of subsequent read data transfers commands. The Controlling State Machine also "snoops" the peripheral device commands to maintain its record of the operating parameters of the peripheral devices and also keeps track of which of the devices is currently active. In one embodiment, the LBPI supports DMA and PIO data transfers on the peripheral side. In another embodiment, the LBPI translates memory data transfers into IO data transfers to improve efficiency of IO data transfers. A DMA Timeout Counter is used during DMA mode data transfer operations to prevent the system from indefinitely waiting for an appropriate DMA Request Signal from a selected peripheral. During a DMA mode data transfer operation, forced interrupts may be generated and transmitted to the host in order to emulate a PIO mode data transfer operation. During a DMA mode data transfer operation, an imposed status or "Fake 3F6" register is utilized to transmit status information to the host system.
摘要翻译：用于计算机本地总线的高性能本地总线外设接口（LBPI）及其高性能外设接口使用流水线架构来增加可用数据传输带宽的使用。在一个实施例中，LBPI可以可选择地配置成在主机侧耦合到VL总线或PCI总线。 LBPI维护已经传送的数据扇区的字数和/或从计算机“窥探”外围设备命令的倒数，以预测后续读取数据传输命令的发生。控制状态机还“窥探”外围设备命令以保持其对外围设备的操作参数的记录，并且还跟踪哪些设备当前处于活动状态。在一个实施例中，LBPI支持外围方面的DMA和PIO数据传输。在另一个实施例中，LBPI将存储器数据传输转换成IO数据传输以提高IO数据传输的效率。在DMA模式数据传输操作期间使用DMA超时计数器，以防止系统无限期地等待来自所选外设的适当的DMA请求信号。在DMA模式数据传输操作期间，可以产生强制中断并将其发送到主机以便模拟PIO模式数据传送操作。在DMA模式数据传输操作期间，利用强制状态或“伪3F6”寄存器将状态信息传送到主机系统。

6. 发明授权

US5592682A Interface circuit for transferring data between host device and mass storage device in response to designated address in host memory space assigned as data port 失效
公开(公告)号：US5592682A
公开(公告)日：1997-01-07
申请号：US329557
申请日：1994-10-25
申请人： Edward J. Chejlava, Jr. , Leslie E. Cline , Kenneth C. Curt
发明人： Edward J. Chejlava, Jr. , Leslie E. Cline , Kenneth C. Curt
IPC分类号： G06F13/12 , G06F3/06 , G06F13/36 , G06F13/38 , G06F15/02
CPC分类号： G06F3/0601 , G06F13/385 , G06F3/061 , G06F3/0656 , G06F3/0689 , G06F2003/0692 , G06F3/0638 , Y02B60/1228 , Y02B60/1235
摘要： A high performance Local Bus Peripheral Interface (LBPI) for a computer local bus and its high performance peripheral interface(s), using a pipelined architecture to increase the use of the available data transfer bandwidth. To accomplish the above, the LBPI, which is coupled between the computer local bus and the peripheral interface(s), is provided a pipelined architecture which includes a Read Ahead Buffer, a Read Ahead Counter, a Data Out Latch, and a Controlling State Machine with a Configuration Register. In one embodiment, the LBPI can be selectably configured to couple on the host side to either a VL bus or PCI bus. Efficiency of Read-Ahead operations is further enhanced by maintaining a countdown of the number of words of a data sector already transferred and/or "snooping" the peripheral device commands from the computer to intelligently predict the occurrence of subsequent read data transfers commands. The Controlling State Machine also "snoops" the peripheral device commands to maintain its record of the operating parameters of the peripheral devices and also keeps track of which of the devices is currently active. In one embodiment, the LBPI supports DMA and PIO data transfers on the peripheral side. In another embodiment, the LBPI translates memory data transfers into IO data transfers to improve efficiency of IO data transfers. A DMA Timeout Counter is used during DMA mode data transfer operations to prevent the system from indefinitely waiting for an appropriate DMA Request Signal from a selected peripheral. During a DMA mode data transfer operation, forced interrupts may be generated and transmitted to the host in order to emulate a PIO mode data transfer operation. During a DMA mode data transfer operation, an imposed status or "Fake 3F6" register is utilized to transmit status information to the host system.

7. 发明授权

US5584040A High performance peripheral interface with read-ahead capability 失效
标题翻译：高性能外设接口具有预读能力
公开(公告)号：US5584040A
公开(公告)日：1996-12-10
申请号：US550187
申请日：1995-10-30
申请人： Kenneth C. Curt , Edward J. Chejlava, Jr. , Anthony Kozaczuk
发明人： Kenneth C. Curt , Edward J. Chejlava, Jr. , Anthony Kozaczuk
IPC分类号： G06F13/12 , G06F3/06 , G06F13/36 , G06F13/38 , G06F3/00
CPC分类号： G06F3/0601 , G06F13/385 , G06F3/061 , G06F3/0656 , G06F3/0689 , G06F2003/0692 , G06F3/0638 , Y02B60/1228 , Y02B60/1235
摘要： A high performance Local Bus Peripheral Interface (LBPI) for a computer local bus and its high performance peripheral interface(s) uses a pipelined architecture to increase the use of the available data transfer bandwidth. The LBPI is coupled between the computer local bus and the peripheral interface(s) and has a pipelined architecture which includes a Read Ahead Buffer, a Read Ahead Counter, a Data Out Latch, and a Controlling State Machine with a Configuration Register. The LPBI maintains a countdown of the number of words of a data sector already transferred and/or "snoops" the peripheral device commands from the computer to intelligently predict the occurrence of subsequent read data transfers commands. The Controlling State Machine also "snoops" the peripheral device commands to maintain its record of the operating parameters of the peripheral devices and also keeps track of which of the devices is currently active.
摘要翻译：用于计算机本地总线的高性能本地总线外设接口（LBPI）及其高性能外设接口使用流水线架构来增加可用数据传输带宽的使用。 LBPI耦合在计算机本地总线和外围接口之间，并且具有流水线架构，其包括预读缓冲器，预读计数器，数据输出锁存器和具有配置寄存器的控制状态机。 LPBI保持已经传送的数据扇区的字数和/或从计算机“窥探”外围设备命令，以智能地预测后续读取数据传输命令的发生的倒数。控制状态机还“窥探”外围设备命令以保持其对外围设备的操作参数的记录，并且还跟踪哪些设备当前处于活动状态。

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