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1. 发明授权

US4000393A Thermal printhead assembly 失效
标题翻译：热敏打印头组件
公开(公告)号：US4000393A
公开(公告)日：1976-12-28
申请号：US501919
申请日：1974-08-29
申请人： Michael J. Cochran , Larry D. Propst , Richard D. Harris , Robert E. Belland , John W. Richardson , Stephen P. Hamilton
发明人： Michael J. Cochran , Larry D. Propst , Richard D. Harris , Robert E. Belland , John W. Richardson , Stephen P. Hamilton
IPC分类号： H05B3/06 , H05B1/00
CPC分类号： H05B3/06
摘要： A method of assembling, positioning, and making connections to a thermal printhead is disclosed. A substrate is provided upon which heating elements or mesas are mounted. Leads from these heating elements are continued on the same side of the substrate as the one on which the elements are located. The leads are brought to terminal pads where connections may be made to the logic circuit which selectively energizes the heating elements to form numerals or characters on heat sensitive paper. A flat flexible cable with conductor ends exposed is held in place so that the exposed conductor ends make contact with the terminal pads of one or more of such substrates. The substrates and cable are clamped together by two metal plates. This entire assembly is mounted on a spring-loaded pivot arrangement so as to hold the heating elements against the heat sensitive paper on an advancing platen. Connections may be made between the cable conductors and the printing logic to allow the heating elements to be energized.
摘要翻译：公开了一种组合，定位和连接热敏打印头的方法。设置有加热元件或台面安装的基板。来自这些加热元件的引线在与元件所在的基板相同的一侧上继续。引线被带到端子焊盘，其中可以对逻辑电路进行连接，逻辑电路选择性地激励加热元件以在热敏纸上形成数字或字符。导体端部露出的扁平柔性电缆被固定到位，使得暴露的导体端部与一个或多个这样的基板的端子焊盘接触。基板和电缆通过两个金属板夹在一起。该整个组件安装在弹簧加载的枢转装置上，以将加热元件保持在前进压板上的热敏纸上。可以在电缆导体和打印逻辑之间进行连接，以允许加热元件被通电。

2. 发明授权

US4145756A Thermal line printer 失效
标题翻译：热线打印机
公开(公告)号：US4145756A
公开(公告)日：1979-03-20
申请号：US748076
申请日：1976-12-06
申请人： Michael J. Cochran , Stephen P. Hamilton
发明人： Michael J. Cochran , Stephen P. Hamilton
IPC分类号： G06K15/02 , G08B5/36
CPC分类号： G06K15/028
摘要： A thermal printer system for actuating a plurality of groups of thermal printing elements. The system includes a first circuit in which a plurality of data words are stored, the words representing the characters to be printed. A second circuit converts the data words into printing character codes. A selected bit from each code, which bit is sequentially altered, is supplied to a third circuit for actuating the printing elements.
摘要翻译：一种用于致动多组热敏打印元件的热敏打印机系统。该系统包括其中存储多个数据字的第一电路，表示要打印的字符的字。第二个电路将数据字转换成打印字符代码。来自每个代码的选择的位被顺序地改变，被提供给用于致动打印元件的第三电路。

3. 发明授权

US4125830A Alphanumeric display system 失效
标题翻译：字母数字显示系统
公开(公告)号：US4125830A
公开(公告)日：1978-11-14
申请号：US658793
申请日：1976-02-17
申请人： Michael J. Cochran , Stephen P. Hamilton
发明人： Michael J. Cochran , Stephen P. Hamilton
IPC分类号： G09G3/14 , G06K15/18
CPC分类号： G09G3/14
摘要： An alphanumeric display system which may be implemented on one or more semiconductor chips for controlling display devices arrayed in N groups, each group of which comprises an A by B matrix of devices and which is capable of displaying a single alphanumeric character. The display devices in each group are sequentially addressed with display commands being communicated therewith in a predetermined manner to cause the display devices to visually display a predetermined alphanumeric character. Use of the alphanumeric display system herein disclosed, permits a total of A by B by N display devices to be controlled by the display system using as few as A + B + N connecting conductors to control the display devices and associated display driver devices.
摘要翻译：可以在一个或多个半导体芯片上实现的用于控制以N组排列的显示设备的字母数字显示系统，每个组包括设备的A乘B矩阵，并且能够显示单个字母数字字符。每组中的显示装置按照预定方式与显示命令进行顺序寻址，以使显示装置可视地显示预定的字母数字字符。使用本文公开的字母数字显示系统，允许N显示设备的总共A乘B由显示系统使用少至A + B + N连接导体来控制显示设备和相关显示驱动器设备。

4. 发明授权

US4038535A Calculator-print cradle system 失效
标题翻译：计算机打印系统
公开(公告)号：US4038535A
公开(公告)日：1977-07-26
申请号：US646463
申请日：1976-01-05
申请人： Bruce E. Aldridge , Michael J. Cochran , Lee G. Kitchens , Robert R. Kressler , Stephen P. Hamilton
发明人： Bruce E. Aldridge , Michael J. Cochran , Lee G. Kitchens , Robert R. Kressler , Stephen P. Hamilton
IPC分类号： G06F15/02
CPC分类号： G06F15/0233
摘要： This invention relates to enhancement of calculator versatility through connections provided in a calculator cradle leading to a printing mechanism therein when a calculator is nested in the cradle. In a more specific aspect, the invention relates to the communication between a calculator and a printer module which nests the calculator and responds to instructions and data flow from the calculator to print selected calculator information.

5. 发明授权

US4020465A Thermal line printer 失效
标题翻译：热线打印机
公开(公告)号：US4020465A
公开(公告)日：1977-04-26
申请号：US428492
申请日：1973-12-26
申请人： Michael J. Cochran , Stephen P. Hamilton
发明人： Michael J. Cochran , Stephen P. Hamilton
IPC分类号： G06K15/02 , G06F3/12 , H04L15/24
CPC分类号： G06K15/028
摘要： A thermal line printer includes a semiconductor chip for control of A .times. N heaters arrayed in N groups past which thermally sensitive paper is stepped B times in printing a line of characters in an A .times. B dot matrix. A sequential access memory stores N multibit words, one word for each character to be printed on a given line with a commutator cyclically to read words from the memory A .times. B times for each line to be printed. A ROM has an A .times. B dot matrix code therein for each available character. A time sequencer and decoder connected to the ROM is synchronized with the commutator to produce a different one bit output from the ROM each time each given word is read from memory. A set of N enable circuits leads from the ROM to N groups of heaters. A set of A enable circuits leads from the sequencer to A groups of heaters where one heater in each A group is from one of the N groups. A decoder interfaces the sequencer to the A groups of heaters and to the motor sequentially to enable the heaters in one A group for each memory cycle and in order through the A columns and B rows of the matrix.
摘要翻译：热线打印机包括用于控制以N组排列的A x N加热器的半导体芯片，其中热敏纸在A×B点阵列中打印一行字符是阶梯B次。顺序访问存储器将N个多位字存储在一个给定行上的每个字符的一个字，循环地用换向器从每个行被打印的存储器读取字B×B次。对于每个可用字符，ROM中具有A×B点阵码。连接到ROM的定时器和解码器与换向器同步，每当从存储器读取每个给定字时，从ROM产生不同的一位输出。一组N个使能电路从ROM引导到N组加热器。一组A使能电路从定序器引导到一组加热器，每组A组中的一个加热器来自N组之一。解码器将定序器与A组加热器和电机顺序接口，以使每个存储器周期中的一组A组中的加热器顺序通过矩阵的A列和B行。

6. 发明授权

US4419746A Multiple pointer memory system 失效
标题翻译：多指针存储系统
公开(公告)号：US4419746A
公开(公告)日：1983-12-06
申请号：US196808
申请日：1980-10-14
申请人： Arthur C. Hunter , Stephen P. Hamilton
发明人： Arthur C. Hunter , Stephen P. Hamilton
IPC分类号： G06F12/02 , G11C8/00 , G11C13/00
CPC分类号： G11C8/00 , G06F12/0207
摘要： A memory system includes a multiple memory pointer in which a pointer selection signal selects one of a plurality of memory pointers to generate an address signal for application to the memory for controlling the location of memory operations. In the preferred embodiment the memory is arranged in an X by Y matrix having X times Y individually addressable memory locations. A first pointer circuit has a plurality of address pointers, one of which is selected for generation of an X coordinate address. A second pointer circuit includes a single address pointer for generation of the Y coordinate address. The second pointer circuit may be a multiple pointer in an alternative embodiment. By provision of a number of individually addressable memories responsive to the same memory pointer system, separate application of address signals from differing address pointers to differing memories permits multiple memory operations in a single instruction cycle.
摘要翻译：存储器系统包括多存储器指针，其中指针选择信号选择多个存储器指针之一以产生用于应用于存储器的地址信号，用于控制存储器操作的位置。在优选实施例中，存储器被布置在具有X次Y个别可寻址存储器位置的X乘Y矩阵中。第一指针电路具有多个地址指针，其中之一被选择用于生成X坐标地址。第二指针电路包括用于生成Y坐标地址的单个地址指针。第二指针电路可以是替代实施例中的多指针。通过提供响应于相同的存储器指针系统的多个可单独寻址的存储器，将地址信号从不同的地址指针分离到不同的存储器，允许在单个指令周期内的多个存储器操作。

7. 发明授权

US4503494A Non-volatile memory system 失效
标题翻译：非易失性存储器系统
公开(公告)号：US4503494A
公开(公告)日：1985-03-05
申请号：US163237
申请日：1980-06-26
申请人： Stephen P. Hamilton , Harry G. McFarland
发明人： Stephen P. Hamilton , Harry G. McFarland
IPC分类号： G06F1/00 , G06F9/312 , G11C5/14 , G06F7/38 , G06F1/04 , H02J9/04
CPC分类号： G06F9/30043 , G06F1/00 , G11C5/141
摘要： Disclosed is a non-volatile memory system which includes a first power means for providing a main power source; a read/write memory means for storing and retrieving data signals so long as power is provided; and second power means for coupling to the first power means and to the read/write memory means, the second power means including auxiliary power means for providing a second power source; the second power means further including controller means for continuously providing power to the read/write memory means from either the first power means or the auxiliary power means. In the preferred embodiment, the first power means is within a housing, said housing having a compartment for the receipt of a plug-in module, and the second power means and read/write memory means are contained within the plug-in module. Additionally, in the preferred embodiment, the memory means and the second power means exclusive of the second power source are comprised of a single integrated circuit. Furthermore, in the preferred embodiment, the power controller and memory system are coupled to a data processing system such as an electronic calculator.
摘要翻译：公开了一种非易失性存储器系统，其包括用于提供主电源的第一电源装置; 读/写存储装置，用于在提供电力的情况下存储和检索数据信号; 以及用于耦合到第一功率装置和读/写存储装置的第二功率装置，第二功率装置包括用于提供第二电源的辅助功率装置; 第二电源装置还包括用于从第一电源装置或辅助电源装置连续向读/写存储装置供电的控制装置。在优选实施例中，第一动力装置在壳体内，所述壳体具有用于接收插件模块的隔室，并且第二动力装置和读/写存储装置被包含在插入式模块内。此外，在优选实施例中，除了第二电源之外的存储装置和第二功率装置由单个集成电路组成。此外，在优选实施例中，功率控制器和存储器系统耦合到诸如电子计算器的数据处理系统。

8. 发明授权

US4125901A Electronic calculator or microprocessor having a multi-input arithmetic unit 失效
标题翻译：具有多输入算术单元的电子计算器或微处理器
公开(公告)号：US4125901A
公开(公告)日：1978-11-14
申请号：US736057
申请日：1976-10-27
申请人： Thomas E. Merrow , Stephen P. Hamilton , Larry L. Miles , Charles P. Grant, Jr., deceased
发明人： Thomas E. Merrow , Stephen P. Hamilton , Larry L. Miles , Charles P. Grant, Jr., deceased
IPC分类号： G06F9/30 , G06F7/48
CPC分类号： G06F9/30134
摘要： An electronic calculator or microprocessor system of the type preferably having keyboard input and a visual display is implemented with a semiconductor chip having a arithmetic unit and memory system. The arithmetic unit and memory system include a plurality of operational registers and an arithmetic unit having two inputs and an output. A plurality of operational registers selector gates interconnect the operational registers and arithmetic unit for connecting any selected two of the plurality of operational registers to the inputs of the arithmetic unit. The plurality of operation register selector gates preferably comprise individual MOS transfer gates.
摘要翻译：具有键盘输入和视觉显示的类型的电子计算器或微处理器系统由具有运算单元和存储器系统的半导体芯片实现。算术单元和存储器系统包括多个操作寄存器和具有两个输入和一个输出的算术单元。多个操作寄存器选择器门互连操作寄存器和运算单元，用于将多个操作寄存器中的所选择的两个连接到运算单元的输入端。多个操作寄存器选择器门优选地包括单独的MOS传输门。

9. 发明授权

US4107781A Electronic calculator or microprocessor with indirect addressing 失效
标题翻译：电子计算器或具有间接寻址的微处理器
公开(公告)号：US4107781A
公开(公告)日：1978-08-15
申请号：US736001
申请日：1976-10-27
申请人： Johnny M. Barrett , Stephen P. Hamilton
发明人： Johnny M. Barrett , Stephen P. Hamilton
IPC分类号： G06F9/32 , G06F9/20
CPC分类号： G06F9/324 , G06F9/321 , G06F9/322 , G06F9/325
摘要： An electronic calculator or microprocessor system of a type preferably having keyboard input and the visual display is implemented with a semiconductor chip having an arithmetic unit, an address register responsive to the input, an instruction word memory for storing a number of instruction words and addressable in response to the address stored in the address register and an, instruction word decoder circuit for decoding instruction words outputted from the instruction word memory and for controlling the arithmetic unit in response thereto. An indirect addressing system includes an auxiliary register coupled to the output of the arithmetic unit for storing at least a portion of a word of numeric data outputted by the arithmetic unit and a branch logic system responsive to the decoding of a particular instruction word by the instruction word decoder logic for causing the address register to branch to a location defined by the contents of the auxiliary register.
摘要翻译：优选地具有键盘输入和视觉显示的类型的电子计算器或微处理器系统利用具有运算单元的半导体芯片，响应于输入的地址寄存器来实现，指令字存储器用于存储多个指令字并且可寻址对存储在地址寄存器中的地址的响应;以及指令字解码器电路，用于对从指令字存储器输出的指令字进行解码，并响应于此控制算术单元。间接寻址系统包括耦合到运算单元的输出的辅助寄存器，用于存储由运算单元输出的数字数据的字的至少一部分，以及分支逻辑系统，其响应于指令对特定指令字的解码字解码器逻辑，用于使地址寄存器分支到由辅助寄存器的内容定义的位置。

10. 发明授权

US4006455A Error correction system in a programmable calculator 失效
标题翻译：可编程计算器中的纠错系统
公开(公告)号：US4006455A
公开(公告)日：1977-02-01
申请号：US622288
申请日：1975-10-10
申请人： Stephen P. Hamilton
发明人： Stephen P. Hamilton
IPC分类号： G06F11/16 , G11B20/10 , G06K5/00
CPC分类号： G11B20/10009 , G06F11/1612
摘要： An error correction system is particularly suitable for user programmable calculators which may be programmed to perform a series of functions on data entries by means of a series of program steps entered into the calculator from a storage media such as recorded magnetic cards or the like. Data is stored in one or more pairs of tracks on the recording media with the first track of each pair for storing binary zeros and a second track of each pair for storing binary ones. Each time a binary zero is present, an alternating transition negative to positive or positive to negative appears on the zero's track of the storage media and each time a one is present an alternating transition negative to positive or positive to negative appears on the one's track of the storage media. For reading the data stored on the storage media, means such as a data latch is provided for each track for storing the direction of the previous transition positive to negative or negative to positive for that track and means for comparing the direction of such previous transition with the direction of the present transition. Whenever it is determined that the state of a bit of data is missing on a pair of tracks, i.e., no transition stored on either track for a given bit, the transitions located prior to, and following said missing bit will indicate the track on which the data bit should have been stored and hence the state of the missing bit. In an embodiment in which at least two pairs of tracks are utilized, the ORed output from the first pair of tracks may be compared to the ORed output from the second pair of tracks such that whenever a bit appears for the first pair but not the second pair it is determined that a bit is missing for the second pair.
摘要翻译：误差校正系统特别适用于用户可编程计算器，其可以被编程为通过从诸如记录的磁卡等的存储介质输入到计算器中的一系列程序步骤来对数据输入执行一系列功能。数据被存储在记录介质上的一对或多对轨道中，每对的第一轨道用于存储二进制零，并且每对的第二轨道用于存储二进制零。每当存在二进制零时，在存储介质的零轨迹上出现负到正或负到负的交替转变，并且每次存在一个存在的情况下，在一个轨迹上出现负向正或负到负的交替转变存储介质。为了读取存储在存储介质上的数据，为每个磁道提供诸如数据锁存器的装置，用于将先前转换的方向存储为对于该磁道为负或负的正或负，以及用于将先前转换的方向与目前转型的方向。无论何时确定在一对轨道上丢失一位数据的状态，即，对于给定位，存储在任一轨道上的转换不存在，则位于所述丢失位之前和之后的转换将指示其上的轨道应该存储数据位，因此应该丢失位的状态。在其中使用至少两对磁道的实施例中，可以将来自第一对磁道的或运算输出与来自第二对磁道的或运算输出进行比较，使得每当第一对出现位而不是第二对时，对确定第二对丢失了一个位。

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