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    • 4. 发明授权
    • Nucleic acids encoding a galacturonosyl tranferase enzyme (GALAT1) from arabidopsis
    • 编码来自拟南芥的半乳糖醛酸转移酶(GALAT1)的核酸
    • US07619077B2
    • 2009-11-17
    • US10544180
    • 2004-02-05
    • Debra MohnenJason Dwight SterlingRon Lou DoongVenkata Siva Kumar KolliMichael G. Hahn
    • Debra MohnenJason Dwight SterlingRon Lou DoongVenkata Siva Kumar KolliMichael G. Hahn
    • C07H21/04C12N15/82A01H5/00
    • C12N9/1051C12N15/8245
    • The invention provides an isolated nucleic acid molecule encoding the polypeptide GALAT1 having galacturonosyltransferase (GalAT) activity. The Arabidopsis GALAT1 sequence disclosed represents the first pectin biosynthetic glycosyltransferase gene isolated from plants. The invention further provides 14 GALAT and 10 GALAT-like gene superfamily members. The identification of the GALAT gene superfamily offers new opportunities to modulate pectin synthesis in vivo and in vitro by modulating the GALAT gene, for example, transgenic plants that produce modified pectins can be generated by altering the GALAT gene. Since modified pectins are predicted to affect plant growth, development, and plant defense responses, the transgenic plants are expected to have improved agricultural value. The modified pectins isolated from such transgenic plants are useful as gelling and stabilizing agents in the food, neutraceutical, and pharmaceutical industries. The expressed proteins, and variants thereof, of the GALAT superfamily are useful to produce in vitro modified pectins of commercial value.
    • 本发明提供了编码具有半乳糖醛酸转移酶(GalAT)活性的多肽GALAT1的分离的核酸分子。 所公开的拟南芥GALAT1序列代表从植物分离的第一个果胶生物合成糖基转移酶基因。 本发明还提供14个GALAT和10个GALAT样基因超家族成员。 GALAT基因超家族的鉴定提供了通过调节GALAT基因在体内和体外调节果胶合成的新机会,例如,可以通过改变GALAT基因产生产生修饰的果胶的转基因植物。 由于修饰的果胶预测会影响植物生长发育和植物防御反应,因此转基因植物预计将具有改善的农业价值。 从这些转基因植物分离的修饰的果胶可用作食品,药物和制药工业中的胶凝和稳定剂。 GALAT超家族的表达蛋白及其变异体可用于产生具有商业价值的体外修饰果胶。
    • 5. 发明授权
    • Ultra-low noise port output driver circuit
    • 超低噪声端口输出驱动电路
    • US5170073A
    • 1992-12-08
    • US782395
    • 1991-10-24
    • Michael G. HahnJoseph H. SalmonRobert E. Larsen
    • Michael G. HahnJoseph H. SalmonRobert E. Larsen
    • H03K17/16
    • H03K17/164
    • A circuit for providing digital output signals carrying large amounts of currents without generating large transients including apparatus for providing a first current path for providing current at a first rate and a first polarity, apparatus for providing a second current path for providing current at the first rate and the first polarity after a first delay, and apparatus for providing a third current path for providing current of the first polarity at a rate greater than the first rate and sufficient for a load connected thereto after a second delay equal to the first delay whereby the current available at the load has built to a level sufficient to sustain the load prior to the provision of the third current.
    • 一种用于提供承载大量电流的数字输出信号而不产生大的瞬变的电路,包括用于提供用于以第一速率和第一极性提供电流的第一电流路径的装置,用于提供用于以第一速率提供电流的第二电流路径的装置 以及第一延迟后的第一极性的装置,以及用于提供第三电流路径的装置,用于以比第一速率大的速率提供第一极性的电流,并且在等于第一延迟的第二延迟之后足以连接到其上的负载 在负载下可用的电流已建立到足以在提供第三电流之前维持负载的电平。
    • 6. 发明授权
    • Asynchronous reset scheme for ultra-low noise port tri-state output
driver circuit
    • 超低噪声端口三态输出驱动电路的异步复位方案
    • US5216289A
    • 1993-06-01
    • US782680
    • 1991-10-24
    • Michael G. HahnJoseph H. SalmonJeffery D. Wilson
    • Michael G. HahnJoseph H. SalmonJeffery D. Wilson
    • H03K17/16
    • H03K17/164
    • A circuit for providing digital output signals carrying large amounts of currents without generating large transients at an output terminal connected to a load comprising apparatus for providing gradually increasing amounts of current of a first polarity to the output terminal, apparatus for providing gradually increasing amounts of current of a second polarity to the output terminal, apparatus for utilizing the apparatus for providing gradually increasing amounts of current of a first polarity to the output terminal to place the output terminal at a voltage level required for input signals, apparatus for providing a high impedance path to hold the output terminal at the voltage level required for input signals, and apparatus for disabling the apparatus for providing gradually increasing amounts of current of a first polarity and the apparatus for providing gradually increasing amounts of current of a second polarity to the output terminal.
    • 一种电路,用于提供承载大量电流的数字输出信号,而不在连接到负载的输出端产生大的瞬变,所述负载包括用于向输出端提供逐渐增加的第一极性的电流的装置,用于逐渐增加电流量的装置 对输出端子具有第二极性的装置,用于利用该装置向输出端子逐渐增加第一极性电流的装置,以将输出端子置于输入信号所需的电压电平的装置,用于提供高阻抗路径的装置 将输出端子保持在输入信号所需的电压电平,以及用于禁止提供第一极性逐渐增加的电流的装置的装置和用于向输出端子逐渐增加第二极性电流的装置。
    • 7. 发明授权
    • Method and apparatus for eliminating latch propagation delays in an
alignment unit for use in a fractional bus architecture
    • 用于消除用于分数总线架构的对准单元中的锁存器传播延迟的方法和装置
    • US5701447A
    • 1997-12-23
    • US508831
    • 1995-07-28
    • Michael G. Hahn
    • Michael G. Hahn
    • G06F1/12G06F13/40
    • G06F1/12G06F13/405
    • An alignment unit is provided for aligning signals transmitted between a core clock domain and a bus clock domain. The alignment unit includes at least one alignment latch connected along each signal path between the core and bus clock domains. For critical path signal lines, the alignment unit also includes a latch bypass to allow critical signals to bypass the latch in circumstances when the core and bus clock signals are already aligned. The bypass mechanism includes a multiplexer which transmits the critical path signal through a tristate buffer if the clock signals are aligned or through a latch and a tristate buffer if the clock signals are unaligned. By bypassing the latch when the signals are aligned, latch propagation delays are avoided. Method and apparatus embodiments are disclosed.
    • 提供对准单元以对准在核心时钟域和总线时钟域之间传输的信号。 对准单元包括沿着核心和总线时钟域之间的每个信号路径连接的至少一个对准锁存器。 对于关键路径信号线,对准单元还包括锁存旁路,以在核心和总线时钟信号已经对准的情况下允许关键信号绕过锁存器。 旁路机构包括多路复用器,如果时钟信号被对准,则通过三态缓冲器传送关键路径信号,或者如果时钟信号未对齐,则通过锁存器和三态缓冲器传送关键路径信号。 当信号对齐时,通过旁路锁存器,避免了锁存器传播延迟。 公开了方法和设备实施例。