专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080040638A1 Evaluation Circuit and Method for Detecting and/or Locating Faulty Data Words in a Data Stream Tn 有权
标题翻译：用于检测和/或定位数据流中的故障数据字的评估电路和方法
公开(公告)号：US20080040638A1
公开(公告)日：2008-02-14
申请号：US10577288
申请日：2004-10-22
申请人： Michael Goessel , Andreas Leininger , Heinz Mattes , Sebastian Sattler
发明人： Michael Goessel , Andreas Leininger , Heinz Mattes , Sebastian Sattler
IPC分类号： G06F11/22
CPC分类号： G01R31/31932 , G01R31/31703
摘要： An evaluation circuit and method for detecting faulty data words in a data stream is disclosed. In one embodiment the evaluation circuit according to the invention includes a first linear automaton circuit and also a second linear automaton circuit connected in parallel, each having a set of states z, which have a common input line for receiving a data stream Tn. The first linear automaton circuit and the second linear automaton circuit are designed such that a first signature and a second signature, respectively, can be calculated. Situated downstream of the two linear automaton circuits are respectively a first logic combination gate and a second logic combination gate, which compare the signature respectively calculated by the linear automaton circuit with a predeterminable good signature and output a comparison value.
摘要翻译：公开了一种用于检测数据流中的错误数据字的评估电路和方法。在一个实施例中，根据本发明的评估电路包括并联连接的第一线性自动机电路和第二线性自动机电路，每个具有一组状态z，其具有用于接收数据流T n 。第一线性自动机电路和第二线性自动机电路被设计成可以分别计算第一签名和第二签名。位于两个线性自动机电路的下游分别是第一逻辑组合门和第二逻辑组合门，其将由线性自动机电路分别计算的签名与可预定的良好签名进行比较并输出比较值。

2. 发明授权

US08312332B2 Device and method for testing and for diagnosing digital circuits 有权
标题翻译：用于测试和诊断数字电路的装置和方法
公开(公告)号：US08312332B2
公开(公告)日：2012-11-13
申请号：US11364369
申请日：2006-03-01
申请人： Andreas Leininger , Michael Goessel
发明人： Andreas Leininger , Michael Goessel
IPC分类号： G01R31/28
CPC分类号： G01R31/31928 , G01R31/31922 , G01R31/31937 , G11C29/40
摘要： A test apparatus includes a test input signal generator that generates a test input signal of word width N, and terminals that connect to inputs and outputs of an electrical circuit to be tested. The electrical circuit includes N digital test inputs and M digital test outputs. The terminals for the test inputs are connected to the test input signal and an electrical circuit is driven such that it outputs at its test outputs data with a macro clock cycle T of length L as test response. A compactor includes M inputs that are connected to the terminals for the test outputs of the circuit to be tested. The compactor compacts the test response with a micro clock cycle t of length l and outputs a data word of width m, where the length L is at least twice as large as the length l.
摘要翻译：测试装置包括测试输入信号发生器，其产生字宽N的测试输入信号，以及连接到要测试的电路的输入和输出的端子。电路包括N个数字测试输入和M个数字测试输出。测试输入的端子连接到测试输入信号，并且驱动电路，使得其测试输出以长度为L的宏时钟周期T作为测试响应输出数据。压实机包括连接到端子的M个输入端，用于待测电路的测试输出。压实机用长度为l的微时钟周期t压缩测试响应，并输出宽度为m的数据字，其中长度L至少是长度l的两倍。

3. 发明申请

US20080263421A1 Electrical Diagnostic Circuit and Method for the Testing and/or the Diagnostic Analysis of an Integrated Circuit 有权
标题翻译：电气诊断电路和集成电路测试和/或诊断分析方法
公开(公告)号：US20080263421A1
公开(公告)日：2008-10-23
申请号：US10568842
申请日：2004-08-11
申请人： Michael Goessel , Andreas Leininger
发明人： Michael Goessel , Andreas Leininger
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318547
摘要： An electrical diagnostic circuit and testing method is disclosed. In one embodiment the electrical diagnostic circuit for testing an integrated circuit includes a number of external inputs, a plurality of essentially similar, series-connected switching units and a circuit output. The switching units are constructed to be controllable in such a manner that an input signal present at the internal input of the switching unit, in dependence on a control signal of the switching unit, can either be forwarded unchanged to the internal input of the switching unit in each case arranged downstream, or can be combined with the test signal in each case present at the external input.
摘要翻译：公开了电诊断电路和测试方法。在一个实施例中，用于测试集成电路的电诊断电路包括多个外部输入，多个基本相似的串联连接的开关单元和电路输出。开关单元被构造为可控制的，使得根据开关单元的控制信号存在于开关单元的内部输入端的输入信号可以被不变地转发到开关单元的内部输入端在每种情况下布置在下游，或者可以在外部输入处存在的每种情况下与测试信号组合。

4. 发明授权

US08060800B2 Evaluation circuit and method for detecting and/or locating faulty data words in a data stream Tn 有权
标题翻译：用于检测和/或定位数据流Tn中的故障数据字的评估电路和方法
公开(公告)号：US08060800B2
公开(公告)日：2011-11-15
申请号：US10577288
申请日：2004-10-22
申请人： Michael Goessel , Andreas Leininger , Heinz Mattes , Sebastian Sattler
发明人： Michael Goessel , Andreas Leininger , Heinz Mattes , Sebastian Sattler
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31932 , G01R31/31703
摘要： An evaluation circuit and method for detecting faulty data words in a data stream is disclosed. In one embodiment the evaluation circuit according to the invention includes a first linear automaton circuit and also a second linear automaton circuit connected in parallel, each having a set of states z, which have a common input line for receiving a data stream Tn. The first linear automaton circuit and the second linear automaton circuit are designed such that a first signature and a second signature, respectively, can be calculated. Situated downstream of the two linear automaton circuits are respectively a first logic combination gate and a second logic combination gate, which compare the signature respectively calculated by the linear automaton circuit with a predeterminable good signature and output a comparison value.
摘要翻译：公开了一种用于检测数据流中的错误数据字的评估电路和方法。在一个实施例中，根据本发明的评估电路包括并联连接的第一线性自动机电路和第二线性自动机电路，每个具有一组状态z，其具有用于接收数据流Tn的公共输入线。第一线性自动机电路和第二线性自动机电路被设计成可以分别计算第一签名和第二签名。位于两个线性自动机电路的下游分别是第一逻辑组合门和第二逻辑组合门，其将由线性自动机电路分别计算的签名与可预定的良好签名进行比较并输出比较值。

5. 发明申请

US20070168814A1 Device and method for testing and for diagnosing digital circuits 有权
标题翻译：用于测试和诊断数字电路的装置和方法
公开(公告)号：US20070168814A1
公开(公告)日：2007-07-19
申请号：US11364369
申请日：2006-03-01
申请人： Andreas Leininger , Michael Goessel
发明人： Andreas Leininger , Michael Goessel
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31928 , G01R31/31922 , G01R31/31937 , G11C29/40
摘要： A test apparatus includes a test input signal generator that generates a test input signal of word width N, and terminals that connect to inputs and outputs of an electrical circuit to be tested. The electrical circuit includes N digital test inputs and M digital test outputs. The terminals for the test inputs are connected to the test input signal and an electrical circuit is driven such that it outputs at its test outputs data with a macro clock cycle T of length L as test response. A compactor includes M inputs that are connected to the terminals for the test outputs of the circuit to be tested. The compactor compacts the test response with a micro clock cycle t of length l and outputs a data word of width m, where the length L is at least twice as large as the length l.
摘要翻译：测试装置包括测试输入信号发生器，其产生字宽N的测试输入信号，以及连接到要测试的电路的输入和输出的端子。电路包括N个数字测试输入和M个数字测试输出。测试输入的端子连接到测试输入信号，并且驱动电路，使得其测试输出以长度为L的宏时钟周期T作为测试响应输出数据。压实机包括连接到端子的M个输入端，用于待测电路的测试输出。压实机用长度为l的微时钟周期t压缩测试响应，并输出宽度为m的数据字，其中长度L至少是长度l的两倍。

6. 发明授权

US07814384B2 Electrical diagnostic circuit and method for the testing and/or the diagnostic analysis of an integrated circuit 有权
标题翻译：用于集成电路的测试和/或诊断分析的电气诊断电路和方法
公开(公告)号：US07814384B2
公开(公告)日：2010-10-12
申请号：US10568842
申请日：2004-08-11
申请人： Michael Goessel , Andreas Leininger
发明人： Michael Goessel , Andreas Leininger
IPC分类号： G01R31/28 , G01R31/26 , G11C29/00 , G06F17/50
CPC分类号： G01R31/318547
摘要： An electrical diagnostic circuit and testing method is disclosed. In one embodiment, the electrical diagnostic circuit for testing an integrated circuit includes a number of external inputs, a plurality of essentially similar, series-connected switching units and a circuit output. The switching units are constructed to be controllable in such a manner that an input signal present at the internal input of the switching unit, in dependence on a control signal of the switching unit, can either be forwarded unchanged to the internal input of the switching unit in each case arranged downstream, or can be combined with the test signal in each case present at the external input.
摘要翻译：公开了电诊断电路和测试方法。在一个实施例中，用于测试集成电路的电诊断电路包括多个外部输入，多个基本相似的串联连接的开关单元和电路输出。开关单元被构造为可控制的，使得根据开关单元的控制信号存在于开关单元的内部输入端的输入信号可以被不变地转发到开关单元的内部输入端在每种情况下布置在下游，或者可以在外部输入处存在的每种情况下与测试信号组合。

7. 发明申请

US20140245106A1 MEMEROY CIRCUITS, METHOD FOR ACCESSING A MEMORY AND METHOD FOR REPAIRING A MEMORY 有权
标题翻译： MEMORYY CIRCUITS，用于访问存储器的方法和用于修复存储器的方法
公开(公告)号：US20140245106A1
公开(公告)日：2014-08-28
申请号：US13773832
申请日：2013-02-22
申请人： Andreas Leininger , Michael Richter , Stefan Franz
发明人： Andreas Leininger , Michael Richter , Stefan Franz
IPC分类号： G06F11/10
CPC分类号： G06F11/1008 , G06F11/1016 , G06F11/1048 , G11C7/1006 , G11C29/42 , H03M13/09 , H03M13/152 , H03M13/2906
摘要： A memory circuit is described comprising a plurality of memory elements, wherein each memory element is configured to store one data element of a plurality of data elements, an error correction information memory configured to store joint error correction information of the plurality of data elements, for each memory element, an error detection information memory storing error detection information for the data element stored in the memory element and a memory access circuit configured to, for an access to a memory element of the plurality of memory elements, check whether the error detection information for the data element stored in the memory element indicates an error of the data element stored in the memory element and, depending on whether the error detection information for the data element stored in the memory element indicates an error of the data element stored in the memory element, to process the error correction information for the access.
摘要翻译：描述了包括多个存储器元件的存储器电路，其中每个存储器元件被配置为存储多个数据元素中的一个数据元素，错误校正信息存储器被配置为存储多个数据元素的联合纠错信息，用于每个存储器元件，存储存储在存储元件中的数据元素的错误检测信息的错误检测信息存储器以及用于访问多个存储器元件的存储元件的存储器访问电路，检查错误检测信息对于存储在存储元件中的数据元素，指示存储在存储元件中的数据元素的错误，并且根据存储在存储元件中的数据元素的错误检测信息是否指示存储在存储器中的数据元素的错误元素，以处理访问的纠错信息。

8. 发明授权

US09619318B2 Memory circuits, method for accessing a memory and method for repairing a memory 有权
公开(公告)号：US09619318B2
公开(公告)日：2017-04-11
申请号：US13773832
申请日：2013-02-22
申请人： Andreas Leininger , Michael Richter , Stefan Franz
发明人： Andreas Leininger , Michael Richter , Stefan Franz
IPC分类号： G11C29/00 , G06F11/10 , G11C7/10 , G11C29/42 , H03M13/29 , H03M13/09 , H03M13/15
CPC分类号： G06F11/1008 , G06F11/1016 , G06F11/1048 , G11C7/1006 , G11C29/42 , H03M13/09 , H03M13/152 , H03M13/2906
摘要： A memory circuit is described comprising a plurality of memory elements, wherein each memory element is configured to store one data element of a plurality of data elements, an error correction information memory configured to store joint error correction information of the plurality of data elements, for each memory element, an error detection information memory storing error detection information for the data element stored in the memory element and a memory access circuit configured to, for an access to a memory element of the plurality of memory elements, check whether the error detection information for the data element stored in the memory element indicates an error of the data element stored in the memory element and, depending on whether the error detection information for the data element stored in the memory element indicates an error of the data element stored in the memory element, to process the error correction information for the access.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式