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1. 发明申请

US20080040638A1 Evaluation Circuit and Method for Detecting and/or Locating Faulty Data Words in a Data Stream Tn 有权
标题翻译：用于检测和/或定位数据流中的故障数据字的评估电路和方法
公开(公告)号：US20080040638A1
公开(公告)日：2008-02-14
申请号：US10577288
申请日：2004-10-22
申请人： Michael Goessel , Andreas Leininger , Heinz Mattes , Sebastian Sattler
发明人： Michael Goessel , Andreas Leininger , Heinz Mattes , Sebastian Sattler
IPC分类号： G06F11/22
CPC分类号： G01R31/31932 , G01R31/31703
摘要： An evaluation circuit and method for detecting faulty data words in a data stream is disclosed. In one embodiment the evaluation circuit according to the invention includes a first linear automaton circuit and also a second linear automaton circuit connected in parallel, each having a set of states z, which have a common input line for receiving a data stream Tn. The first linear automaton circuit and the second linear automaton circuit are designed such that a first signature and a second signature, respectively, can be calculated. Situated downstream of the two linear automaton circuits are respectively a first logic combination gate and a second logic combination gate, which compare the signature respectively calculated by the linear automaton circuit with a predeterminable good signature and output a comparison value.
摘要翻译：公开了一种用于检测数据流中的错误数据字的评估电路和方法。在一个实施例中，根据本发明的评估电路包括并联连接的第一线性自动机电路和第二线性自动机电路，每个具有一组状态z，其具有用于接收数据流T n 。第一线性自动机电路和第二线性自动机电路被设计成可以分别计算第一签名和第二签名。位于两个线性自动机电路的下游分别是第一逻辑组合门和第二逻辑组合门，其将由线性自动机电路分别计算的签名与可预定的良好签名进行比较并输出比较值。

2. 发明授权

US07206712B2 Test apparatus and test method for mixed-signal semiconductor components 有权
标题翻译：混合信号半导体元件的测试装置和测试方法
公开(公告)号：US07206712B2
公开(公告)日：2007-04-17
申请号：US11395528
申请日：2006-04-03
申请人： Sebastian Sattler , Heinz Mattes
发明人： Sebastian Sattler , Heinz Mattes
IPC分类号： G01R27/28
CPC分类号： G01R31/3167 , G01R31/31924 , G01R31/31926
摘要： A semiconductor component is tested by providing a tester, a loadboard and an evaluation apparatus. The semiconductor component is operated using a test sequence, with the reference signal being applied to the semiconductor component or to the evaluation apparatus.
摘要翻译：通过提供测试器，加载板和评估装置来测试半导体部件。使用测试序列来操作半导体部件，其中参考信号被施加到半导体部件或评估装置。

3. 发明申请

US20060238392A1 Test apparatus and test method for mixed-signal semiconductor components 有权
标题翻译：混合信号半导体元件的测试装置和测试方法
公开(公告)号：US20060238392A1
公开(公告)日：2006-10-26
申请号：US11395528
申请日：2006-04-03
申请人： Sebastian Sattler , Heinz Mattes
发明人： Sebastian Sattler , Heinz Mattes
IPC分类号： H03M1/10
CPC分类号： G01R31/3167 , G01R31/31924 , G01R31/31926
摘要： A semiconductor component is tested by providing a tester, a loadboard and an evaluation apparatus. The loadboard provided with the semiconductor component, and a reference signal is generated according to the following: providing a number n of periods for which signal values are generated, where n is a natural number greater than 1; a number m of samples is provided, where n and m are prime numbers; a step size h is stipulated on the basis of the equation h=n*360°/m; the initial value for the cosine x0 and for the sine y0 is stipulated; the cosine value xi+1 and the sine value yi+1 for the following time (i+1)*h are calculated from the sine value yi and the cosine value xi for the present time i*h, the calculation being performed in an electrical circuit which is situated on the loadboard or in the semiconductor component to be tested; and the previous calculation is repeated in a loop with a control variable i which runs from 0 to m. The semiconductor component is operated using a test sequence, with the reference signal being applied to the semiconductor component or to the evaluation apparatus.
摘要翻译：通过提供测试器，加载板和评估装置来测试半导体部件。设置有半导体元件的装载板和参考信号根据以下产生：提供产生信号值的n个周期，其中n是大于1的自然数; 提供m个样本，其中n和m是素数; 基于等式h = n * 360°/ m规定步长h; 规定余弦x <0>和正弦y <0>的初始值; 对于随后的时间（i + 1）* h的余弦值x i + 1和正弦值y i + 1＆lt; i＆gt;从正弦值y i＆lt; i＆gt;和余弦值x i i i i h h，计算是在位于加载板上或要测试的半导体部件中的电路中执行的; 并且以从0到m的控制变量i的循环重复先前的计算。使用测试序列来操作半导体部件，其中参考信号被施加到半导体部件或评估装置。

4. 发明授权

US08060800B2 Evaluation circuit and method for detecting and/or locating faulty data words in a data stream Tn 有权
标题翻译：用于检测和/或定位数据流Tn中的故障数据字的评估电路和方法
公开(公告)号：US08060800B2
公开(公告)日：2011-11-15
申请号：US10577288
申请日：2004-10-22
申请人： Michael Goessel , Andreas Leininger , Heinz Mattes , Sebastian Sattler
发明人： Michael Goessel , Andreas Leininger , Heinz Mattes , Sebastian Sattler
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31932 , G01R31/31703
摘要： An evaluation circuit and method for detecting faulty data words in a data stream is disclosed. In one embodiment the evaluation circuit according to the invention includes a first linear automaton circuit and also a second linear automaton circuit connected in parallel, each having a set of states z, which have a common input line for receiving a data stream Tn. The first linear automaton circuit and the second linear automaton circuit are designed such that a first signature and a second signature, respectively, can be calculated. Situated downstream of the two linear automaton circuits are respectively a first logic combination gate and a second logic combination gate, which compare the signature respectively calculated by the linear automaton circuit with a predeterminable good signature and output a comparison value.
摘要翻译：公开了一种用于检测数据流中的错误数据字的评估电路和方法。在一个实施例中，根据本发明的评估电路包括并联连接的第一线性自动机电路和第二线性自动机电路，每个具有一组状态z，其具有用于接收数据流Tn的公共输入线。第一线性自动机电路和第二线性自动机电路被设计成可以分别计算第一签名和第二签名。位于两个线性自动机电路的下游分别是第一逻辑组合门和第二逻辑组合门，其将由线性自动机电路分别计算的签名与可预定的良好签名进行比较并输出比较值。

5. 发明申请

US20070089010A1 Test apparatus for digitized test responses, method for testing semiconductor devices and diagnosis method for a semiconductor device 有权
标题翻译：用于数字化测试响应的测试装置，半导体器件测试方法和半导体器件的诊断方法
公开(公告)号：US20070089010A1
公开(公告)日：2007-04-19
申请号：US11534005
申请日：2006-09-21
申请人： Stephane Kirmser , Heinz Mattes , Sebastian Sattler
发明人： Stephane Kirmser , Heinz Mattes , Sebastian Sattler
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318371 , H03M1/1085 , H03M1/12
摘要： A test apparatus for testing digitized test responses has a generator (2) and a signal extractor (3). The generator (2) uses direct digital synthesis to generate a set of n digital reference signals (xk, yk) which are orthogonal to one another. In this case, n is a natural number greater than 1. The signal extractor (3) contains a test input and a plurality of reference inputs. The test input receives a digitized test response (E) and the reference inputs are connected to the reference signals (xk, yk) which are generated by the generator (2). The signal extractor (3) generates scalar products from a respective reference signal (xk, yk) and the test response (E) and uses said products to calculate whether a combination of reference signals (xk, yk) is contained in the test response (E).
摘要翻译：用于测试数字化测试响应的测试装置具有发生器（2）和信号提取器（3）。发生器（2）使用直接数字合成来产生彼此正交的一组n个数字参考信号（x，k，y，k）。在这种情况下，n是大于1的自然数。信号提取器（3）包含测试输入和多个参考输入。测试输入接收数字化的测试响应（E），并且参考输入连接到由发生器（2）产生的参考信号（x，k，y，k））。信号提取器（3）从相应的参考信号（x k，y k k）和测试响应（E）产生标量积，并且使用所述乘积来计算是否在测试响应（E）中包含参考信号（x，k，y，k）的组合。

6. 发明申请

US20050241362A1 Method and device for detecting period length fluctuations of periodic signals 有权
标题翻译：用于检测周期信号周期长度波动的方法和装置
公开(公告)号：US20050241362A1
公开(公告)日：2005-11-03
申请号：US10525163
申请日：2003-08-08
申请人： Hans-Dieter Oberle , Sebastian Sattler
发明人： Hans-Dieter Oberle , Sebastian Sattler
IPC分类号： G01R23/10 , G01R29/027 , H04L25/02 , G01R29/02
CPC分类号： H04L25/0262 , G01R23/10 , G01R29/0273
摘要： To determine the period length of a first signal, the length is measured by counting the periods of a second signal with a shorter period length. To measure the fluctuations of the period length of the first signal whilst also taking into account the fluctuations of the period length of the second signal, the measurement is carried out for two different values of the period length of the second signal. Both the fluctuations of the period length of the first signal and the accumulated fluctuations of the period length of the second signal are calculated independently of one another from the two values. The method enables the period length fluctuations of a first signal that originates from a phase-locked loop to be detected.
摘要翻译：为了确定第一信号的周期长度，通过对具有较短周期长度的第二信号的周期进行计数来测量长度。为了测量第一信号的周期长度的波动，同时考虑到第二信号的周期长度的波动，对于第二信号的周期长度的两个不同的值进行测量。从两个值彼此独立地计算第一信号的周期长度的波动和第二信号的周期长度的累积波动。该方法使得能够检测来自锁相环的第一信号的周期长度波动。

7. 发明授权

US06944810B2 Method and apparatus for the testing of input/output drivers of a circuit 有权
标题翻译：用于测试电路的输入/输出驱动器的方法和装置
公开(公告)号：US06944810B2
公开(公告)日：2005-09-13
申请号：US10213728
申请日：2002-08-06
申请人： Hans-Dieter Oberle , Sebastian Sattler
发明人： Hans-Dieter Oberle , Sebastian Sattler
IPC分类号： G01R31/317 , G01R31/3185 , G01R31/319 , G01R31/28
CPC分类号： G01R31/31715 , G01R31/318572 , G01R31/31905
摘要： In order to test the input and output drivers of a circuit, in particular an integrated semiconductor circuit, a method and apparatus is provided to connect the input or output drivers assigned to individual signal connections of the circuit to be tested in series to a ring oscillator or to an open chain with the oscillation of the ring oscillator or the delay time being evaluated. By providing appropriate controllable switches, the configuration of the ring oscillator or the chain can be altered variably depending on the input or output drivers to be tested respectively. In this way an “at-speed” and “leakage” test of all input and output drivers, including the external signal connections, are possible with all of these having to be connected to a rapid test unit.
摘要翻译：为了测试电路的输入和输出驱动器，特别是集成半导体电路，提供了一种方法和装置，用于将分配给待测试电路的各个信号连接的输入或输出驱动器串联连接到环形振荡器或者与环形振荡器的振荡或延迟时间进行评估的开链。通过提供适当的可控开关，环形振荡器或链条的配置可以根据要分别测试的输入或输出驱动器而变化。以这种方式，所有输入和输出驱动器（包括外部信号连接）的“速度”和“泄漏”测试都是可能的，其中所有这些都必须连接到快速测试单元。

8. 发明授权

US07720645B2 Test apparatus for digitized test responses, method for testing semiconductor devices and diagnosis method for a semiconductor device 有权
标题翻译：用于数字化测试响应的测试装置，半导体器件测试方法和半导体器件的诊断方法
公开(公告)号：US07720645B2
公开(公告)日：2010-05-18
申请号：US11534005
申请日：2006-09-21
申请人： Stephane Kirmser , Heinz Mattes , Sebastian Sattler
发明人： Stephane Kirmser , Heinz Mattes , Sebastian Sattler
IPC分类号： G01R31/28
CPC分类号： G01R31/318371 , H03M1/1085 , H03M1/12
摘要： A test apparatus for testing digitized test responses has a generator and a signal extractor. The generator uses direct digital synthesis to generate a set of n digital reference signals which are orthogonal to one another. In this case, n is a natural number greater than 1. The signal extractor contains a test input and reference inputs. The test input receives a digitized test response and the reference inputs are connected to the reference signals which are generated by the generator. The signal extractor generates scalar products from a respective reference signal and the test response and uses the products to calculate whether a combination of reference signals is contained in the test response.
摘要翻译：用于测试数字化测试响应的测试装置具有发生器和信号提取器。发生器使用直接数字合成来产生彼此正交的一组n个数字参考信号。在这种情况下，n是大于1的自然数。信号提取器包含测试输入和参考输入。测试输入接收数字化的测试响应，参考输入连接到由发生器产生的参考信号。信号提取器从相应的参考信号和测试响应产生标量产物，并使用产品来计算参考信号的组合是否包含在测试响应中。

9. 发明授权

US07558991B2 Device and method for measuring jitter 有权
标题翻译：用于测量抖动的装置和方法
公开(公告)号：US07558991B2
公开(公告)日：2009-07-07
申请号：US11440441
申请日：2006-05-25
申请人： Heinz Mattes , Sebastian Sattler
发明人： Heinz Mattes , Sebastian Sattler
IPC分类号： G11B20/20 , G01R31/28 , G01R29/26 , H04B3/26
CPC分类号： H04L1/205 , G01R31/31709 , H04B3/462 , H04B14/044 , H04B17/364 , H04J2203/0062
摘要： A test device contains a data pattern generator for providing a delta-sigma-modulated data stream sampled with a sampling frequency fs at its output. A phase modulator generates a test clock subjected to jitter and having the clock frequency ft at its output. The output of the data pattern generator is connected to a terminal for connection to a data input of a semiconductor component to be tested. The output of the phase modulator is connected to a terminal for connection to a clock input of a semiconductor component to be tested. An evaluation device determines the jitter parameters of the input signal at the input of the data device from the low-frequency component of the input signal. In this case, the low-frequency component contains only frequency components of frequencies which are less than half the sampling frequency fs/2.
摘要翻译：测试装置包含一个数据模式发生器，用于提供在其输出端以采样频率fs采样的Δ-Σ调制数据流。相位调制器产生经受抖动的测试时钟，并在其输出端具有时钟频率ft。数据模式发生器的输出端连接到用于连接到要测试的半导体元件的数据输入端的端子。相位调制器的输出连接到用于连接到要测试的半导体部件的时钟输入的端子。评估装置从输入信号的低频分量确定数据装置的输入处的输入信号的抖动参数。在这种情况下，低频分量仅包含小于采样频率fs / 2的一半的频率的频率分量。

10. 发明授权

US07487060B2 Apparatus and method for tolerance analysis for digital and/or digitized measure values 有权
标题翻译：用于数字和/或数字化测量值的容差分析的装置和方法
公开(公告)号：US07487060B2
公开(公告)日：2009-02-03
申请号：US10546073
申请日：2004-02-04
申请人： Hans-Dieter Oberle , Sebastian Sattler
发明人： Hans-Dieter Oberle , Sebastian Sattler
IPC分类号： G06F19/00
CPC分类号： G01R31/31707 , G01R31/31703 , G01R31/3187 , G06F7/026
摘要： An electric tolerance analysis circuit for digital and digitized measured values has inputs for receiving a measured value, a reference value, and a tolerance value and also an output for transmitting an output value. The electric tolerance analysis circuit also has a checking device for checking the measured value using at least one prescribable tolerance criterion and has an output device for outputting an output value which is obtained from the state of the checking device, depending on whether or not the measured value meets the respective prescribed tolerance criterion.
摘要翻译：用于数字和数字化测量值的电容差分析电路具有用于接收测量值，参考值和公差值的输入端，以及用于传输输出值的输出。电容差分析电路还具有用于使用至少一个可规定的公差标准来检查测量值的检查装置，并且具有输出装置，用于输出从检查装置的状态获得的输出值，这取决于所测量的值符合相应规定的公差标准。

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