专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06239485B1 Reduced cross-talk noise high density signal interposer with power and ground wrap 失效
标题翻译：减少串扰噪声高密度信号插入器与电源和地面包装
公开(公告)号：US06239485B1
公开(公告)日：2001-05-29
申请号：US09315785
申请日：1999-05-20
申请人： Michael G. Peters , Wen-chou Vincent Wang , Yasuhito Takahashi , William Chou , Michael G. Lee , Solomon Beilin
发明人： Michael G. Peters , Wen-chou Vincent Wang , Yasuhito Takahashi , William Chou , Michael G. Lee , Solomon Beilin
IPC分类号： H01L2312
CPC分类号： H05K1/0219 , H01L23/49822 , H01L23/49833 , H01L23/49838 , H01L23/50 , H01L23/5383 , H01L23/5385 , H01L23/5386 , H01L23/552 , H01L2224/16225 , H01L2224/16235 , H01L2924/01004 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/01327 , H01L2924/09701 , H01L2924/10253 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H05K1/141 , H05K1/144 , H05K3/20 , H05K2201/049 , H05K2201/055 , H05K2201/10378 , H01L2924/00
摘要： An interposer for providing power, ground, and signal connections between an integrated circuit chip or chips and a substrate. The inventive interposer includes a signal core and external power/ground connection wrap. The two sections may be fabricated and tested separately, then joined together using z-connection technology. The signal core is formed from a conductive power/ground plane positioned between two dielectric layers. A patterned metal layer is formed on each dielectric layer. The two metal layers are interconnected by a through via or post process. The conductive power/ground plane functions to reduce signal cross-talk between signal lines formed on the two patterned metal layers. The power/ground wrap includes an upper substrate positioned above the signal core and a lower substrate positioned below the signal core. The upper and lower substrates of the power/ground wrap are formed from a dielectric film having a patterned metal layer on both sides, with the patterned layers connected by a through via or post process. The two power/ground wrap substrates may be formed separately or from one substrate which is bent into a desired form (e.g., a “U” shape). The two power/ground substrates are maintained in their proper alignment relative to the signal core and to each other by edge connectors which are also connected to the signal core's intermediary power/ground plane.
摘要翻译：一种用于在集成电路芯片或芯片与基板之间提供电源，接地和信号连接的插入器。本发明的插入器包括信号芯和外部电源/接地连接外壳。这两个部分可以单独制造和测试，然后使用z连接技术连接在一起。信号芯由位于两个电介质层之间的导电电源/接地平面形成。在每个电介质层上形成图案化的金属层。两个金属层通过通孔或后处理相互连接。导电功率/接地面用于减少形成在两个图案化金属层上的信号线之间的信号串扰。电源/接地包裹物包括位于信号芯上方的上基板和位于信号芯下方的下基板。电源/接地线圈的上下基板由两面具有图案化金属层的电介质膜形成，图案化层通过通孔或后工艺连接。两个电源/接地包覆基板可以分开地形成，或者可以从弯曲成所需形状（例如，“U”形状）的一个基板形成。两个电源/接地基板相对于信号芯线保持正确的对准，并通过也连接到信号芯的中间电源/接地平面的边缘连接器彼此保持。

2. 发明授权

US6081026A High density signal interposer with power and ground wrap 有权
标题翻译：高密度信号插入器，具有电源和地面包装
公开(公告)号：US6081026A
公开(公告)日：2000-06-27
申请号：US191755
申请日：1998-11-13
申请人： Wen-chou Vincent Wang , Yasuhito Takahashi , William T. Chou , Michael G. Peters , Michael G. Lee , Solomon Beilin
发明人： Wen-chou Vincent Wang , Yasuhito Takahashi , William T. Chou , Michael G. Peters , Michael G. Lee , Solomon Beilin
IPC分类号： H01L23/498 , H01L23/50 , H01L23/538 , H01L23/552 , H05K1/02 , H05K1/14 , H05K3/20 , H01L23/12 , H01L23/053
CPC分类号： H01L23/5383 , H01L23/49822 , H01L23/49833 , H01L23/49838 , H01L23/50 , H01L23/5385 , H01L23/5386 , H01L23/552 , H05K1/0219 , H01L2224/16225 , H01L2924/00014 , H01L2924/01078 , H01L2924/15311 , H01L2924/3011 , H05K1/141 , H05K1/144 , H05K2201/049 , H05K2201/055 , H05K2201/10378 , H05K3/20
摘要： An interposer for providing power, ground, and signal connections between an integrated circuit chip or chips and a substrate. The interposer includes a signal core and external power/ground connection wrap. The two sections may be fabricated and tested separately, then joined together using z-connection technology. The signal core is a dielectric film with patterned metal on both sides. The two metal layers are interconnected by a through via or post process. The power/ground wrap includes an upper substrate positioned above the signal core and a lower substrate positioned below the signal core. The upper and lower substrates of the power/ground wrap are formed from a dielectric film having a patterned metal layer on both sides connected by a through via or post process. The upper power/ground wrap substrate, signal core, and lower power/ground substrate are interconnected as desired using z-connection technology (e.g., solder or conductive ink). The power/ground layers on the upper substrate can be connected to the power/ground layers on the lower substrate by suitable edge connectors. With an integrated circuit chip or chips connected to the upper layer of the top substrate of the power/ground wrap and a printed circuit board or other mounting substrate connected to the bottom layer of the lower substrate of the wrap, the inventive interposer provides a set of high density and electrically isolated signal, power, and ground interconnections.
摘要翻译：一种用于在集成电路芯片或芯片与基板之间提供电源，接地和信号连接的插入器。插入器包括信号芯和外部电源/接地连接外壳。这两个部分可以单独制造和测试，然后使用z连接技术连接在一起。信号芯是两侧具有图案化金属的电介质膜。两个金属层通过通孔或后处理相互连接。电源/接地包裹物包括位于信号芯上方的上基板和位于信号芯下方的下基板。电源/接地套管的上基板和下基板由具有通过通孔或后工艺连接的两侧上的图案化金属层的电介质膜形成。上电源/地基封装衬底，信号芯和下电源/接地衬底根据需要使用z连接技术（例如焊料或导电油墨）互连。上基板上的电源/接地层可以通过合适的边缘连接器连接到下基板上的电源/接地层。通过将集成电路芯片或芯片连接到电源/接地外壳的顶部基板的上层，以及连接到包装的下基板的底层的印刷电路板或其它安装基板，本发明的插入件提供一组高密度和电隔离的信号，电源和接地互连。

3. 发明授权

US06662443B2 Method of fabricating a substrate with a via connection 失效
标题翻译：用通孔连接制造衬底的方法
公开(公告)号：US06662443B2
公开(公告)日：2003-12-16
申请号：US09935378
申请日：2001-08-22
申请人： William T. Chou , Solomon Beilin , Michael G. Lee , Michael G. Peters , Wen-chou Vincent Wang
发明人： William T. Chou , Solomon Beilin , Michael G. Lee , Michael G. Peters , Wen-chou Vincent Wang
IPC分类号： H01K310
CPC分类号： H05K3/423 , H05K3/0035 , H05K2201/0355 , H05K2201/0394 , H05K2203/0733 , Y10T29/49126 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： A method of fabricating a multilayer interconnected substrate is disclosed. In one embodiment, the method includes providing a structure having a dielectric substrate having a first substantially planar surface and an opposing second substantially planar surface. A first conductive layer is disposed on the first substantially planar surface of the dielectric substrate, and an interface is present between the first conductive layer and the dielectric substrate. A blind via site is formed in the structure, and through the dielectric substrate to the interface between the first conductive layer and the dielectric substrate. The blind via site is filled with a conductive material by an electrolytic plating process.
摘要翻译：公开了一种制造多层互连衬底的方法。在一个实施例中，该方法包括提供具有电介质基底的结构，其具有第一基本上平坦的表面和相对的第二基本上平坦的表面。第一导电层设置在电介质基板的第一基本上平坦的表面上，并且在第一导电层和电介质基板之间存在界面。在该结构中形成盲通孔部位，并且通过电介质基板到第一导电层和电介质基板之间的界面。盲孔通过电镀工艺填充导电材料。

4. 发明授权

US06168972A Flip chip pre-assembly underfill process 失效
标题翻译：倒装芯片预组装底部填充工艺
公开(公告)号：US06168972A
公开(公告)日：2001-01-02
申请号：US09218781
申请日：1998-12-22
申请人： Wen-chou Vincent Wang , Michael G. Peters , Dashun S. Zhou , Yasuhito Takahashi
发明人： Wen-chou Vincent Wang , Michael G. Peters , Dashun S. Zhou , Yasuhito Takahashi
IPC分类号： H01L2148
CPC分类号： H01L24/94 , H01L21/563 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/29 , H01L2224/06102 , H01L2224/11334 , H01L2224/131 , H01L2224/16 , H01L2224/274 , H01L2224/73203 , H01L2224/73204 , H01L2224/83102 , H01L2224/83191 , H01L2224/83192 , H01L2224/83856 , H01L2224/92125 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01009 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/15787 , H01L2924/351 , H01L2224/13099 , H01L2224/29099 , H01L2924/00
摘要： An encapsulation process for flip-chip bonding chips to a substrate encapsulates solder balls on the chip in a separate encapsulation process in which the chip is coated with encapsulation layer and then a portion of the encapsulation layer is removed to expose a portion of the solder balls.
摘要翻译：用于将衬底倒装芯片接合到衬底的封装工艺在单独的封装工艺中封装芯片上的焊球，其中芯片被封装层涂覆，然后去除一部分封装层以暴露焊料球的一部分。

5. 发明授权

US5854534A Controlled impedence interposer substrate 失效
标题翻译：受控阻抗插入器基板
公开(公告)号：US5854534A
公开(公告)日：1998-12-29
申请号：US559369
申请日：1995-11-16
申请人： Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Michael G. Peters , James J. Roman , Som S. Swamy , Wen-chou Vincent Wang , Larry L. Moresco , Teruo Murase
发明人： Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Michael G. Peters , James J. Roman , Som S. Swamy , Wen-chou Vincent Wang , Larry L. Moresco , Teruo Murase
IPC分类号： H01L21/48 , H01L23/498 , H01L23/538 , H01L23/66 , H01L25/065 , H05K1/14 , H01L23/52 , H01L23/04 , H01L23/053 , H01L23/34
CPC分类号： H05K1/144 , H01L21/486 , H01L23/49827 , H01L23/49838 , H01L23/4985 , H01L23/5385 , H01L23/5387 , H01L23/66 , H01L25/0652 , H01L2224/16 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/19041 , H01L2924/3011
摘要： An interposer substrate for mounting an integrated circuit chip to a substrate, and method of making the same, are shown. The interposer substrate comprises power supply paths and controlled impedance signal paths that are substantially isolated from each other. Power supply is routed though rigid segments and signals are routed though a thin film flexible connector that runs from the upper surface of the interposer substrate to the lower surface. Bypass capacitance is incorporated into the interposer substrate and connected to the power supply so that it is positioned very close to the integrated circuit chip. The interposer may be fabricated by forming a multilayered thin film structure including the signal paths over a rigid substrate having vias formed therein, removing the central portion of the substrate leaving the two end segments, and folding and joining the end segments such that the vias are connected. In another embodiment of the invention, a separate power plate is provided for carrying the power lines. Portions of the power plate, with a multilayered thin film structure thereon, are cut and folded to form interposers. Methods of making single-chip interposers are also disclosed.
摘要翻译：示出了用于将集成电路芯片安装到基板的插入器基板及其制造方法。插入器基板包括彼此基本隔离的电源路径和受控阻抗信号路径。电源通过刚性段传送，信号通过薄膜柔性连接器布线，该连接器从插入器基板的上表面延伸到下表面。旁路电容被并入到插入器基板中并且连接到电源，使得其非常靠近集成电路芯片。可以通过在其上形成有通孔的刚性基板上形成包括信号路径的多层薄膜结构来制造插入件，去除离开两端段的基板的中心部分，以及折叠和连接端部段，使得通孔为连接的。在本发明的另一实施例中，提供了用于承载电源线的单独的功率板。在其上具有多层薄膜结构的功率板的部分被切割和折叠以形成插入件。还公开了制造单芯片插入件的方法。

6. 发明授权

US6102710A Controlled impedance interposer substrate and method of making 失效
标题翻译：受控阻抗插入器基板及其制造方法
公开(公告)号：US6102710A
公开(公告)日：2000-08-15
申请号：US70493
申请日：1998-04-30
申请人： Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Michael G. Peters , James J. Roman , Som S. Swamy , Wen-chou Vincent Wang , Larry L. Moresco , Teruo Murase
发明人： Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Michael G. Peters , James J. Roman , Som S. Swamy , Wen-chou Vincent Wang , Larry L. Moresco , Teruo Murase
IPC分类号： H01L21/48 , H01L23/498 , H01L23/538 , H01L23/66 , H01L25/065 , H05K1/14 , H01R12/00
CPC分类号： H05K1/144 , H01L21/486 , H01L23/49827 , H01L23/49838 , H01L23/4985 , H01L23/5385 , H01L23/5387 , H01L23/66 , H01L25/0652 , H01L2224/16 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/19041 , H01L2924/3011
摘要： An interposer substrate for mounting an integrated circuit chip to a substrate, and method of making the same, are shown. The interposer substrate comprises power supply paths and controlled impedance signal paths that are substantially isolated from each other. Power supply is routed through rigid segments and signals are routed through a thin film flexible connector that runs from the upper surface of the interposer substrate to the lower surface. Bypass capacitance is incorporated into the interposer substrate and connected to the power supply so that it is positioned very close to the integrated circuit chip. The interposer may be fabricated by forming a multilayered thin film structure including the signal paths over a rigid substrate having vias formed therein, removing the central portion of the substrate leaving the two end segments, and folding and joining the end segments such that the vias are connected. In another embodiment of the invention, a separate power plate is provided for carrying the power lines. Portions of the power plate, with a multilayered thin film structure thereon, are cut and folded to form interposers. Methods of making single-chip interposers are also disclosed.
摘要翻译：示出了用于将集成电路芯片安装到基板的插入器基板及其制造方法。插入器基板包括彼此基本隔离的电源路径和受控阻抗信号路径。电源通过刚性段布线，信号通过从内插器基板的上表面延伸到下表面的薄膜柔性连接器。旁路电容被并入到插入器基板中并且连接到电源，使得其非常靠近集成电路芯片。可以通过在其上形成有通孔的刚性基板上形成包括信号路径的多层薄膜结构来制造插入件，去除离开两端段的基板的中心部分，以及折叠和连接端部段，使得通孔为连接的。在本发明的另一实施例中，提供了用于承载电源线的单独的功率板。在其上具有多层薄膜结构的功率板的部分被切割和折叠以形成插入件。还公开了制造单芯片插入件的方法。

7. 发明授权

US5891354A Methods of etching through wafers and substrates with a composite etch stop layer 失效
标题翻译：用复合蚀刻停止层蚀刻晶片和衬底的方法
公开(公告)号：US5891354A
公开(公告)日：1999-04-06
申请号：US687723
申请日：1996-07-26
申请人： Michael G. Lee , Solomon I. Beilin , William T. Chou , Michael G. Peters , Wen-chou Vincent Wang
发明人： Michael G. Lee , Solomon I. Beilin , William T. Chou , Michael G. Peters , Wen-chou Vincent Wang
IPC分类号： H01L21/78 , H01L23/482 , H05K3/00 , B44C1/22 , H05K3/06
CPC分类号： H01L21/30604 , H01L21/78 , H01L23/4822 , H01L24/01 , H01L2924/01029 , H05K3/0017
摘要： Methods of wet etching through a silicon substrate using composite etch-stop layers are disclosed. In one embodiment, the composite etch stop comprises a layer of silicon dioxide and a layer of polyimide.
摘要翻译：公开了通过使用复合蚀刻停止层的硅衬底进行湿蚀刻的方法。在一个实施例中，复合蚀刻停止件包括二氧化硅层和聚酰亚胺层。

8. 发明授权

US5778529A Method of making a multichip module substrate 失效
标题翻译：制造多芯片模块基板的方法
公开(公告)号：US5778529A
公开(公告)日：1998-07-14
申请号：US651479
申请日：1996-05-22
申请人： Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Teruo Murase , Michael G. Peters , James J. Roman , Som S. Swamy , Wen-Chou Vincent Wang
发明人： Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Teruo Murase , Michael G. Peters , James J. Roman , Som S. Swamy , Wen-Chou Vincent Wang
IPC分类号： H01L21/48 , H01L23/473 , H01L23/498 , H01L23/538 , H01L23/66 , H01L25/065 , H05K1/14 , H01K3/10 , H05K3/10
CPC分类号： H01L21/486 , H01L21/4857 , H01L23/473 , H01L23/49827 , H01L23/49838 , H01L23/4985 , H01L23/5385 , H01L23/66 , H01L25/0652 , H05K1/144 , H01L2224/16 , H01L2924/00013 , H01L2924/01019 , H01L2924/01078 , H01L2924/09701 , H01L2924/3011 , Y10T29/49155 , Y10T29/49165 , Y10T29/49204
摘要： A multichip module substrate for use in a three-dimensional multichip module, and methods of making the same, are disclosed. The substrate comprises a thin film structure, for routing signals to and from integrated circuit chips, formed over a rigid support base. Apertures are formed in the support base exposing the underside of the thin film structure, thereby allowing high density connectors to be mounted on both surfaces of the thin film structure, greatly enhancing the ability to communicate signals between adjacent substrates in the chip module. This avoids the need to route the signals either through the rigid support base or to the edges of the thin film structure. Power and ground, which do not require a high connection density, are routed in low impedance paths through the support base. Preferably, the thin film structure is made of alternating layers of patterned metal, such as copper, and a low dielectric organic polymer, such as a polyimide.
摘要翻译：公开了一种用于三维多芯片模块的多芯片模块基板及其制造方法。衬底包括薄膜结构，用于将信号路由到集成电路芯片上并从集成电路芯片路由到刚性支撑基底上。在支撑基体中形成孔，露出薄膜结构的下侧，从而允许将高密度连接器安装在薄膜结构的两个表面上，大大增强了在芯片模块中的相邻基板之间传递信号的能力。这避免了将信号路由通过刚性支撑底座或薄膜结构的边缘的需要。不需要高连接密度的电源和接地路径通过支持底座的低阻抗路径。优选地，薄膜结构由诸如铜的图案化金属的交替层和诸如聚酰亚胺的低介电有机聚合物制成。

9. 发明授权

US5872696A Sputtered and anodized capacitors capable of withstanding exposure to high temperatures 失效
标题翻译：溅射和阳极氧化电容器能承受高温暴露
公开(公告)号：US5872696A
公开(公告)日：1999-02-16
申请号：US826980
申请日：1997-04-09
申请人： Michael G. Peters , Michael G. Lee , Solomon I. Beilin , Yasuhito Takahashi
发明人： Michael G. Peters , Michael G. Lee , Solomon I. Beilin , Yasuhito Takahashi
IPC分类号： H01G4/08 , H01L21/02 , H01G4/008 , B05D5/12 , H01G4/06
CPC分类号： H01L28/60 , H01G4/085
摘要： Novel structures for capacitors which are capable of withstanding heat treatments to at least 400.degree. C. while providing low defect densities and low electrical series resistance in its electrodes are disclosed. In one embodiment of the present invention, a capacitor structure includes a bottom capacitor electrode formed of a first sub-layer of aluminum, a second sub-layer of tantalum nitride, and a third sub-layer of tantalum. The capacitor structure further includes a sputtered dielectric layer of tantalum pentoxide over the tantalum sub-layer of the bottom electrode. The resulting structure is anodized such that the underlying tantalum layer is fully anodized, and preferably such that a portion of the tantalum nitride layer is converted to a tantalum oxy-nitride. The tantalum nitride layer was discovered by the inventors to act as a good high temperature diffusion barrier for the aluminum, preventing the aluminum from migrating into the anodized tantalum pentoxide layer under high temperature processing conditions, where it would chemically reduce the tantalum atoms in the tantalum pentoxide layer and introduce conductive paths of tantalum in the dielectric (tantalum pentoxide) layer. The aluminum layer provides good electrical conductivity for the bottom electrode, and is anodized to fill any pinhole defects in the layers formed above it, thereby increasing manufacturing yields.
摘要翻译：公开了一种电容器的新型结构，其能够耐热处理至少400℃，同时在其电极中提供低缺陷密度和低电串联电阻。在本发明的一个实施例中，电容器结构包括由铝的第一子层，氮化钽的第二子层和钽的第三子层形成的底部电容器电极。电容器结构还包括在底部电极的钽子层上的五氧化二钽的溅射介电层。所得到的结构被阳极氧化，使得下面的钽层被完全阳极氧化，并且优选地使得一部分氮化钽层转化为氮氧化钽。本发明人发现氮化钽层用作铝的良好的高温扩散阻挡层，防止铝在高温加工条件下迁移到阳极氧化的五氧化二钽层中，其中它将化学还原钽中的钽原子并在介电（五氧化二钽）层中引入钽的导电路径。铝层为底部电极提供良好的导电性，并被阳极氧化以填充其上形成的层中的任何针孔缺陷，从而提高制造产量。

10. 发明授权

US06226171B1 Power conducting substrates with high-yield integrated substrate capacitor 有权
标题翻译：具有高成本集成基板电容器的导电基板
公开(公告)号：US06226171B1
公开(公告)日：2001-05-01
申请号：US09227239
申请日：1999-01-08
申请人： Solomon I. Beilin , William T. Chou , Michael G. Lee , David Dung Ngo , Michael G. Peters , James J. Roman , Yasuhito Takahashi
发明人： Solomon I. Beilin , William T. Chou , Michael G. Lee , David Dung Ngo , Michael G. Peters , James J. Roman , Yasuhito Takahashi
IPC分类号： H01G4228
CPC分类号： H01L23/50 , H01L23/5383 , H01L2924/0002 , H01L2924/3011 , H05K1/056 , H05K1/162 , H05K3/045 , H05K3/388 , H05K3/44 , H05K2201/0154 , H05K2201/0195 , H05K2201/09481 , H05K2201/09509 , H05K2201/09554 , H05K2203/0315 , H01L2924/00
摘要： Several inventive features for increasing the yield of substrate capacitors are disclosed. The inventive features relating to selective placement of insulating layers and patches around selected areas of the capacitor's main dielectric layer. These insulating layers and defects prevent certain manufacturing processing steps from creating pin-hole defects in the main dielectric layer. The inventive features are suitable for any type of material for the main dielectric layer, and are particularly suited to anodized dielectric layers.
摘要翻译：公开了用于增加基板电容器的产量的几个发明特征。本发明的特征涉及在电容器的主介电层的选定区域周围选择性地放置绝缘层和贴片。这些绝缘层和缺陷防止某些制造处理步骤在主介电层中产生针孔缺陷。本发明的特征适合于用于主介电层的任何类型的材料，并且特别适用于阳极化电介质层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式