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1. 发明授权

US06239485B1 Reduced cross-talk noise high density signal interposer with power and ground wrap 失效
标题翻译：减少串扰噪声高密度信号插入器与电源和地面包装
公开(公告)号：US06239485B1
公开(公告)日：2001-05-29
申请号：US09315785
申请日：1999-05-20
申请人： Michael G. Peters , Wen-chou Vincent Wang , Yasuhito Takahashi , William Chou , Michael G. Lee , Solomon Beilin
发明人： Michael G. Peters , Wen-chou Vincent Wang , Yasuhito Takahashi , William Chou , Michael G. Lee , Solomon Beilin
IPC分类号： H01L2312
CPC分类号： H05K1/0219 , H01L23/49822 , H01L23/49833 , H01L23/49838 , H01L23/50 , H01L23/5383 , H01L23/5385 , H01L23/5386 , H01L23/552 , H01L2224/16225 , H01L2224/16235 , H01L2924/01004 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/01327 , H01L2924/09701 , H01L2924/10253 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H05K1/141 , H05K1/144 , H05K3/20 , H05K2201/049 , H05K2201/055 , H05K2201/10378 , H01L2924/00
摘要： An interposer for providing power, ground, and signal connections between an integrated circuit chip or chips and a substrate. The inventive interposer includes a signal core and external power/ground connection wrap. The two sections may be fabricated and tested separately, then joined together using z-connection technology. The signal core is formed from a conductive power/ground plane positioned between two dielectric layers. A patterned metal layer is formed on each dielectric layer. The two metal layers are interconnected by a through via or post process. The conductive power/ground plane functions to reduce signal cross-talk between signal lines formed on the two patterned metal layers. The power/ground wrap includes an upper substrate positioned above the signal core and a lower substrate positioned below the signal core. The upper and lower substrates of the power/ground wrap are formed from a dielectric film having a patterned metal layer on both sides, with the patterned layers connected by a through via or post process. The two power/ground wrap substrates may be formed separately or from one substrate which is bent into a desired form (e.g., a “U” shape). The two power/ground substrates are maintained in their proper alignment relative to the signal core and to each other by edge connectors which are also connected to the signal core's intermediary power/ground plane.
摘要翻译：一种用于在集成电路芯片或芯片与基板之间提供电源，接地和信号连接的插入器。本发明的插入器包括信号芯和外部电源/接地连接外壳。这两个部分可以单独制造和测试，然后使用z连接技术连接在一起。信号芯由位于两个电介质层之间的导电电源/接地平面形成。在每个电介质层上形成图案化的金属层。两个金属层通过通孔或后处理相互连接。导电功率/接地面用于减少形成在两个图案化金属层上的信号线之间的信号串扰。电源/接地包裹物包括位于信号芯上方的上基板和位于信号芯下方的下基板。电源/接地线圈的上下基板由两面具有图案化金属层的电介质膜形成，图案化层通过通孔或后工艺连接。两个电源/接地包覆基板可以分开地形成，或者可以从弯曲成所需形状（例如，“U”形状）的一个基板形成。两个电源/接地基板相对于信号芯线保持正确的对准，并通过也连接到信号芯的中间电源/接地平面的边缘连接器彼此保持。

2. 发明授权

US06662443B2 Method of fabricating a substrate with a via connection 失效
标题翻译：用通孔连接制造衬底的方法
公开(公告)号：US06662443B2
公开(公告)日：2003-12-16
申请号：US09935378
申请日：2001-08-22
申请人： William T. Chou , Solomon Beilin , Michael G. Lee , Michael G. Peters , Wen-chou Vincent Wang
发明人： William T. Chou , Solomon Beilin , Michael G. Lee , Michael G. Peters , Wen-chou Vincent Wang
IPC分类号： H01K310
CPC分类号： H05K3/423 , H05K3/0035 , H05K2201/0355 , H05K2201/0394 , H05K2203/0733 , Y10T29/49126 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： A method of fabricating a multilayer interconnected substrate is disclosed. In one embodiment, the method includes providing a structure having a dielectric substrate having a first substantially planar surface and an opposing second substantially planar surface. A first conductive layer is disposed on the first substantially planar surface of the dielectric substrate, and an interface is present between the first conductive layer and the dielectric substrate. A blind via site is formed in the structure, and through the dielectric substrate to the interface between the first conductive layer and the dielectric substrate. The blind via site is filled with a conductive material by an electrolytic plating process.
摘要翻译：公开了一种制造多层互连衬底的方法。在一个实施例中，该方法包括提供具有电介质基底的结构，其具有第一基本上平坦的表面和相对的第二基本上平坦的表面。第一导电层设置在电介质基板的第一基本上平坦的表面上，并且在第一导电层和电介质基板之间存在界面。在该结构中形成盲通孔部位，并且通过电介质基板到第一导电层和电介质基板之间的界面。盲孔通过电镀工艺填充导电材料。

3. 发明授权

US06444921B1 Reduced stress and zero stress interposers for integrated-circuit chips, multichip substrates, and the like 失效
标题翻译：用于集成电路芯片，多芯片基板等的减少应力和零应力插入件
公开(公告)号：US06444921B1
公开(公告)日：2002-09-03
申请号：US09497542
申请日：2000-02-03
申请人： Wen-chou Vincent Wang , Michael G. Lee , Solomon Beilin
发明人： Wen-chou Vincent Wang , Michael G. Lee , Solomon Beilin
IPC分类号： H05K116
CPC分类号： H01L23/49827 , H01L23/49833 , H01L23/4985 , H01L2224/05568 , H01L2224/05573 , H01L2224/056 , H01L2224/16 , H01L2224/16225 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/10253 , H01L2924/15311 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/0061 , H05K3/363 , H05K2201/049 , H05K2201/10734 , H01L2924/00 , H01L2924/00014
摘要： Disclosed is an interposer for electrically coupling two electrical components having different coefficients of thermal expansion (CTEs). The interposer has two substrates which have different CTE values, with each substrate having a first surface and a second surface. The interposer has electrical connectors located on the first surfaces of the two substrates, the connectors for making electrical connections to the two corresponding electrical components. A flexible-circuit layer is disposed between the two substrates and interconnects the connectors on the first substrate to the connectors on the second substrate. The two substrates are folded such that their second surfaces confront one another, where they may be attached to one another. General methods of making interposers for electrically coupling two electrical components are disclosed. A first substrate and a sacrificial substrate are encapsulated in an encapsulant material to form a composite substrate, with a second substrate being formed from the cured encapsulate material. Alternatively, the second substrate may be provided by a separate substrate that is encapsulated along with the first substrate and the sacrificial substrate. The surfaces of the composite substrate are polished, and a dielectric layer is formed over a polished surface of the composite substrate. A plurality of electrical traces are formed over the dielectric film. A portion of the composite substrate at its back surface is removed to expose a surface of the sacrificial substrate, and the sacrificial substrate is removed.
摘要翻译：公开了一种用于电耦合具有不同热膨胀系数（CTE）的两个电气部件的插入器。插入器具有两个具有不同CTE值的基板，每个基板具有第一表面和第二表面。插入器具有位于两个基板的第一表面上的电连接器，用于与两个相应的电气部件电连接的连接器。柔性电路层设置在两个基板之间并将第一基板上的连接器互连到第二基板上的连接器。两个基板被折叠成使得它们的第二表面彼此面对，在那里它们可以彼此附接。公开了用于电连接两个电气部件的内插件的一般方法。将第一衬底和牺牲衬底封装在密封材料中以形成复合衬底，其中第二衬底由固化的封装材料形成。或者，第二衬底可以由与第一衬底和牺牲衬底一起封装的单独衬底提供。抛光复合基板的表面，并在复合基板的抛光表面上形成电介质层。在电介质膜上形成多个电迹线。去除其后表面处的复合衬底的一部分以暴露牺牲衬底的表面，并且去除牺牲衬底。

4. 发明授权

US06391220B1 Methods for fabricating flexible circuit structures 失效
标题翻译：制造柔性电路结构的方法
公开(公告)号：US06391220B1
公开(公告)日：2002-05-21
申请号：US09376645
申请日：1999-08-18
申请人： Lei Zhang , Solomon Beilin , Som S. Swamy , James J. Roman
发明人： Lei Zhang , Solomon Beilin , Som S. Swamy , James J. Roman
IPC分类号： B32B3100
CPC分类号： B32B37/26 , B32B2457/08 , H01L21/6835 , H01L2221/68318 , H01L2221/68345 , H01L2221/68381 , H05K3/025 , H05K3/205 , Y10S438/957 , Y10S438/968 , Y10S438/976 , Y10T29/49155 , Y10T29/4916 , Y10T156/1082 , Y10T156/1158
摘要： Methods and articles used to fabricate flexible circuit structures are disclosed. The methods include depositing a release layer on substrate, and then forming a conductive laminate on the release layer. After the release layer is formed, the conductive laminate can be easily separated by the substrate to eventually form a flexible circuit structure.
摘要翻译：公开了用于制造柔性电路结构的方法和制品。所述方法包括在基材上沉积剥离层，然后在剥离层上形成导电层压材料。在形成释放层之后，导电层压体可以容易地被衬底分离，最终形成柔性电路结构。

5. 发明授权

US6081026A High density signal interposer with power and ground wrap 有权
标题翻译：高密度信号插入器，具有电源和地面包装
公开(公告)号：US6081026A
公开(公告)日：2000-06-27
申请号：US191755
申请日：1998-11-13
申请人： Wen-chou Vincent Wang , Yasuhito Takahashi , William T. Chou , Michael G. Peters , Michael G. Lee , Solomon Beilin
发明人： Wen-chou Vincent Wang , Yasuhito Takahashi , William T. Chou , Michael G. Peters , Michael G. Lee , Solomon Beilin
IPC分类号： H01L23/498 , H01L23/50 , H01L23/538 , H01L23/552 , H05K1/02 , H05K1/14 , H05K3/20 , H01L23/12 , H01L23/053
CPC分类号： H01L23/5383 , H01L23/49822 , H01L23/49833 , H01L23/49838 , H01L23/50 , H01L23/5385 , H01L23/5386 , H01L23/552 , H05K1/0219 , H01L2224/16225 , H01L2924/00014 , H01L2924/01078 , H01L2924/15311 , H01L2924/3011 , H05K1/141 , H05K1/144 , H05K2201/049 , H05K2201/055 , H05K2201/10378 , H05K3/20
摘要： An interposer for providing power, ground, and signal connections between an integrated circuit chip or chips and a substrate. The interposer includes a signal core and external power/ground connection wrap. The two sections may be fabricated and tested separately, then joined together using z-connection technology. The signal core is a dielectric film with patterned metal on both sides. The two metal layers are interconnected by a through via or post process. The power/ground wrap includes an upper substrate positioned above the signal core and a lower substrate positioned below the signal core. The upper and lower substrates of the power/ground wrap are formed from a dielectric film having a patterned metal layer on both sides connected by a through via or post process. The upper power/ground wrap substrate, signal core, and lower power/ground substrate are interconnected as desired using z-connection technology (e.g., solder or conductive ink). The power/ground layers on the upper substrate can be connected to the power/ground layers on the lower substrate by suitable edge connectors. With an integrated circuit chip or chips connected to the upper layer of the top substrate of the power/ground wrap and a printed circuit board or other mounting substrate connected to the bottom layer of the lower substrate of the wrap, the inventive interposer provides a set of high density and electrically isolated signal, power, and ground interconnections.
摘要翻译：一种用于在集成电路芯片或芯片与基板之间提供电源，接地和信号连接的插入器。插入器包括信号芯和外部电源/接地连接外壳。这两个部分可以单独制造和测试，然后使用z连接技术连接在一起。信号芯是两侧具有图案化金属的电介质膜。两个金属层通过通孔或后处理相互连接。电源/接地包裹物包括位于信号芯上方的上基板和位于信号芯下方的下基板。电源/接地套管的上基板和下基板由具有通过通孔或后工艺连接的两侧上的图案化金属层的电介质膜形成。上电源/地基封装衬底，信号芯和下电源/接地衬底根据需要使用z连接技术（例如焊料或导电油墨）互连。上基板上的电源/接地层可以通过合适的边缘连接器连接到下基板上的电源/接地层。通过将集成电路芯片或芯片连接到电源/接地外壳的顶部基板的上层，以及连接到包装的下基板的底层的印刷电路板或其它安装基板，本发明的插入件提供一组高密度和电隔离的信号，电源和接地互连。

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