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1. 发明申请

US20070016733A1 Method to Provide Atomic Update Primitives in an Asymmetric Heterogeneous Multiprocessor Environment 有权
标题翻译：在非对称异构多处理器环境中提供原子更新原语的方法
公开(公告)号：US20070016733A1
公开(公告)日：2007-01-18
申请号：US11468317
申请日：2006-08-30
申请人： Michael Day , Charles Johns , James Kahle , Peichum Liu , Thuong Truong
发明人： Michael Day , Charles Johns , James Kahle , Peichum Liu , Thuong Truong
IPC分类号： G06F12/14 , G06F13/28
CPC分类号： G06F13/28 , G06F9/3004 , G06F9/30087 , G06F12/0831 , G06F2213/0038
摘要： The present invention provides for atomic update primitives in an asymmetric single-chip heterogeneous multiprocessor computer system having a shared memory with DMA transfers. At least one lock line command is generated from a set comprising a get lock line command with reservation, a put lock line conditional command, and a put lock line unconditional command.
摘要翻译：本发明提供了具有具有DMA传输的共享存储器的非对称单芯片异构多处理器计算机系统中的原子更新原语。从包括具有预留的get lock line命令，put lock line条件命令和put lock line无条件命令的集合中生成至少一个lock line命令。

2. 发明申请

US20070174509A1 SYSTEM FOR ASYNCHRONOUS DMA COMMAND COMPLETION NOTIFICATION 失效
标题翻译：异步DMA命令完成通知系统
公开(公告)号：US20070174509A1
公开(公告)日：2007-07-26
申请号：US11695436
申请日：2007-04-02
申请人： Michael Day , Harm Hofstee , Charles Johns , Peichum Liu , Thuong Truong , Takeshi Yamazaki
发明人： Michael Day , Harm Hofstee , Charles Johns , Peichum Liu , Thuong Truong , Takeshi Yamazaki
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： The present invention provides for a system comprising a DMA queue configured to receive a DMA command comprising a tag, wherein the tag belongs to one of a plurality of tag groups. A counter couples to the DMA queue and is configured to increment a tag group count of the tag group to which the tag belongs upon receipt of the DMA command by the DMA queue and to decrement the tag group count upon execution of the DMA command. A tag group count status register couples to the counter and is configured to store the tag group count for each of the plurality of tag groups. And the tag group count status register is further configured to receive a request for a tag group status and to respond to the request for the tag group status.
摘要翻译：本发明提供一种包括配置成接收包括标签的DMA命令的DMA队列的系统，其中标签属于多个标签组之一。计数器耦合到DMA队列，并配置为在DMA队列接收到DMA命令时增加标签组所属标签组的标签组计数，并在执行DMA命令时递减标签组计数。标签组计数状态寄存器耦合到计数器，并被配置为存储多个标签组中的每一个的标签组计数。并且标签组计数状态寄存器被进一步配置为接收对标签组状态的请求并响应对标签组状态的请求。

3. 发明申请

US20050055505A1 Software-controlled cache set management with software-generated class identifiers 失效
标题翻译：软件控制的缓存集管理与软件生成的类标识符
公开(公告)号：US20050055505A1
公开(公告)日：2005-03-10
申请号：US10655365
申请日：2003-09-04
申请人： Michael Day , Harm Hofstee , Charles Johns , James Kahle , David Shippy , Thuong Truong , Takeshi Yamazaki
发明人： Michael Day , Harm Hofstee , Charles Johns , James Kahle , David Shippy , Thuong Truong , Takeshi Yamazaki
IPC分类号： G06F12/00 , G06F12/12
CPC分类号： G06F12/126
摘要： The present invention provides for selectively overwriting sets of a cache as a function of a replacement management table and a least recently used function. A class identifier is created as a function of an address miss. A replacement management table is employable to read the class identifier to create a tag replacement control indicia. The cache, comprising a plurality of sets, is employable to disable the replacement of at least one of the plurality of sets as a function of the tag replacement control indicia.
摘要翻译：本发明提供了根据替换管理表和最近最少使用的功能来选择性地覆盖高速缓存的集合。根据地址未命中创建类标识符。替换管理表可用于读取类标识符以创建标签替换控制标记。包括多个集合的高速缓存可用于根据标签替换控制标记来禁用对多个集合中的至少一个的替换。

4. 发明申请

US20050080998A1 Method and apparatus for coherent memory structure of heterogeneous processor systems 失效
标题翻译：异构处理器系统的相干存储器结构的方法和装置
公开(公告)号：US20050080998A1
公开(公告)日：2005-04-14
申请号：US10682386
申请日：2003-10-09
申请人： Michael Day , Harm Hofstee , Charles Johns , James Kahle , David Shippy , Thuong Truong
发明人： Michael Day , Harm Hofstee , Charles Johns , James Kahle , David Shippy , Thuong Truong
IPC分类号： G06F12/08
CPC分类号： G06F12/0835
摘要： Disclosed is a coherent cache system that operates in conjunction with non-homogeneous processing units. A set of processing units of a first configuration has conventional cache and directly accesses common or shared system physical and virtual address memory through the use of a conventional MMU (Memory Management Unit). Additional processors of a different configuration and/or other devices that need to access system memory are configured to store accessed data in compatible caches. Each of the caches is compatible with a given protocol coherent memory management bus interspersed between the caches and the system memory.
摘要翻译：公开了与非均匀处理单元结合操作的一致的缓存系统。一组第一配置的处理单元具有常规高速缓存，并且通过使用常规MMU（存储器管理单元）直接访问公用或共享系统物理和虚拟地址存储器。需要访问系统存储器的不同配置和/或其他设备的其他处理器被配置为将访问的数据存储在兼容的高速缓存中。每个缓存与散列在高速缓存和系统存储器之间的给定协议相干存储器管理总线兼容。

5. 发明申请

US20050055507A1 Software-controlled cache set management 失效
标题翻译：软件控制缓存集管理
公开(公告)号：US20050055507A1
公开(公告)日：2005-03-10
申请号：US10655367
申请日：2003-09-04
申请人： Michael Day , Harm Hofstee , Charles Johns , James Kahle , David Shippy , Thuong Truong , Takeshi Yamazaki
发明人： Michael Day , Harm Hofstee , Charles Johns , James Kahle , David Shippy , Thuong Truong , Takeshi Yamazaki
IPC分类号： G06F12/00 , G06F12/12
CPC分类号： G06F12/126
摘要： The present invention provides for selectively overwriting sets of a cache as a function of a replacement management table and a least recently used function. A class identifier is created as a function of an address miss. A replacement management table is employable to read the class identifier to create a tag replacement control indicia. The cache, comprising a plurality of sets, is employable to disable the replacement of at least one of the plurality of sets as a function of the tag replacement control indicia.
摘要翻译：本发明提供了根据替换管理表和最近最少使用的功能来选择性地覆盖高速缓存的集合。根据地址未命中创建类标识符。替换管理表可用于读取类标识符以创建标签替换控制标记。包括多个集合的高速缓存可用于根据标签替换控制标记来禁用对多个集合中的至少一个的替换。

6. 发明申请

US20050028015A1 Method and apparatus for managing the power consumption of a data processing system 失效
标题翻译：用于管理数据处理系统的功耗的方法和装置
公开(公告)号：US20050028015A1
公开(公告)日：2005-02-03
申请号：US10631537
申请日：2003-07-31
申请人： Shigehiro Asano , Jeffrey Brown , Michael Day , Charles Johns , James Kahle , Alvan Ng , Michael Wang , Thuong Truong
发明人： Shigehiro Asano , Jeffrey Brown , Michael Day , Charles Johns , James Kahle , Alvan Ng , Michael Wang , Thuong Truong
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F12/0831 , G06F12/1027 , G06F2212/1028 , Y02D10/13
摘要： A component of a microprocessor-based data processing system, which includes features for regulating power consumption in snoopable components and has gating off memory coherency properties, is determined to be in a relatively inactive state and is transitioned to a non-snoopable low power mode. Then, when a snoop request occurs, a retry protocol is sent in response to the snoop request. In conjunction with the retry protocol, a signal is sent to bring the component into snoopable mode. When the retry snoop is requested, the component is in full power mode and can properly respond to the snoop request. After the snoop request has been satisfied, the component again enters into a low power mode. Therefore, the component is able to enter into a low power mode in between snoops
摘要翻译：基于微处理器的数据处理系统的一个组件，其包括用于调节可窥探组件中的功耗并具有门控存储器一致性属性的特征，被确定为处于相对不活动状态，并且转换到不可窥探的低功率模式。然后，当侦听请求发生时，响应于窥探请求发送重试协议。结合重试协议，发送信号使组件进入窥探模式。当请求重试监听时，组件处于全功率模式，并可以正常响应窥探请求。在snoop请求已满足后，组件再次进入低功耗模式。因此，该组件能够在两个snoops之间进入低功耗模式

7. 发明申请

US20060095668A1 Method for processor to use locking cache as part of system memory 失效
标题翻译：处理器使用锁定缓存作为系统内存的一部分的方法
公开(公告)号：US20060095668A1
公开(公告)日：2006-05-04
申请号：US10976260
申请日：2004-10-28
申请人： Michael Day , Charles Johns , Thuong Truong
发明人： Michael Day , Charles Johns , Thuong Truong
IPC分类号： G06F12/14
CPC分类号： G06F12/126 , G06F12/0848 , G06F2212/2515
摘要： The present invention provides a method for a processor to write data to a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it is loaded for use. Data remains in the locking cache until it is specifically overwritten under software control. The locking cache or other fast memory can be used as additional system memory. In an embodiment of the invention, the locking cache is one or more sets of ways, but not all of the sets or ways, of a multiple set associative cache.
摘要翻译：本发明提供了一种用于处理器将数据写入高速缓存或其他快速存储器的方法，而不将其写入主存储器。此外，数据被“锁定”到高速缓存或其他快速存储器中，直到它被加载使用为止。数据保留在锁定缓存中，直到它在软件控制下被特别覆盖为止。锁定缓存或其他快速存储器可用作附加系统内存。在本发明的实施例中，锁定高速缓存是多组关联高速缓存的一组或多组方式，但不是所有的集合或方式。

8. 发明申请

US20050111478A1 Distributed control load shaping method and apparatus 审中-公开
标题翻译：分布式控制负载整形方法及装置
公开(公告)号：US20050111478A1
公开(公告)日：2005-05-26
申请号：US10718936
申请日：2003-11-20
申请人： Jeffrey Brown , Michael Day , Charles Johns , Thuong Truong , Takeshi Yamazaki
发明人： Jeffrey Brown , Michael Day , Charles Johns , Thuong Truong , Takeshi Yamazaki
IPC分类号： H04L12/56 , H04L12/42
CPC分类号： H04L47/822 , H04L47/13 , H04L47/20 , H04L47/22 , H04L47/2441 , H04L47/39 , H04L47/70 , H04L47/72 , H04L47/781 , H04L47/803 , H04L47/821
摘要： Disclosed is an apparatus for controlling or managing the transmission of data packets over a multiplexed communication path, referred to herein as a bus, on a priority basis up to a given authorized BW (Bandwidth), in a given operational time period, for presently authorized devices or applications. Non-managed (not presently authorized) bus requests are handled in a prior art “best effort” basis.
摘要翻译：公开了一种用于在给定的操作时间段内，在给定的操作时间段内优先地基于多路通信路径（这里称为总线）来控制或管理数据分组的传输的装置，用于当前授权的设备或应用程序。非管理（未授权）总线请求以现有技术“尽力而为”为基础来处理。

9. 发明申请

US20060015652A1 Establishing command order in an out of order DMA command queue 失效
标题翻译：在命令行DMA命令队列中建立命令顺序
公开(公告)号：US20060015652A1
公开(公告)日：2006-01-19
申请号：US10891772
申请日：2004-07-15
申请人： Michael Day , Charles Johns , Peichun Liu , Thuong Truong , Takeshi Yamazaki
发明人： Michael Day , Charles Johns , Peichun Liu , Thuong Truong , Takeshi Yamazaki
IPC分类号： G06F13/14
CPC分类号： G06F13/28
摘要： A method, an apparatus, and a computer program are provided for controlling memory access. Direct Memory Access (DMA) units have become commonplace in a number of bus architectures. However, managing limited system resources has become a challenge with multiple DMA units. In order to mange the multitude of commands generated and preserve dependencies, embedded flags in commands or a barrier command are used. These operations then can control the order in which commands are executed so as to preserve dependencies.
摘要翻译：提供了一种用于控制存储器访问的方法，装置和计算机程序。直接存储器访问（DMA）单元已经在许多总线架构中变得普遍。然而，管理有限的系统资源已成为多个DMA单元的挑战。为了管理生成的多个命令并保留依赖关系，使用命令中的嵌入式标志或障碍命令。这些操作然后可以控制执行命令的顺序，以便保留依赖性。

10. 发明申请

US20070079018A1 System and method for communicating command parameters between a processor and a memory flow controller 失效
标题翻译：用于在处理器和存储器流控制器之间传送命令参数的系统和方法
公开(公告)号：US20070079018A1
公开(公告)日：2007-04-05
申请号：US11207986
申请日：2005-08-19
申请人： Michael Day , Charles Johns , Peichun Liu , Todd Swanson , Thuong Truong
发明人： Michael Day , Charles Johns , Peichun Liu , Todd Swanson , Thuong Truong
IPC分类号： G06F13/00
CPC分类号： G06F13/32 , G06F13/1642
摘要： A system and method for communicating command parameters between a processor and a memory flow controller are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译：提供了一种用于在处理器和存储器流控制器之间传送命令参数的系统和方法。系统和方法利用通道接口作为处理器和存储器流控制器之间通信的主要机制。通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。这些通道可以被指定为阻塞或非阻塞。使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。因此，本发明的通道允许处理器保持在低功率状态。

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