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1. 发明申请

US20130009666A1 FIELD PROGRAMMABLE GATE ARRAY WITH INTEGRATED APPLICATION SPECIFIC INTEGRATED CIRCUIT FABRIC 审中-公开
标题翻译：具有集成应用的现场可编程阵列特殊集成电路布
公开(公告)号：US20130009666A1
公开(公告)日：2013-01-10
申请号：US13613925
申请日：2012-09-13
申请人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
发明人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/17732 , H03K19/17796
摘要： A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.
摘要翻译：提供具有集成专用集成电路（ASIC）结构的现场可编程门阵列（FPGA）。 ASIC结构可以用于在FPGA内实现一个或多个定制或半定制硬块。 ASIC结构可以由自定义区域和接口区域组成。定制区域可以实现定制或半定制ASIC设计，接口区域可以将自定义区域集成到FPGA电路的其余部分。定制区域可以基于结构化ASIC设计。接口区域可以允许将ASIC结构并入FPGA的分级组织中，从而允许定制区域以无缝的方式连接到FPGA电路。

2. 发明授权

US08314636B2 Field programmable gate array with integrated application specific integrated circuit fabric 有权
标题翻译：具有集成专用集成电路结构的现场可编程门阵列
公开(公告)号：US08314636B2
公开(公告)日：2012-11-20
申请号：US12767696
申请日：2010-04-26
申请人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
发明人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/17732 , H03K19/17796
摘要： A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.
摘要翻译：提供具有集成专用集成电路（ASIC）结构的现场可编程门阵列（FPGA）。 ASIC结构可以用于在FPGA内实现一个或多个定制或半定制硬块。 ASIC结构可以由自定义区域和接口区域组成。定制区域可以实现定制或半定制ASIC设计，接口区域可以将自定义区域集成到FPGA电路的其余部分。定制区域可以基于结构化ASIC设计。接口区域可以允许将ASIC结构并入FPGA的分级组织中，从而允许定制区域以无缝的方式连接到FPGA电路。

3. 发明申请

US20090051387A1 Field programmable gate array with integrated application specific integrated circuit fabric 有权
标题翻译：具有集成专用集成电路结构的现场可编程门阵列
公开(公告)号：US20090051387A1
公开(公告)日：2009-02-26
申请号：US11894283
申请日：2007-08-20
申请人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
发明人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/17732 , H03K19/17796
摘要： A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.
摘要翻译：提供了具有集成专用集成电路（“ASIC”）结构的现场可编程门阵列（“FPGA”）。 ASIC结构可以用于在FPGA内实现一个或多个定制或半定制硬块。 ASIC结构可以由“自定义区域”和“接口区域”组成。定制区域可以实现定制或半定制ASIC设计，接口区域可以将自定义区域集成到FPGA电路的其余部分。定制区域可以基于结构化ASIC设计。接口区域可以允许将ASIC结构并入FPGA的分级组织中，从而允许定制区域以无缝的方式连接到FPGA电路。

4. 发明授权

US07724032B2 Field programmable gate array with integrated application specific integrated circuit fabric 有权
标题翻译：具有集成专用集成电路结构的现场可编程门阵列
公开(公告)号：US07724032B2
公开(公告)日：2010-05-25
申请号：US11894283
申请日：2007-08-20
申请人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
发明人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/17732 , H03K19/17796
摘要： A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.
摘要翻译：提供了具有集成专用集成电路（“ASIC”）结构的现场可编程门阵列（“FPGA”）。 ASIC结构可以用于在FPGA内实现一个或多个定制或半定制硬块。 ASIC结构可以由“自定义区域”和“接口区域”组成。自定义区域可以实现定制或半定制ASIC设计，接口区域可以将自定义区域集成并连接到FPGA的其余部分电路。定制区域可以基于结构化ASIC设计。接口区域可以允许将ASIC结构并入FPGA的分层组织中，从而允许定制区域以无缝的方式连接到FPGA电路。

5. 发明授权

US09705506B2 Field programmable gate array with integrated application specific integrated circuit fabric 有权
公开(公告)号：US09705506B2
公开(公告)日：2017-07-11
申请号：US13613925
申请日：2012-09-13
申请人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
发明人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/17732 , H03K19/17796
摘要： A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.

6. 发明申请

US20100207659A1 FIELD PROGRAMMABLE GATE ARRAY WITH INTEGRATED APPLICATION SPECIFIC INTEGRATED CIRCUIT FABRIC 有权
标题翻译：具有集成应用的现场可编程阵列阵列集成电路布
公开(公告)号：US20100207659A1
公开(公告)日：2010-08-19
申请号：US12767696
申请日：2010-04-26
申请人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
发明人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
IPC分类号： H03K19/177 , G06F17/50
CPC分类号： H03K19/17744 , H03K19/17732 , H03K19/17796
摘要： A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.
摘要翻译：提供了具有集成专用集成电路（“ASIC”）结构的现场可编程门阵列（“FPGA”）。 ASIC结构可以用于在FPGA内实现一个或多个定制或半定制硬块。 ASIC结构可以由“自定义区域”和“接口区域”组成。自定义区域可以实现定制或半定制ASIC设计，接口区域可以将自定义区域集成并连接到FPGA的其余部分电路。定制区域可以基于结构化ASIC设计。接口区域可以允许将ASIC结构并入FPGA的分级组织中，从而允许定制区域以无缝的方式连接到FPGA电路。

7. 发明授权

US07420390B1 Method and apparatus for implementing additional registers in field programmable gate arrays to reduce design size 有权
标题翻译：用于在现场可编程门阵列中实现附加寄存器以减少设计尺寸的方法和装置
公开(公告)号：US07420390B1
公开(公告)日：2008-09-02
申请号：US11328407
申请日：2006-01-09
申请人： Michael D. Hutton , James G. Schleicher, II
发明人： Michael D. Hutton , James G. Schleicher, II
IPC分类号： H03K19/177
CPC分类号： H03K19/17748 , H03K19/17728 , H03K19/17736 , H03K19/1776
摘要： A field programmable gate array includes a plurality of programmable logic blocks to implement one or more logic functions. The field programmable gate array includes a plurality of independent registers not associated with any specific one of the plurality of programmable logic blocks. The plurality of independent registers may be programmed to support any one of the plurality of programmable logic blocks.
摘要翻译：现场可编程门阵列包括多个可编程逻辑块以实现一个或多个逻辑功能。现场可编程门阵列包括不与多个可编程逻辑块中的任何特定的一个相关联的多个独立寄存器。多个独立寄存器可被编程为支持多个可编程逻辑块中的任何一个。

8. 发明授权

US07368942B1 Dedicated resource interconnects 有权
标题翻译：专用资源互连
公开(公告)号：US07368942B1
公开(公告)日：2008-05-06
申请号：US11351882
申请日：2006-02-09
申请人： Michael D. Hutton , Bruce B. Pedersen , James G. Schleicher, II
发明人： Michael D. Hutton , Bruce B. Pedersen , James G. Schleicher, II
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17732
摘要： The present invention, generally speaking, relates to taking advantage of existing outputs from logic groupings that neighbor a digital signal processing block in a programmable logic device to expand the functionality of the digital signal processing block. The outputs from the logic groupings are used as dedicated routing interconnects that provide additional inputs into the digital signal processing block (e.g., into function specific blocks) such that the signal processing block receives additional signals. These additional signals can be input into the signal processing block via the dedicated routing interconnect without significant addition of input interconnection resources that are silicon-area expensive.
摘要翻译：本发明一般来说涉及利用与可编程逻辑器件中的数字信号处理块相邻的逻辑组的现有输出来扩展数字信号处理块的功能。来自逻辑组的输出被用作为数字信号处理块（例如，转换为功能特定块）提供附加输入的专用路由互连，使得信号处理块接收附加信号。这些附加信号可以经由专用路由互连而被输入到信号处理块中，而不会显着增加硅区域昂贵的输入互连资源。

9. 发明申请

US20130176052A1 INTEGRATED CIRCUITS WITH SHARED INTERCONNECT BUSES 有权
标题翻译：集成电路与共享互连总线
公开(公告)号：US20130176052A1
公开(公告)日：2013-07-11
申请号：US13345564
申请日：2012-01-06
申请人： Michael D. Hutton , David Lewis
发明人： Michael D. Hutton , David Lewis
IPC分类号： H03K19/177
CPC分类号： H03K19/17764 , H03K19/17736
摘要： An integrated circuit may include programmable logic regions coupled in parallel to an interconnect bus. Multiplexing circuitry may be interposed between the programmable logic regions and the interconnect bus. The multiplexing circuitry may be formed from multiplexing circuits formed in a cascade structure. The multiplexing circuitry may dynamically receive control signals that determines which programmable logic region is allowed to drive output signals onto the interconnect bus. Alternatively, each programmable logic region may have an associated output circuit that is coupled to the interconnect bus. The output circuits may be dynamically controlled by control circuitry. The output circuits may receive control signals from the control circuitry that selectively enable and selectively disable the output circuits. The output circuits may be formed with logic circuitry that ensures that the interconnect bus is not simultaneously driven by the output circuits.
摘要翻译：集成电路可以包括与互连总线并联耦合的可编程逻辑区域。多路复用电路可以插在可编程逻辑区和互连总线之间。复用电路可以由级联结构中形成的多路复用电路形成。复用电路可以动态地接收控制信号，该控制信号确定允许哪个可编程逻辑区域将输出信号驱动到互连总线上。或者，每个可编程逻辑区域可以具有耦合到互连总线的相关联的输出电路。输出电路可以由控制电路动态控制。输出电路可以接收来自控制电路的控制信号，其选择性地启用和选择性地禁用输出电路。输出电路可以由确保互连总线不由输出电路同时驱动的逻辑电路形成。

10. 发明授权

US08112728B1 Early timing estimation of timing statistical properties of placement 有权
标题翻译：时间安排的时间统计性质的早期时间估计
公开(公告)号：US08112728B1
公开(公告)日：2012-02-07
申请号：US12539070
申请日：2009-08-11
申请人： Michael D. Hutton , David Karchmer
发明人： Michael D. Hutton , David Karchmer
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5036 , G06F17/5031
摘要： A performance estimation module estimates the performance values of user designs in early phases of compilation and accounts for the performance variability introduced by subsequent compilation phases. The user design is parameterized. The performance estimation model outputs a probability distribution function of estimated performance values of the user design, based upon this parameterization. The performance estimation model is created by parameterizing sample designs. The sample designs are compiled and analyzed to determine their performance values. To account for random variability in compilation phases, the module compiles and analyzes sample designs multiple times. The performance estimation model is created from the relationship between sample designs' performance values and their parameterizations. A regression analysis may be used to determine this relationship. The performance estimation model can be updated with the analysis of compiled user designs. The performance values can include timing, power, and resource consumption.
摘要翻译：性能估计模块在编译的早期阶段估计用户设计的性能价值，并考虑随后编译阶段引入的性能变异性。用户设计参数化。基于该参数化，性能估计模型输出用户设计的估计性能值的概率分布函数。通过参数化样本设计创建性能估计模型。样本设计被编译和分析以确定其性能值。为了解决编译阶段的随机变化，模块多次对样本进行编译和分析。性能估计模型是根据样本设计的性能值与参数化之间的关系来创建的。可以使用回归分析来确定这种关系。可以通过编译用户设计的分析来更新性能估计模型。性能值可以包括时序，功率和资源消耗。

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