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1. 发明申请

US20120017186A1 SPECIFYING CIRCUIT LEVEL CONNECTIVITY DURING CIRCUIT DESIGN SYNTHESIS 有权
标题翻译：在电路设计合成期间指定电路电平连接
公开(公告)号：US20120017186A1
公开(公告)日：2012-01-19
申请号：US12835780
申请日：2010-07-14
申请人： Michael D. Amundson , Dorothy Kucar , Ruchir Puri , Chin Ngai Sze , Matthew M. Ziegler
发明人： Michael D. Amundson , Dorothy Kucar , Ruchir Puri , Chin Ngai Sze , Matthew M. Ziegler
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Exemplary embodiments include a method for modifying a circuit synthesis flow having automated instructions, the method including receiving circuit design input for a circuit design, receiving custom specifications to the circuit design input, synthesizing high level logic from the circuit design input, placing logic on the circuit design, refining the circuit design and generating a circuit description from the circuit design.
摘要翻译：示例性实施例包括用于修改具有自动指令的电路合成流的方法，该方法包括接收用于电路设计的电路设计输入，接收电路设计输入的定制规范，从电路设计输入合成高电平逻辑，将逻辑放置在电路设计，精简电路设计，并从电路设计中产生电路描述。

2. 发明授权

US08839162B2 Specifying circuit level connectivity during circuit design synthesis 有权
标题翻译：在电路设计合成期间指定电路级连接
公开(公告)号：US08839162B2
公开(公告)日：2014-09-16
申请号：US12835780
申请日：2010-07-14
申请人： Michael D. Amundson , Dorothy Kucar , Ruchir Puri , Chin Ngai Sze , Matthew M. Ziegler
发明人： Michael D. Amundson , Dorothy Kucar , Ruchir Puri , Chin Ngai Sze , Matthew M. Ziegler
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5045
摘要： Exemplary embodiments include a method for modifying a circuit synthesis flow having automated instructions, the method including receiving circuit design input for a circuit design, receiving custom specifications to the circuit design input, synthesizing high level logic from the circuit design input, placing logic on the circuit design, refining the circuit design and generating a circuit description from the circuit design.
摘要翻译：示例性实施例包括用于修改具有自动指令的电路合成流的方法，该方法包括接收用于电路设计的电路设计输入，接收电路设计输入的定制规范，从电路设计输入合成高电平逻辑，将逻辑放置在电路设计，精简电路设计，并从电路设计中产生电路描述。

3. 发明申请

US20120054699A1 CONVERGED LARGE BLOCK AND STRUCTURED SYNTHESIS FOR HIGH PERFORMANCE MICROPROCESSOR DESIGNS 有权
标题翻译：用于高性能微处理器设计的大块和结构化合成
公开(公告)号：US20120054699A1
公开(公告)日：2012-03-01
申请号：US12868086
申请日：2010-08-25
申请人： Minsik Cho , Victor N. Kravets , Smita Krishnaswamy , Dorothy Kucar , Jagannathan Narasimhan , Ruchir Puri , Haifeng Qian , Haoxing Ren , Chin Ngai Sze , Louise H. Trevillyan , Hua Xiang , Matthew M. Ziegler
发明人： Minsik Cho , Victor N. Kravets , Smita Krishnaswamy , Dorothy Kucar , Jagannathan Narasimhan , Ruchir Puri , Haifeng Qian , Haoxing Ren , Chin Ngai Sze , Louise H. Trevillyan , Hua Xiang , Matthew M. Ziegler
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Exemplary embodiments include a computer implemented method for large block and structured synthesis, the method including determining initial design data from starting points for a synthesis flow, receiving user-directed structuring is incorporated into the synthesis flow, applying logical synthesis on the initial design data, applying a physical design on the initial design data, determining whether circuit design parameters have been met and in response to circuit design parameters not being met, adjusting the circuit design parameters.
摘要翻译：示例性实施例包括用于大块和结构化合成的计算机实现的方法，所述方法包括从合成流的起点确定初始设计数据，接收用户导向的结构化被并入到合成流中，对初始设计数据应用逻辑合成，对初始设计数据应用物理设计，确定电路设计参数是否已满足，并响应于电路设计参数不满足，调整电路设计参数。

4. 发明授权

US08271920B2 Converged large block and structured synthesis for high performance microprocessor designs 有权
标题翻译：用于高性能微处理器设计的融合大块和结构化合成
公开(公告)号：US08271920B2
公开(公告)日：2012-09-18
申请号：US12868086
申请日：2010-08-25
申请人： Minsik Cho , Victor N. Kravets , Smita Krishnaswamy , Dorothy Kucar , Jagannathan Narasimhan , Ruchir Puri , Haifeng Qian , Haoxing Ren , Chin Ngai Sze , Louise H. Trevillyan , Hua Xiang , Matthew M. Ziegler
发明人： Minsik Cho , Victor N. Kravets , Smita Krishnaswamy , Dorothy Kucar , Jagannathan Narasimhan , Ruchir Puri , Haifeng Qian , Haoxing Ren , Chin Ngai Sze , Louise H. Trevillyan , Hua Xiang , Matthew M. Ziegler
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Exemplary embodiments include a computer implemented method for large block and structured synthesis, the method including determining initial design data from starting points for a synthesis flow, receiving user-directed structuring is incorporated into the synthesis flow, applying logical synthesis on the initial design data, applying a physical design on the initial design data, determining whether circuit design parameters have been met and in response to circuit design parameters not being met, adjusting the circuit design parameters.
摘要翻译：示例性实施例包括用于大块和结构化合成的计算机实现的方法，所述方法包括从合成流的起点确定初始设计数据，接收用户导向的结构化被并入到合成流中，对初始设计数据应用逻辑合成，对初始设计数据应用物理设计，确定电路设计参数是否已满足，并响应于电路设计参数不满足，调整电路设计参数。

5. 发明授权

US08484594B2 Routing-based pin placement 失效
标题翻译：基于路由的引脚放置
公开(公告)号：US08484594B2
公开(公告)日：2013-07-09
申请号：US13005330
申请日：2011-01-12
申请人： Dorothy Kucar , Jarrod A. Roy
发明人： Dorothy Kucar , Jarrod A. Roy
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077 , G06F2217/40
摘要： A method for routing-based pin placement is provided and includes receiving a logical description of a macro of a partitioned circuit with connectivity information and a physical outline, generating an abstracted shape as an abstraction of a generic shape of a pin for providing a connection to the macro in accordance with the connectivity information as a shape conforming to dimensions of the macro, providing a routing tool with freedom to route a net for connection to the pin toward any part of the abstracted shape of the pin to create a routed net and identifying a location where the routed net crosses the physical outline as a chosen location for the pin.
摘要翻译：提供了一种用于基于路由的引脚放置的方法，并且包括接收具有连接信息和物理轮廓的分区电路的宏的逻辑描述，生成抽象形状作为引脚的通用形状的抽象以提供连接所述宏根据所述连接信息作为符合所述宏尺寸的形状，提供布线工具，所述路线工具具有将所述网路连接到所述销的所述引脚的所述抽象形状的任何部分的自由以创建路由网并且识别路由网络将物理轮廓作为引脚的选定位置交叉的位置。

6. 发明申请

US20120180017A1 ROUTING G-BASED PIN PLACEMENT 失效
标题翻译：路由基于G的PIN放置
公开(公告)号：US20120180017A1
公开(公告)日：2012-07-12
申请号：US13005330
申请日：2011-01-12
申请人： Dorothy Kucar , Jarrod A. Roy
发明人： Dorothy Kucar , Jarrod A. Roy
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077 , G06F2217/40
摘要： A method for routing-based pin placement is provided and includes receiving a logical description of a macro of a partitioned circuit with connectivity information and a physical outline, generating an abstracted shape as an abstraction of a generic shape of a pin for providing a connection to the macro in accordance with the connectivity information as a shape conforming to dimensions of the macro, providing a routing tool with freedom to route a net for connection to the pin toward any part of the abstracted shape of the pin to create a routed net and identifying a location where the routed net crosses the physical outline as a chosen location for the pin.
摘要翻译：提供了一种用于基于路由的引脚放置的方法，并且包括接收具有连接信息和物理轮廓的分区电路的宏的逻辑描述，生成抽象形状作为引脚的通用形状的抽象以提供连接所述宏根据所述连接信息作为符合所述宏尺寸的形状，提供布线工具，所述路线工具具有将所述网路连接到所述销的所述引脚的所述抽象形状的任何部分的自由以创建路由网并且识别路由网络将物理轮廓作为引脚的选定位置交叉的位置。

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