专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070268825A1 Fine-grain fairness in a hierarchical switched system 审中-公开
标题翻译：分层交换系统中的细粒度公平
公开(公告)号：US20070268825A1
公开(公告)日：2007-11-22
申请号：US11437186
申请日：2006-05-19
申请人： Michael Corwin , Joseph Chamdani , Stephen Trevitt
发明人： Michael Corwin , Joseph Chamdani , Stephen Trevitt
IPC分类号： H04L12/26
CPC分类号： H04L67/1017 , H04L47/50 , H04L47/60 , H04L67/1002 , H04L67/1008 , H04L67/1097 , H04L67/32
摘要： A scalable solution to managing fairness in a congested hierarchical switched system is disclosed. The solution comprises a means for managing fairness during congestion in a hierarchical switched system comprising a first level arbitration system and a second level arbitration system of a stage. The first level arbitration system comprises a plurality of arbitration segments that arbitrate between information flows received from at least one ingress point based upon weights associated with those information flows (or the ingress points). Each arbitration segment determines an aggregate weight from each active ingress point providing the information flows to the segment and forwards a selected information flow along with the aggregate weight (in-band or out-of-band) to the second level arbitration system. The second level arbitration system then arbitrates between information flows received from the arbitration segments of the first level arbitration system based upon the aggregate weights received along with those information flows. The second level arbitration system then forwards a selected information flow to an egress point of the stage. The stage may, for example, comprise a portion of a switch, a switch, or a switch network.
摘要翻译：公开了一种用于管理拥塞分层交换系统中的公平性的可扩展解决方案。解决方案包括一种用于管理分层交换系统中的拥塞期间的公平性的装置，包括阶段的第一级仲裁系统和第二级仲裁系统。第一级仲裁系统包括多个仲裁段，其根据与这些信息流（或入口点）相关联的权重来仲裁从至少一个入口点接收的信息流之间。每个仲裁段确定来自每个活动入口点的聚合权重，提供信息流到段，并将所选择的信息流与带宽或带外的总权重一起转发到第二级仲裁系统。然后，第二级仲裁系统基于与这些信息流一起接收的总权重，在从第一级仲裁系统的仲裁段接收的信息流之间进行仲裁。然后，第二级仲裁系统将所选择的信息流转发到舞台的出口点。舞台可以例如包括开关的一部分，开关或开关网络。

2. 发明授权

US07952997B2 Congestion management groups 有权
标题翻译：拥塞管理组
公开(公告)号：US07952997B2
公开(公告)日：2011-05-31
申请号：US11437389
申请日：2006-05-18
申请人： Michael Corwin , Joseph Chamdani , Stephen Trevitt
发明人： Michael Corwin , Joseph Chamdani , Stephen Trevitt
IPC分类号： H04J3/14
CPC分类号： H04L47/10 , H04L47/11 , H04L47/22 , H04L47/30
摘要： A scalable solution to managing congestion in a network is disclosed. In one implementation, such a solution comprises a means for managing traffic including at least one flow monitor and a plurality of flow control regulators that together manage congestion within a network. Each of the flow control regulators monitor traffic at a corresponding ingress point and determine a state of the ingress point corresponding to the traffic monitored at the ingress point. Each flow control regulators forward the state (or information representative of the state) to the flow monitor. The flow monitor detects congestion based upon the states of the flow control regulators and, in the event of congestion, determines a target bandwidth for the ingress points. The flow monitor provides a control signal to at least one of the flow control regulators, and at least one of the flow control regulators control flows at its corresponding ingress point based upon the control signal received from the flow monitor.
摘要翻译：公开了一种用于管理网络拥塞的可扩展解决方案。在一个实现中，这样的解决方案包括用于管理流量的装置，其包括一起管理网络内的拥塞的至少一个流量监视器和多个流量控制调节器。每个流量控制调节器监视相应进入点处的流量，并确定与入口点处监控的流量相对应的入口点的状态。每个流量控制调节器将状态（或表示状态的信息）转发到流量监视器。流量监视器基于流量控制调节器的状态来检测拥塞，并且在拥塞的情况下，确定入口点的目标带宽。流量监控器向至少一个流量控制调节器提供控制信号，并且流量控制调节器中的至少一个基于从流量监视器接收到的控制信号在其对应的入口点处控制流量。

3. 发明申请

US20070268829A1 Congestion management groups 有权
标题翻译：拥塞管理组
公开(公告)号：US20070268829A1
公开(公告)日：2007-11-22
申请号：US11437389
申请日：2006-05-18
申请人： Michael Corwin , Joseph Chamdani , Stephen Trevitt
发明人： Michael Corwin , Joseph Chamdani , Stephen Trevitt
IPC分类号： G06F15/173 , H04J1/16
CPC分类号： H04L47/10 , H04L47/11 , H04L47/22 , H04L47/30
摘要： A scalable solution to managing congestion in a network is disclosed. In one implementation, such a solution comprises a means for managing traffic including at least one flow monitor and a plurality of flow control regulators that together manage congestion within a network. Each of the flow control regulators monitor traffic at a corresponding ingress point and determine a state of the ingress point corresponding to the traffic monitored at the ingress point. Each flow control regulators forward the state (or information representative of the state) to the flow monitor. The flow monitor detects congestion based upon the states of the flow control regulators and, in the event of congestion, determines a target bandwidth for the ingress points. The flow monitor provides a control signal to at least one of the flow control regulators, and at least one of the flow control regulators control flows at its corresponding ingress point based upon the control signal received from the flow monitor.
摘要翻译：公开了一种用于管理网络拥塞的可扩展解决方案。在一个实现中，这样的解决方案包括用于管理流量的装置，其包括一起管理网络内的拥塞的至少一个流量监视器和多个流量控制调节器。每个流量控制调节器监视相应进入点处的流量，并确定与入口点处监控的流量相对应的入口点的状态。每个流量控制调节器将状态（或表示状态的信息）转发到流量监视器。流量监视器基于流量控制调节器的状态来检测拥塞，并且在拥塞的情况下，确定入口点的目标带宽。流量监控器向至少一个流量控制调节器提供控制信号，并且流量控制调节器中的至少一个基于从流量监视器接收到的控制信号在其对应的入口点处控制流量。

4. 发明申请

US20070258380A1 Fault detection, isolation and recovery for a switch system of a computer network 审中-公开
标题翻译：计算机网络交换机系统的故障检测，隔离和恢复
公开(公告)号：US20070258380A1
公开(公告)日：2007-11-08
申请号：US11417087
申请日：2006-05-02
申请人： Joseph Chamdani , Michael Corwin , Joseph Pelissier , Michael Crater
发明人： Joseph Chamdani , Michael Corwin , Joseph Pelissier , Michael Crater
IPC分类号： H04J1/16 , H04L12/28
CPC分类号： H04L49/557 , H04L49/357 , H04L49/555
摘要： A method, system or switch device, the switch device being one of a ported and a non-ported switch device, either of which including a housing containing an ASIC providing a switching system within the switch device, the housing further including a plurality of extender ports communicating with the ASIC and being connectable to themselves either in loopback fashion or to one or more ported or non-ported switch devices, whereby the extender ports operate on a discrete protocol from standard switch ports. The ported switch device further includes a plurality of standard ports connectable to one or more external computer network devices. A switch device hereof is adapted to send and/or receive an identification communication, the identification communication adapted to be indicative of the health of a switch device or a connecting link in a switch system.
摘要翻译：一种方法，系统或开关装置，所述开关装置是移动式和非端口式开关装置之一，所述开关装置中的任一种包括壳体，所述壳体包含在开关装置内提供开关系统的ASIC，所述壳体还包括多个延长器端口与ASIC通信并且以环回方式连接到自身或者连接到一个或多个端口或非端口交换设备，由此扩展器端口以标准交换机端口的离散协议操作。端口交换设备还包括可连接到一个或多个外部计算机网络设备的多个标准端口。本发明的开关装置适于发送和/或接收识别通信，所述识别通信适于指示交换机设备或连接链路在交换系统中的健康状况。

5. 发明申请

US20070258443A1 Switch hardware and architecture for a computer network 审中-公开
标题翻译：切换计算机网络的硬件和架构
公开(公告)号：US20070258443A1
公开(公告)日：2007-11-08
申请号：US11417075
申请日：2006-05-02
申请人： Joseph Chamdani , Raj Cherabuddi , Michael Corwin , Yu Fang , Joseph Pelissier
发明人： Joseph Chamdani , Raj Cherabuddi , Michael Corwin , Yu Fang , Joseph Pelissier
IPC分类号： H04L12/50
CPC分类号： H04L49/45 , H04L49/357 , H04L49/40
摘要： A method, system or switch device, the switch device being one of a ported and a non-ported switch device, both including a housing containing an ASIC providing a switching system within the switch device; the housing further including a plurality of extender ports communicating with the ASIC and being connectable to themselves either in loopback fashion or to one or more ported or non-ported switch devices, whereby the extender ports operate on a discrete protocol from standard switch ports. The ported switch device further includes a plurality of standard ports connectable to one or more external computer network devices and is adapted to be operable as a switch system in an independent standalone mode as well as being adapted to be operable in conjunction with a discrete non-ported switch device.
摘要翻译：一种方法，系统或开关装置，所述开关装置是移动式和非端口式开关装置之一，两者都包括壳体，所述外壳包含提供所述开关装置内的开关系统的ASIC; 壳体还包括与ASIC通信的多个扩展器端口，并且可以以环回方式连接到它们自身或者连接到一个或多个端口或非端口交换设备，由此扩展器端口以标准交换机端口的离散协议操作。移植的交换设备还包括可连接到一个或多个外部计算机网络设备的多个标准端口，并且适于作为独立独立模式中的交换机系统操作，并且适于与离散非易失性存储器移植开关设备。

6. 发明申请

US20100082895A1 MULTI-LEVEL CONTENT ADDRESSABLE MEMORY 审中-公开
标题翻译：多级内容可寻址存储器
公开(公告)号：US20100082895A1
公开(公告)日：2010-04-01
申请号：US12567624
申请日：2009-09-25
申请人： Jeremy Branscome , Michael Corwin
发明人： Jeremy Branscome , Michael Corwin
IPC分类号： G06F12/00
CPC分类号： G11C15/00
摘要： A multi-level content addressable memory (CAM) architecture compresses out much of the redundancy encountered in the search space of a single CAM, particularly for flow-based lookups in a network. Destination and source address may be associated with internal equivalence classes independently in one level of the multi-level CAM architecture, while flow-specific properties linking arbitrary classes of the destination and source addresses may be applied in a later level of the multi-level CAM.
摘要翻译：多级内容可寻址存储器（CAM）架构压缩了单个CAM的搜索空间中遇到的冗余，特别是对于网络中的基于流的查找。目的地址和源地址可以在多级CAM架构的一个级别中独立地与内部等价类相关联，而链接目的地址和源地址的任意类别的流特定属性可以应用于多级CAM的后一级。

7. 发明申请

US20090254516A1 ACCESSING DATA IN A COLUMN STORE DATABASE BASED ON HARDWARE COMPATIBLE INDEXING AND REPLICATED REORDERED COLUMNS 有权
标题翻译：基于硬件兼容的索引和已更新的列进行存储数据库中的数据访问
公开(公告)号：US20090254516A1
公开(公告)日：2009-10-08
申请号：US12099133
申请日：2008-04-07
申请人： Krishnan Meiyyappan , Liuxi Yang , Jeremy Branscome , Michael Corwin , Ravi Krishnamurthy , Kapil Surlaker , James Shau , Joseph I. Chamdani
发明人： Krishnan Meiyyappan , Liuxi Yang , Jeremy Branscome , Michael Corwin , Ravi Krishnamurthy , Kapil Surlaker , James Shau , Joseph I. Chamdani
IPC分类号： G06F7/06 , G06F17/30
CPC分类号： G06F17/30442 , G06F17/30094 , G06F17/30315 , G06F17/30492 , G06F17/30504
摘要： Embodiments of the present invention provide hardware-friendly indexing of databases. In particular, forward and reverse indexing are utilized to allow for easy traversal of primary key to foreign key relationships. A novel structure known as a hit list also allows for easy scanning of various indexes in hardware. Group indexing is provided for flexible support of complex group key definition, such as for date range indexing and text indexing. A Replicated Reordered Column (RRC) may also be added to the group index to convert random I/O pattern into sequential I/O of only needed column elements.
摘要翻译：本发明的实施例提供数据库的硬件友好索引。特别地，正向和反向索引被用于允许轻松地遍历主键到外键关系。被称为命中列表的新颖结构还允许在硬件中容易地扫描各种索引。提供组索引，用于复杂组密钥定义的灵活支持，如日期范围索引和文本索引。还可以将复制的重新排列（RRC）添加到组索引中以将随机I / O模式转换为仅需要的列元素的顺序I / O。

8. 发明授权

US08234267B2 Hardware accelerated reconfigurable processor for accelerating database operations and queries 有权
标题翻译：硬件加速可重构处理器，用于加速数据库操作和查询
公开(公告)号：US08234267B2
公开(公告)日：2012-07-31
申请号：US13048031
申请日：2011-03-15
申请人： Jeremy Branscome , Michael Corwin , Liuxi Yang , Joseph I. Chamdani
发明人： Jeremy Branscome , Michael Corwin , Liuxi Yang , Joseph I. Chamdani
IPC分类号： G06F7/00 , G06F17/30
CPC分类号： G06F17/30442
摘要： Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system. For example, table and column descriptors are embedded in the machine code database instructions. For ease of installation, the hardware accelerators employ a standard interconnect, such as a PCle or HT interconnect. The processing elements implement a novel dataflow design and Inter Macro-Op Communication (IMC) data structures to execute the machine code database instructions. The hardware accelerator may also comprise a relatively large memory to enhance the hardware execution of the query/operation tasks requested. The hardware accelerator utilizes hardware-friendly memory addressing, which allows for arithmetic derivation of a physical address from a global database virtual address simply based on a row identifier. The hardware accelerator minimizes memory reads/writes by keeping most intermediate results flowing through IMCs in pipelined and parallel fashion. Furthermore, the hardware accelerator may employ task pipelining and pre-fetch pipelining to enhance its performance.
摘要翻译：本发明的实施例提供了一种辅助主机数据库系统处理其查询的硬件加速器。硬件加速器包括能够以机器码数据库指令的形式接收数据库查询/操作任务的专用处理元件，无需软件执行硬件，并将查询/运算结果返回主机系统。例如，表和列描述符嵌入在机器码数据库指令中。为了便于安装，硬件加速器采用标准互连，如PCle或HT互连。处理元件实现了一种新颖的数据流设计和Inter Macro-Op Communication（IMC）数据结构来执行机器码数据库指令。硬件加速器还可以包括相对大的存储器，以增强所请求的查询/操作任务的硬件执行。硬件加速器使用硬件友好的存储器寻址，这允许仅仅基于行标识符从全局数据库虚拟地址算术推导物理地址。硬件加速器通过保持大多数中间结果以流水线和并行方式流过IMC来最小化存储器读/写。此外，硬件加速器可以采用任务流水线和预取流水线来增强其性能。

9. 发明申请

US20100005077A1 METHODS AND SYSTEMS FOR GENERATING QUERY PLANS THAT ARE COMPATIBLE FOR EXECUTION IN HARDWARE 审中-公开
标题翻译：用于产生兼容硬件执行的查询计划的方法和系统
公开(公告)号：US20100005077A1
公开(公告)日：2010-01-07
申请号：US12168821
申请日：2008-07-07
申请人： Ravi Krishnamurthy , Chi-Young Ku , James Shau , Chun Zhang , Kapil Surlaker , Jeremy Branscome , Michael Corwin , Joseph I. Chamdani
发明人： Ravi Krishnamurthy , Chi-Young Ku , James Shau , Chun Zhang , Kapil Surlaker , Jeremy Branscome , Michael Corwin , Joseph I. Chamdani
IPC分类号： G06F17/30
CPC分类号： G06F16/24542
摘要： Embodiments of the present invention generate and optimize query plans that are at least partially executable in hardware. Upon receiving a query, the query is rewritten and optimized with a bias for hardware execution of fragments of the query. A template-based algorithm may be employed for transforming a query into fragments and then into query tasks. The various query tasks can then be routed to either a hardware accelerator, a software module, or sent back to a database management system for execution. For those tasks routed to the hardware accelerator, the query tasks are compiled into machine code database instructions. In order to optimize query execution, query tasks may be broken into subtasks, rearranged based on available resources of the hardware, pipelined, or branched conditionally
摘要翻译：本发明的实施例生成和优化在硬件中至少部分可执行的查询计划。在接收到查询后，查询将被重写和优化，以便查询的片段的硬件执行偏差。可以采用基于模板的算法将查询转换成片段，然后转换为查询任务。然后可以将各种查询任务路由到硬件加速器，软件模块，或者发送回数据库管理系统以执行。对于路由到硬件加速器的任务，将查询任务编译为机器码数据库指令。为了优化查询执行，查询任务可能被分解为子任务，根据硬件的可用资源，流水线或有条件的分支进行重新排列

10. 发明授权

US07606968B2 Multi-level content addressable memory 有权
标题翻译：多层内容可寻址内存
公开(公告)号：US07606968B2
公开(公告)日：2009-10-20
申请号：US11430389
申请日：2006-05-08
申请人： Jeremy Branscome , Michael Corwin
发明人： Jeremy Branscome , Michael Corwin
IPC分类号： G06F12/00
CPC分类号： G11C15/00
摘要： A multi-level content addressable memory (CAM) architecture compresses out much of the redundancy encountered in the search space of a single CAM, particularly for flow-based lookups in a network. Destination and source address may be associated with internal equivalence classes independently in one level of the multi-level CAM architecture, while flow-specific properties linking arbitrary classes of the destination and source addresses may be applied in a later level of the multi-level CAM.
摘要翻译：多级内容可寻址存储器（CAM）架构压缩了单个CAM的搜索空间中遇到的冗余，特别是对于网络中的基于流的查找。目的地址和源地址可以在多级CAM架构的一个级别中独立地与内部等价类相关联，而链接目的地址和源地址的任意类别的流特定属性可以应用于多级CAM的后一级。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式