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1. 发明授权

US08234267B2 Hardware accelerated reconfigurable processor for accelerating database operations and queries 有权
标题翻译：硬件加速可重构处理器，用于加速数据库操作和查询
公开(公告)号：US08234267B2
公开(公告)日：2012-07-31
申请号：US13048031
申请日：2011-03-15
申请人： Jeremy Branscome , Michael Corwin , Liuxi Yang , Joseph I. Chamdani
发明人： Jeremy Branscome , Michael Corwin , Liuxi Yang , Joseph I. Chamdani
IPC分类号： G06F7/00 , G06F17/30
CPC分类号： G06F17/30442
摘要： Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system. For example, table and column descriptors are embedded in the machine code database instructions. For ease of installation, the hardware accelerators employ a standard interconnect, such as a PCle or HT interconnect. The processing elements implement a novel dataflow design and Inter Macro-Op Communication (IMC) data structures to execute the machine code database instructions. The hardware accelerator may also comprise a relatively large memory to enhance the hardware execution of the query/operation tasks requested. The hardware accelerator utilizes hardware-friendly memory addressing, which allows for arithmetic derivation of a physical address from a global database virtual address simply based on a row identifier. The hardware accelerator minimizes memory reads/writes by keeping most intermediate results flowing through IMCs in pipelined and parallel fashion. Furthermore, the hardware accelerator may employ task pipelining and pre-fetch pipelining to enhance its performance.
摘要翻译：本发明的实施例提供了一种辅助主机数据库系统处理其查询的硬件加速器。硬件加速器包括能够以机器码数据库指令的形式接收数据库查询/操作任务的专用处理元件，无需软件执行硬件，并将查询/运算结果返回主机系统。例如，表和列描述符嵌入在机器码数据库指令中。为了便于安装，硬件加速器采用标准互连，如PCle或HT互连。处理元件实现了一种新颖的数据流设计和Inter Macro-Op Communication（IMC）数据结构来执行机器码数据库指令。硬件加速器还可以包括相对大的存储器，以增强所请求的查询/操作任务的硬件执行。硬件加速器使用硬件友好的存储器寻址，这允许仅仅基于行标识符从全局数据库虚拟地址算术推导物理地址。硬件加速器通过保持大多数中间结果以流水线和并行方式流过IMC来最小化存储器读/写。此外，硬件加速器可以采用任务流水线和预取流水线来增强其性能。

2. 发明申请

US20060095584A1 Semantic-based switch fabric OS 审中-公开
标题翻译：基于语义的交换架构OS
公开(公告)号：US20060095584A1
公开(公告)日：2006-05-04
申请号：US10988114
申请日：2004-11-12
申请人： Vikas Deolaliker , Udayakumar Subbarayan , Liuxi Yang , Jay Sethuram
发明人： Vikas Deolaliker , Udayakumar Subbarayan , Liuxi Yang , Jay Sethuram
IPC分类号： G06F15/173
CPC分类号： H04L67/16 , H04L67/02
摘要： A operating system creates a semantic-based platform or fabric that provides a service oriented network. The operating system assigns virtual addresses to services registered with the network. Messages for the services are sent by service requesters using their virtual addresses. The virtual address is then mapped to the actual address of the service provider, which is then sent to the intended service provider. The messages are processed according to an SOA stack, where messages can be routed at the virtual IP, transport, or message layer without the need to process the message at the IP layer. The web services can be classified into a service zone, with the zone exposed to a service requester as a single entity. The zone is an independent domain, with communication within the zone managed by a semantic-based switch in the switch fabric.
摘要翻译：操作系统创建一个提供面向服务的网络的基于语义的平台或架构。操作系统为在网络注册的服务分配虚拟地址。服务请求者使用其虚拟地址发送服务的消息。然后将虚拟地址映射到服务提供商的实际地址，然后将其发送到预期的服务提供商。消息根据SOA堆栈进行处理，其中可以在虚拟IP，传输或消息层路由消息，而不需要在IP层处理消息。 Web服务可以分为服务区域，区域作为单个实体暴露给服务请求者。该区域是一个独立的域，通过交换结构中基于语义的交换机管理的区域内的通信。

3. 发明授权

US06725347B2 Spin-wheel SDRAM access scheduler for high performance microprocessors 有权
标题翻译：用于高性能微处理器的Spin-wheel SDRAM访问调度程序
公开(公告)号：US06725347B2
公开(公告)日：2004-04-20
申请号：US09760678
申请日：2001-01-16
申请人： Liuxi Yang , Duong Tong
发明人： Liuxi Yang , Duong Tong
IPC分类号： G06F1200
CPC分类号： G06F13/1621 , G06F13/1642
摘要： A memory control unit has been developed. The control unit includes a command “spin wheel” which schedules the order of read and write commands to the memory. It also includes a read “spin wheel” which ensures proper timing of the read commands and a write “spin wheel” which ensures proper timing of the write commands.
摘要翻译：已经开发了存储器控制单元。控制单元包括一个命令“旋转轮”，该命令将读取和写入命令的顺序排列到存储器中。它还包括一个读取“旋转轮”，确保读取命令的正确定时和写入“旋转轮”，从而确保写入命令的正确定时。

4. 发明申请

US20110167083A1 HARDWARE ACCELERATED RECONFIGURABLE PROCESSOR FOR ACCELERATING DATABASE OPERATIONS AND QUERIES 有权
公开(公告)号：US20110167083A1
公开(公告)日：2011-07-07
申请号：US13048015
申请日：2011-03-15
申请人： JEREMY BRANSCOME , MICHAEL CORWIN , LIUXI YANG , JOSEPH I. CHAMDANI
发明人： JEREMY BRANSCOME , MICHAEL CORWIN , LIUXI YANG , JOSEPH I. CHAMDANI
IPC分类号： G06F17/30
CPC分类号： G06F17/30442
摘要： Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system. For example, table and column descriptors are embedded in the machine code database instructions. For ease of installation, the hardware accelerators employ a standard interconnect, such as a PCle or HT interconnect. The processing elements implement a novel dataflow design and Inter Macro-Op Communication (IMC) data structures to execute the machine code database instructions. The hardware accelerator may also comprise a relatively large memory to enhance the hardware execution of the query/operation tasks requested. The hardware accelerator utilizes hardware-friendly memory addressing, which allows for arithmetic derivation of a physical address from a global database virtual address simply based on a row identifier. The hardware accelerator minimizes memory reads/writes by keeping most intermediate results flowing through IMCs in pipelined and parallel fashion. Furthermore, the hardware accelerator may employ task pipelining and pre-fetch pipelining to enhance its performance.

5. 发明申请

US20090254516A1 ACCESSING DATA IN A COLUMN STORE DATABASE BASED ON HARDWARE COMPATIBLE INDEXING AND REPLICATED REORDERED COLUMNS 有权
标题翻译：基于硬件兼容的索引和已更新的列进行存储数据库中的数据访问
公开(公告)号：US20090254516A1
公开(公告)日：2009-10-08
申请号：US12099133
申请日：2008-04-07
申请人： Krishnan Meiyyappan , Liuxi Yang , Jeremy Branscome , Michael Corwin , Ravi Krishnamurthy , Kapil Surlaker , James Shau , Joseph I. Chamdani
发明人： Krishnan Meiyyappan , Liuxi Yang , Jeremy Branscome , Michael Corwin , Ravi Krishnamurthy , Kapil Surlaker , James Shau , Joseph I. Chamdani
IPC分类号： G06F7/06 , G06F17/30
CPC分类号： G06F17/30442 , G06F17/30094 , G06F17/30315 , G06F17/30492 , G06F17/30504
摘要： Embodiments of the present invention provide hardware-friendly indexing of databases. In particular, forward and reverse indexing are utilized to allow for easy traversal of primary key to foreign key relationships. A novel structure known as a hit list also allows for easy scanning of various indexes in hardware. Group indexing is provided for flexible support of complex group key definition, such as for date range indexing and text indexing. A Replicated Reordered Column (RRC) may also be added to the group index to convert random I/O pattern into sequential I/O of only needed column elements.
摘要翻译：本发明的实施例提供数据库的硬件友好索引。特别地，正向和反向索引被用于允许轻松地遍历主键到外键关系。被称为命中列表的新颖结构还允许在硬件中容易地扫描各种索引。提供组索引，用于复杂组密钥定义的灵活支持，如日期范围索引和文本索引。还可以将复制的重新排列（RRC）添加到组索引中以将随机I / O模式转换为仅需要的列元素的顺序I / O。

6. 发明授权

US07539929B1 Error correction for data communication 失效
标题翻译：数据通信纠错
公开(公告)号：US07539929B1
公开(公告)日：2009-05-26
申请号：US11154886
申请日：2005-06-15
申请人： Ulrich Stern , Joseph I. Chamdani , Yu Fang , Liuxi Yang
发明人： Ulrich Stern , Joseph I. Chamdani , Yu Fang , Liuxi Yang
IPC分类号： H03M13/00 , G06F11/00
CPC分类号： H03M13/13
摘要： Generating a check matrix includes defining a generator function operable to yield check bits associated with a word. A set of primitive elements is calculated from the generator function. A set of check matrix columns is generated, where each check matrix column includes a matrix having a subset of the set of primitive elements. A check matrix is generated from a subset of the set of check matrix columns, where the check matrix yields a syndrome that comprises an error pattern for the word. The check matrix is reported.
摘要翻译：生成校验矩阵包括定义发生器功能，其可操作以产生与单词相关联的校验位。从生成函数计算一组原始元素。生成一组校验矩阵列，其中每个校验矩阵列包括具有该组原始元素的子集的矩阵。从校验矩阵列集合的子集生成校验矩阵，其中校验矩阵产生包括该单词的错误模式的校正子。报告校验矩阵。

7. 发明授权

US09378231B2 Accessing data in column store database based on hardware compatible data structures 有权
标题翻译：基于硬件兼容的数据结构访问列存储数据库中的数据
公开(公告)号：US09378231B2
公开(公告)日：2016-06-28
申请号：US13107399
申请日：2011-05-13
申请人： Liuxi Yang , Kapil Surlaker , Ravi Krishnamurthy , Michael Corwin , Jeremy Branscome , Krishnan Meiyyappan , Joseph I. Chamdani
发明人： Liuxi Yang , Kapil Surlaker , Ravi Krishnamurthy , Michael Corwin , Jeremy Branscome , Krishnan Meiyyappan , Joseph I. Chamdani
IPC分类号： G06F17/30
CPC分类号： G06F17/30315
摘要： Embodiments of the present invention provide one or more hardware-friendly data structures that enable efficient hardware acceleration of database operations. In particular, the present invention employs a column-store format for the database. In the database, column-groups are stored with implicit row ids (RIDs) and a RID-to-primary key column having both column-store and row-store benefits via column hopping and a heap structure for adding new data. Fixed-width column compression allow for easy hardware database processing directly on the compressed data. A global database virtual address space is utilized that allows for arithmetic derivation of any physical address of the data regardless of its location. A word compression dictionary with token compare and sort index is also provided to allow for efficient hardware-based searching of text. A tuple reconstruction process is provided as well that allows hardware to reconstruct a row by stitching together data from multiple column groups.
摘要翻译：本发明的实施例提供了一个或多个能够有效地加速数据库操作的硬件友好的数据结构。特别地，本发明采用数据库的列存储格式。在数据库中，列组通过列跳转和用于添加新数据的堆结构存储隐式行ids（RID）和具有列存储和行存储优势的RID至主键列。固定宽度列压缩允许直接对压缩数据进行硬件数据库处理。使用全局数据库虚拟地址空间，允许对数据的任何物理地址的算术推导，而不管其位置如何。还提供了具有令牌比较和排序索引的单词压缩字典，以允许对文本进行高效的基于硬件的搜索。还提供了一个元组重建过程，允许硬件通过将来自多个列组的数据进行拼接来重建行。

8. 发明申请

US20110218987A1 HARDWARE ACCELERATED RECONFIGURABLE PROCESSOR FOR ACCELERATING DATABASE OPERATIONS AND QUERIES 有权
标题翻译：用于加速数据库操作和查询的硬件加速可重构处理器
公开(公告)号：US20110218987A1
公开(公告)日：2011-09-08
申请号：US13048024
申请日：2011-03-15
申请人： JEREMY BRANSCOME , MICHAEL CORWIN , LIUXI YANG , JOSEPH I. CHAMDANI
发明人： JEREMY BRANSCOME , MICHAEL CORWIN , LIUXI YANG , JOSEPH I. CHAMDANI
IPC分类号： G06F7/00 , G06F17/30
CPC分类号： G06F17/30442
摘要： Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system. For example, table and column descriptors are embedded in the machine code database instructions. For ease of installation, the hardware accelerators employ a standard interconnect, such as a PCle or HT interconnect. The processing elements implement a novel dataflow design and Inter Macro-Op Communication (IMC) data structures to execute the machine code database instructions. The hardware accelerator may also comprise a relatively large memory to enhance the hardware execution of the query/operation tasks requested. The hardware accelerator utilizes hardware-friendly memory addressing, which allows for arithmetic derivation of a physical address from a global database virtual address simply based on a row identifier. The hardware accelerator minimizes memory reads/writes by keeping most intermediate results flowing through IMCs in pipelined and parallel fashion. Furthermore, the hardware accelerator may employ task pipelining and pre-fetch pipelining to enhance its performance.
摘要翻译：本发明的实施例提供了一种辅助主机数据库系统处理其查询的硬件加速器。硬件加速器包括能够以机器码数据库指令的形式接收数据库查询/操作任务的专用处理元件，无需软件执行硬件，并将查询/运算结果返回主机系统。例如，表和列描述符嵌入在机器码数据库指令中。为了便于安装，硬件加速器采用标准互连，如PCle或HT互连。处理元件实现了一种新颖的数据流设计和Inter Macro-Op Communication（IMC）数据结构来执行机器码数据库指令。硬件加速器还可以包括相对大的存储器，以增强所请求的查询/操作任务的硬件执行。硬件加速器使用硬件友好的存储器寻址，这允许仅仅基于行标识符从全局数据库虚拟地址算术推导物理地址。硬件加速器通过保持大多数中间结果以流水线和并行方式流过IMC来最小化存储器读/写。此外，硬件加速器可以采用任务流水线和预取流水线来增强其性能。

9. 发明申请

US20110167055A1 HARDWARE ACCELERATED RECONFIGURABLE PROCESSOR FOR ACCELERATING DATABASE OPERATIONS AND QUERIES 有权
公开(公告)号：US20110167055A1
公开(公告)日：2011-07-07
申请号：US13048031
申请日：2011-03-15
申请人： JEREMY BRANSCOME , MICHAEL CORWIN , LIUXI YANG , JOSEPH I. CHAMDANI
发明人： JEREMY BRANSCOME , MICHAEL CORWIN , LIUXI YANG , JOSEPH I. CHAMDANI
IPC分类号： G06F17/30
CPC分类号： G06F17/30442
摘要： Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system. For example, table and column descriptors are embedded in the machine code database instructions. For ease of installation, the hardware accelerators employ a standard interconnect, such as a PCle or HT interconnect. The processing elements implement a novel dataflow design and Inter Macro-Op Communication (IMC) data structures to execute the machine code database instructions. The hardware accelerator may also comprise a relatively large memory to enhance the hardware execution of the query/operation tasks requested. The hardware accelerator utilizes hardware-friendly memory addressing, which allows for arithmetic derivation of a physical address from a global database virtual address simply based on a row identifier. The hardware accelerator minimizes memory reads/writes by keeping most intermediate results flowing through IMCs in pipelined and parallel fashion. Furthermore, the hardware accelerator may employ task pipelining and pre-fetch pipelining to enhance its performance.

10. 发明授权

US07966343B2 Accessing data in a column store database based on hardware compatible data structures 有权
标题翻译：基于硬件兼容的数据结构访问列存储数据库中的数据
公开(公告)号：US07966343B2
公开(公告)日：2011-06-21
申请号：US12099131
申请日：2008-04-07
申请人： Liuxi Yang , Kapil Surlaker , Ravi Krishnamurthy , Michael Corwin , Jeremy Branscome , Krishnan Meiyyappan , Joseph I. Chamdani
发明人： Liuxi Yang , Kapil Surlaker , Ravi Krishnamurthy , Michael Corwin , Jeremy Branscome , Krishnan Meiyyappan , Joseph I. Chamdani
IPC分类号： G06F17/30
CPC分类号： G06F17/30315
摘要： Embodiments of the present invention provide one or more hardware-friendly data structures that enable efficient hardware acceleration of database operations. In particular, the present invention employs a column-store format for the database. In the database, column-groups are stored with implicit row ids (RIDs) and a RID-to-primary key column having both column-store and row-store benefits via column hopping and a heap structure for adding new data. Fixed-width column compression allow for easy hardware database processing directly on the compressed data. A global database virtual address space is utilized that allows for arithmetic derivation of any physical address of the data regardless of its location. A word compression dictionary with token compare and sort index is also provided to allow for efficient hardware-based searching of text. A tuple reconstruction process is provided as well that allows hardware to reconstruct a row by stitching together data from multiple column groups.
摘要翻译：本发明的实施例提供了一个或多个能够有效地加速数据库操作的硬件友好的数据结构。特别地，本发明采用数据库的列存储格式。在数据库中，列组通过列跳转和用于添加新数据的堆结构存储隐式行ids（RID）和具有列存储和行存储优势的RID至主键列。固定宽度列压缩允许直接对压缩数据进行硬件数据库处理。使用全局数据库虚拟地址空间，允许对数据的任何物理地址的算术推导，而不管其位置如何。还提供了具有令牌比较和排序索引的单词压缩字典，以允许对文本进行高效的基于硬件的搜索。还提供了一个元组重建过程，允许硬件通过将来自多个列组的数据进行拼接来重建行。

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