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1. 发明申请

US20070042588A1 Single damascene with disposable stencil and method therefore 有权
标题翻译：具有一次性模板的单镶嵌和方法
公开(公告)号：US20070042588A1
公开(公告)日：2007-02-22
申请号：US11204982
申请日：2005-08-16
申请人： Michael Beck , Bee Hong , Armin Tilke , Hermann Wendt
发明人： Michael Beck , Bee Hong , Armin Tilke , Hermann Wendt
IPC分类号： H01L21/44
CPC分类号： H01L21/76885 , Y10S438/926
摘要： In a method of fabricating a semiconductor device, a liner is deposited over a conductive region of a wafer and a stencil layer is deposited over the liner. The stencil layer and the liner are etched to form a stencil pattern for a conductive layer. A second liner is deposited over exposed surfaces of the stencil pattern, and the exposed horizontal surfaces of the second liner are removed by sputtering. A low-k dielectric layer is then deposited over the wafer, and the wafer is planarized down to the stencil pattern by chemical-mechanical polishing. The stencil pattern is removed with a wet etch to form an aperture in the wafer exposing the liner and remaining portions of the second liner. Metal is deposited in the aperture, and the surface of the wafer is replanarized by chemical-mechanical polishing to produce a planar surface for additional metallization layers that may be deposited.
摘要翻译：在制造半导体器件的方法中，衬垫沉积在晶片的导电区域上，并且模板层沉积在衬垫上。蚀刻模板层和衬垫以形成用于导电层的模板图案。第二衬里沉积在模板图案的暴露表面上，并且通过溅射去除第二衬里的暴露的水平表面。然后将低k电介质层沉积在晶片上，并且通过化学机械抛光将晶片平面化到模板图案。用湿蚀刻去除模板图案，以在晶片中形成暴露衬垫和第二衬垫的剩余部分的孔。金属沉积在孔中，晶片的表面通过化学机械抛光进行再生，以产生可沉积的附加金属化层的平面。

2. 发明授权

US07452804B2 Single damascene with disposable stencil and method therefore 有权
标题翻译：具有一次性模板的单镶嵌和方法
公开(公告)号：US07452804B2
公开(公告)日：2008-11-18
申请号：US11204982
申请日：2005-08-16
申请人： Michael Beck , Bee Kim Hong , Armin Tilke , Hermann Wendt
发明人： Michael Beck , Bee Kim Hong , Armin Tilke , Hermann Wendt
IPC分类号： H01L21/00
CPC分类号： H01L21/76885 , Y10S438/926
摘要： In a method of fabricating a semiconductor device, a liner is deposited over a conductive region of a wafer and a stencil layer is deposited over the liner. The stencil layer and the liner are etched to form a stencil pattern for a conductive layer. A second liner is deposited over exposed surfaces of the stencil pattern, and the exposed horizontal surfaces of the second liner are removed by sputtering. A low-k dielectric layer is then deposited over the wafer, and the wafer is planarized down to the stencil pattern by chemical-mechanical polishing. The stencil pattern is removed with a wet etch to form an aperture in the wafer exposing the liner and remaining portions of the second liner. Metal is deposited in the aperture, and the surface of the wafer is replanarized by chemical-mechanical polishing to produce a planar surface for additional metallization layers that may be deposited.
摘要翻译：在制造半导体器件的方法中，衬垫沉积在晶片的导电区域上，并且模板层沉积在衬垫上。蚀刻模板层和衬垫以形成用于导电层的模板图案。第二衬里沉积在模板图案的暴露表面上，并且通过溅射去除第二衬里的暴露的水平表面。然后将低k电介质层沉积在晶片上，并且通过化学机械抛光将晶片平面化到模板图案。用湿蚀刻去除模板图案，以在晶片中形成暴露衬垫和第二衬垫的剩余部分的孔。金属沉积在孔中，晶片的表面通过化学机械抛光进行再生，以产生可沉积的附加金属化层的平面。

3. 发明授权

US07883987B2 Semiconductor devices and methods of manufacture thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07883987B2
公开(公告)日：2011-02-08
申请号：US12762172
申请日：2010-04-16
申请人： Armin Tilke , Frank Huebinger , Hermann Wendt
发明人： Armin Tilke , Frank Huebinger , Hermann Wendt
IPC分类号： H01L21/76 , H01L29/00
CPC分类号： H01L21/76229 , H01L21/76232
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and a trench formed within the workpiece. The trench has an upper portion and a lower portion, the upper portion having a first width and the lower portion having a second width, the second width being greater than the first width. A first material is disposed in the lower portion of the trench at least partially in regions where the second width of the lower portion is greater than the first width of the upper portion. A second material is disposed in the upper portion of the trench and at least in the lower portion of the trench beneath the upper portion.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，半导体器件包括工件和形成在工件内的沟槽。沟槽具有上部和下部，上部具有第一宽度，下部具有第二宽度，第二宽度大于第一宽度。第一材料至少部分地在下部的第二宽度大于上部的第一宽度的区域中设置在沟槽的下部。第二材料设置在沟槽的上部，并且至少在上部下方的沟槽的下部。

4. 发明授权

US07619310B2 Semiconductor interconnect and method of making same 有权
标题翻译：半导体互连及其制作方法
公开(公告)号：US07619310B2
公开(公告)日：2009-11-17
申请号：US11592427
申请日：2006-11-03
申请人： Frank Huebinger , Moosung Chae , Armin Tilke , Hermann Wendt
发明人： Frank Huebinger , Moosung Chae , Armin Tilke , Hermann Wendt
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76834 , H01L21/76835 , H01L21/7684 , H01L21/76849 , H01L23/5222 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit interconnect structure includes a conductive line, a first barrier layer disposed on a bottom surface of conductive line, a second barrier layer disposed on the top surface of the conductive line, and an interlevel dielectric surrounding the conductive line.
摘要翻译：集成电路互连结构包括导线，布置在导线底面上的第一阻挡层，设置在导线上表面的第二阻挡层和围绕导线的层间电介质。

5. 发明授权

US07723818B2 Semiconductor devices and methods of manufacture thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07723818B2
公开(公告)日：2010-05-25
申请号：US11805232
申请日：2007-05-22
申请人： Armin Tilke , Frank Huebinger , Hermann Wendt
发明人： Armin Tilke , Frank Huebinger , Hermann Wendt
IPC分类号： H01L29/00 , H01L21/76
CPC分类号： H01L21/76229 , H01L21/76232
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and a trench formed within the workpiece. The trench has an upper portion and a lower portion, the upper portion having a first width and the lower portion having a second width, the second width being greater than the first width. A first material is disposed in the lower portion of the trench at least partially in regions where the second width of the lower portion is greater than the first width of the upper portion. A second material is disposed in the upper portion of the trench and at least in the lower portion of the trench beneath the upper portion.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，半导体器件包括工件和形成在工件内的沟槽。沟槽具有上部和下部，上部具有第一宽度，下部具有第二宽度，第二宽度大于第一宽度。第一材料至少部分地在下部的第二宽度大于上部的第一宽度的区域中设置在沟槽的下部。第二材料设置在沟槽的上部，并且至少在上部下方的沟槽的下部。

6. 发明申请

US20080290448A1 Semiconductor devices and methods of manufacture thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080290448A1
公开(公告)日：2008-11-27
申请号：US11805232
申请日：2007-05-22
申请人： Armin Tilke , Frank Huebinger , Hermann Wendt
发明人： Armin Tilke , Frank Huebinger , Hermann Wendt
IPC分类号： H01L21/762
CPC分类号： H01L21/76229 , H01L21/76232
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and a trench formed within the workpiece. The trench has an upper portion and a lower portion, the upper portion having a first width and the lower portion having a second width, the second width being greater than the first width. A first material is disposed in the lower portion of the trench at least partially in regions where the second width of the lower portion is greater than the first width of the upper portion. A second material is disposed in the upper portion of the trench and at least in the lower portion of the trench beneath the upper portion.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，半导体器件包括工件和形成在工件内的沟槽。沟槽具有上部和下部，上部具有第一宽度，下部具有第二宽度，第二宽度大于第一宽度。第一材料至少部分地在下部的第二宽度大于上部的第一宽度的区域中设置在沟槽的下部。第二材料设置在沟槽的上部，并且至少在上部下方的沟槽的下部。

7. 发明申请

US20100197112A1 Semiconductor Devices and Methods of Manufacture Thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100197112A1
公开(公告)日：2010-08-05
申请号：US12762172
申请日：2010-04-16
申请人： Armin Tilke , Frank Huebinger , Hermann Wendt
发明人： Armin Tilke , Frank Huebinger , Hermann Wendt
IPC分类号： H01L21/762
CPC分类号： H01L21/76229 , H01L21/76232
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and a trench formed within the workpiece. The trench has an upper portion and a lower portion, the upper portion having a first width and the lower portion having a second width, the second width being greater than the first width. A first material is disposed in the lower portion of the trench at least partially in regions where the second width of the lower portion is greater than the first width of the upper portion. A second material is disposed in the upper portion of the trench and at least in the lower portion of the trench beneath the upper portion.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，半导体器件包括工件和形成在工件内的沟槽。沟槽具有上部和下部，上部具有第一宽度，下部具有第二宽度，第二宽度大于第一宽度。第一材料至少部分地在下部的第二宽度大于上部的第一宽度的区域中设置在沟槽的下部。第二材料设置在沟槽的上部，并且至少在上部下方的沟槽的下部。

8. 发明申请

US20080108219A1 Semiconductor interconnect and method of making same 有权
标题翻译：半导体互连及其制作方法
公开(公告)号：US20080108219A1
公开(公告)日：2008-05-08
申请号：US11592427
申请日：2006-11-03
申请人： Frank Huebinger , Moosung Chae , Armin Tilke , Hermann Wendt
发明人： Frank Huebinger , Moosung Chae , Armin Tilke , Hermann Wendt
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76834 , H01L21/76835 , H01L21/7684 , H01L21/76849 , H01L23/5222 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit interconnect structure includes a conductive line, a first barrier layer disposed on a bottom surface of conductive line, a second barrier layer disposed on the top surface of the conductive line, and an interlevel dielectric surrounding the conductive line.
摘要翻译：集成电路互连结构包括导线，布置在导线底面上的第一阻挡层，设置在导线上表面的第二阻挡层和围绕导线的层间电介质。

9. 发明申请

US20070059897A1 Isolation for semiconductor devices 审中-公开
标题翻译：半导体器件隔离
公开(公告)号：US20070059897A1
公开(公告)日：2007-03-15
申请号：US11223232
申请日：2005-09-09
申请人： Armin Tilke , Bee Hong
发明人： Armin Tilke , Bee Hong
IPC分类号： H01L21/76
CPC分类号： H01L21/76229 , H01L21/3065 , H01L21/3086
摘要： Methods of forming and structures for isolation structures for semiconductor devices are disclosed. The isolation structures are wider at the bottom than at the top, providing the ability to further scale the size of semiconductor devices. A first etch process is used to form a first trench portion, and a second etch process or an oxidation process is used to form a second trench portion beneath the first trench portion. The second trench portion is wider than the first trench portion. A liner may form during the first trench portion on the sidewalls of the first trench portion that protects the first trench portion sidewalls during the second etch process, in one embodiment. Alternatively, a liner may be deposited on the sidewalls of the first trench portion, in another embodiment.
摘要翻译：公开了用于半导体器件的隔离结构的形成方法和结构。隔离结构在底部比在顶部更宽，提供了进一步缩小半导体器件尺寸的能力。第一蚀刻工艺用于形成第一沟槽部分，并且第二蚀刻工艺或氧化工艺用于在第一沟槽部分下方形成第二沟槽部分。第二沟槽部分比第一沟槽部分宽。在一个实施例中，衬垫可以在第一沟槽部分的侧壁处的第一沟槽部分期间形成，其在第二蚀刻工艺期间保护第一沟槽部分侧壁。或者，在另一个实施例中，衬垫可以沉积在第一沟槽部分的侧壁上。

10. 发明申请

US20070205489A1 Methods of fabricating isolation regions of semiconductor devices and structures thereof 有权
标题翻译：制造半导体器件的隔离区域的方法及其结构
公开(公告)号：US20070205489A1
公开(公告)日：2007-09-06
申请号：US11365226
申请日：2006-03-01
申请人： Armin Tilke , Marcus Culmsee , Chris Stapelmann , Bee Hong , Roland Hampp
发明人： Armin Tilke , Marcus Culmsee , Chris Stapelmann , Bee Hong , Roland Hampp
IPC分类号： H01L29/06
CPC分类号： H01L29/0649 , H01L21/02271 , H01L21/76229 , H01L21/76232
摘要： Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and at least one trench formed in the workpiece. The at least one trench includes sidewalls, a bottom surface, a lower portion, and an upper portion. A first liner is disposed over the sidewalls and the bottom surface of the at least one trench. A second liner is disposed over the first liner in the lower portion of the at least one trench. A first insulating material is disposed over the second liner in the lower portion of the at least one trench. A second insulating material is disposed over the first insulating material in the upper portion of the at least one trench. The first liner, the second liner, the first insulating material, and the second insulating material comprise an isolation region of the semiconductor device.
摘要翻译：公开了制造半导体器件的隔离区域的方法及其结构。在优选实施例中，半导体器件包括工件和形成在工件中的至少一个沟槽。所述至少一个沟槽包括侧壁，底面，下部和上部。第一衬垫设置在所述至少一个沟槽的侧壁和底表面上。第二衬垫设置在至少一个沟槽的下部中的第一衬垫之上。第一绝缘材料设置在至少一个沟槽的下部中的第二衬垫上。第二绝缘材料设置在至少一个沟槽的上部中的第一绝缘材料之上。第一衬垫，第二衬垫，第一绝缘材料和第二绝缘材料包括半导体器件的隔离区域。

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