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1. 发明授权

US5282170A Negative power supply 失效
标题翻译：负电源
公开(公告)号：US5282170A
公开(公告)日：1994-01-25
申请号：US964807
申请日：1992-10-22
申请人： Michael A. Van Buskirk , Johnny C. Chen , Chung K. Chang , Lee E. Cleveland , Antonio Montalvo
发明人： Michael A. Van Buskirk , Johnny C. Chen , Chung K. Chang , Lee E. Cleveland , Antonio Montalvo
IPC分类号： G11C17/00 , G11C5/14 , G11C16/06 , H02M3/07 , H03K19/096 , G11C13/00
CPC分类号： H02M3/073 , G11C5/145 , G11C5/147
摘要： A negative power supply for generating and supplying a regulated negative potential to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure includes charge pumping means (12) formed of a plurality of charge pump stages (401-404) for generating a high negative voltage, and cancellation means coupled to each stage of the charge pump means for effectively canceling out threshold voltage drops in the charge pump means. A regulator means (16) responsive to the high negative voltage and a reference potential is provided for generating the regulated negative potential so that it is independent of an external supply potential (VCC).
摘要翻译：用于在闪速擦除期间通过闪存EEPROM存储单元阵列中的字线产生和提供调节的负电位以控制所选存储单元的栅极的负电源包括由多个电荷泵级（401- 404），以及耦合到电荷泵装置的每个级的消除装置，用于有效地消除电荷泵装置中的阈值电压降。提供响应于高负电压的调节器装置（16），并且提供用于产生调节负电位的参考电位，使得其独立于外部电源电位（VCC）。

2. 发明授权

US5291446A VPP power supply having a regulator circuit for controlling a regulated positive potential 失效
标题翻译： VPP电源具有用于控制调节的正电位的调节器电路
公开(公告)号：US5291446A
公开(公告)日：1994-03-01
申请号：US964684
申请日：1992-10-22
申请人： Michael A. Van Buskirk , Johnny C. Chen , Chung K. Chang , Lee E. Cleveland , Antonio Montalvo
发明人： Michael A. Van Buskirk , Johnny C. Chen , Chung K. Chang , Lee E. Cleveland , Antonio Montalvo
IPC分类号： G11C17/00 , G05F3/24 , G11C16/06 , G11C16/12 , G11C16/30 , H02M3/07 , H03K17/06 , H03K17/14 , H03K19/096 , H03L1/00
CPC分类号： G11C16/30 , G05F3/247 , G11C16/12 , H03K17/063 , H03K17/145
摘要： A positive power supply for generating and supplying a regulated positive potential to control gates of selected memory cells via word lines in an array of flash EEPROM memory cells during programming includes a clock circuit (18b) for generating a pair of non-overlapping clock signals and charge pump means (18c) responsive to an external power supply potential (VCC) and to the non-overlapping clock signals for generating a high positive voltage. A regulator circuit (20) responsive to the high positive voltage and a reference voltage is provided for controlling the regulated positive potential so that it is independent of the external power supply potential (VCC).
摘要翻译：用于在编程期间通过闪存EEPROM存储单元阵列中的字线产生和提供调节的正电位以控制所选存储单元的栅极的正电源包括用于产生一对非重叠时钟信号的时钟电路（18b）响应于外部电源电位（VCC）的电荷泵装置（18c）和用于产生高正电压的非重叠时钟信号。提供响应于高正电压和参考电压的调节器电路（20），用于控制调节的正电位，使其独立于外部电源电位（VCC）。

3. 发明授权

US5263000A Drain power supply 失效
标题翻译：排水电源
公开(公告)号：US5263000A
公开(公告)日：1993-11-16
申请号：US964697
申请日：1992-10-22
申请人： Michael A. Van Buskirk , Johnny C. Chen , Chung K. Chang , Lee E. Cleveland , Antonio Montalvo
发明人： Michael A. Van Buskirk , Johnny C. Chen , Chung K. Chang , Lee E. Cleveland , Antonio Montalvo
IPC分类号： G11C17/00 , G11C16/06 , G11C16/30 , H02M3/07 , H03K19/096 , G11C13/00
CPC分类号： G11C16/30
摘要： A drain power supply for generating and supplying a regulated positive potential to drain regions of selected memory cells via bit lines in an array of flash EEPROM memory cells during programming includes charge pump means (20) formed of a plurality of charge pump sections (20a-20h) driven by one of a plurality of staggered clock signals for generating a moderately high level positive voltage. Cancellation means (26, 28) are coupled to each of the plurality of charge pump sections for effectively canceling out threshold voltage drops in the charge pump circuit. A regulator circuit (22) responsive to the regulated positive potential at an output node and a reference voltage is provided for generating a control voltage so as to control the high level positive voltage on the output node.

4. 发明授权

US5376835A Power-on reset circuit 失效
标题翻译：上电复位电路
公开(公告)号：US5376835A
公开(公告)日：1994-12-27
申请号：US964806
申请日：1992-10-22
申请人： Michael A. Van Buskirk , Johnny C.-L. Chen , Chung K. Chang , Lee E. Cleveland , Antonio Montalvo
发明人： Michael A. Van Buskirk , Johnny C.-L. Chen , Chung K. Chang , Lee E. Cleveland , Antonio Montalvo
IPC分类号： H03K17/22 , H03K5/153 , H03K17/687
CPC分类号： H03K17/223
摘要： A power-on reset circuit for generating and maintaining a reset signal in an active low state during power-up until a power supply voltage exceeds a predetermined level includes a resetting circuit (12a) and a control logic circuit (12b). The reset circuit is responsive to a monitoring signal, a start-up signal and a reference voltage for generating a reset signal which is initially in the active low state. The reset circuit includes a differential comparator (54) having a first input for receiving the start-up signal, a second input for receiving the reference voltage, and an output for generating the reset signal. The control logic circuit is responsive to the monitoring signal and the reset signal for generating a logic control signal which is initially in a high state. The differential comparator is responsive to the control signal and is activated only after the power supply voltage has exceeded a predetermined level so as to maintain initially the reset signal on its output in the low state. The output of the differential comparator is forced to a high state after the monitoring signal has reached a low state and the start-up signal exceeds the reference voltage. Logic and/or memory circuitry (18) is provided which responds to the reset signal so as to force its outputs to a known logic state.
摘要翻译：一种用于在上电期间产生并维持处于低电平状态的复位信号，直到电源电压超过预定电平的上电复位电路包括复位电路（12a）和控制逻辑电路（12b）。复位电路响应于监视信号，启动信号和用于产生初始处于低电平状态的复位信号的参考电压。复位电路包括差分比较器（54），其具有用于接收启动信号的第一输入端，用于接收基准电压的第二输入端和用于产生复位信号的输出端。控制逻辑电路响应于监视信号和复位信号，用于产生最初处于高状态的逻辑控制信号。差分比较器响应于控制信号，并且仅在电源电压已经超过预定电平后被激活，以便将其输出上的复位信号初始化为低状态。在监视信号达到低电平并且启动信号超过参考电压之后，差分比较器的输出被强制为高电平。提供逻辑和/或存储器电路（18），其响应于复位信号，以便将其输出强制到已知的逻辑状态。

5. 发明授权

US5349558A Sector-based redundancy architecture 失效
标题翻译：基于扇区的冗余架构
公开(公告)号：US5349558A
公开(公告)日：1994-09-20
申请号：US112033
申请日：1993-08-26
申请人： Lee E. Cleveland , Michael A. Van Buskirk , Johnny C. Chen , Chung K. Chang
发明人： Lee E. Cleveland , Michael A. Van Buskirk , Johnny C. Chen , Chung K. Chang
IPC分类号： G11C17/00 , G11C16/06 , G11C29/00 , G11C29/04 , H01L21/8247 , H01L27/115 , G11C7/00
CPC分类号： G11C29/808
摘要： An improved redundancy architecture is provided for an array of flash EEPROM cells which permit repair of defective columns of memory cells in the array with redundant columns of memory cells on a sector-by-sector basis. The redundancy circuitry includes a plurality of sector-based redundancy blocks (2-8) each having redundant columns of memory cells extending through the plurality of sectors. Sector selection transistors (Q1,Q2) are provided for dividing the redundant columns into different segments, each residing in at least one of the plurality of sectors and for isolating the different segments so as to allow independent use from other segments in the same redundant column in repairing defective columns in the corresponding ones of the plurality of sectors. Addressable storage circuitry (314a,314b) is used for storing sector-based redundancy column addresses, each defining a column address containing the defective column of memory cells in the plurality of sectors in association with one of the different redundant column segments to be used in repairing the defective column.
摘要翻译：提供了一种用于快闪EEPROM单元阵列的改进的冗余架构，其允许以扇区为基础以冗余列的存储器单元来修复阵列中的存储器单元的有缺陷的列。冗余电路包括多个基于扇区的冗余块（2-8），每个冗余块具有延伸穿过多个扇区的多个存储单元冗余列。扇区选择晶体管（Q1，Q2）被提供用于将冗余列分成不同的段，每个段驻留在多个扇区中的至少一个扇区中，并且用于隔离不同的段，以允许独立使用同一冗余列中的其他段在修复多个扇区中相应的扇区中的有缺陷的列。可寻址存储电路（314a，314b）用于存储基于扇区的冗余列地址，每个定义包含多个扇区中的存储单元的缺陷列的列地址，与不同冗余列段之一相关联地使用修理有缺陷的列。

6. 发明授权

US5406517A Distributed negative gate power supply 失效
标题翻译：分布式负栅极电源
公开(公告)号：US5406517A
公开(公告)日：1995-04-11
申请号：US109881
申请日：1993-08-23
申请人： Chung K. Chang , Johnny C. Chen , Michael A. Van Buskirk , Lee E. Cleveland
发明人： Chung K. Chang , Johnny C. Chen , Michael A. Van Buskirk , Lee E. Cleveland
IPC分类号： G11C17/00 , G11C16/06 , G11C16/30 , G11C13/00
CPC分类号： G11C16/30
摘要： A distributed negative gate power supply for generating and selectively supplying a relatively high negative voltage to control gates of memory cells in selected half-sectors via wordlines in an array of flash EEPROM memory cells during flash erasure. The distributed negative gate power supply includes a main charge pumping circuit (20a, 20b), a plurality of distribution sector pumping means (18a-18p). Each of the plurality of distribution sector pumping circuits is responsive to a half-sector select signal for selectively connecting the primary negative voltage to the wordlines of the selected half-sectors.
摘要翻译：一种分布式负栅极电源，用于在闪速擦除期间，通过闪存EEPROM存储单元阵列中的字线产生并选择性地向所选择的半扇区中的存储单元的控制栅极提供相对较高的负电压。分布式负栅极电源包括主电荷泵浦电路（20a，20b），多个分配扇区泵送装置（18a-18p）。多个分配扇区泵浦电路中的每一个响应于半扇区选择信号，用于选择性地将初级负电压连接到所选择的半扇区的字线。

7. 发明授权

US5359558A Flash eeprom array with improved high endurance 失效
标题翻译：闪光eeprom阵列具有改善的高耐力
公开(公告)号：US5359558A
公开(公告)日：1994-10-25
申请号：US109886
申请日：1993-08-23
申请人： Chung K. Chang , Johnny C. Chen , Michael A. Van Buskirk , Lee E. Cleveland
发明人： Chung K. Chang , Johnny C. Chen , Michael A. Van Buskirk , Lee E. Cleveland
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/28 , G11C16/34 , H01L27/10 , G11C11/40
CPC分类号： G11C16/3409 , G11C16/10 , G11C16/28 , G11C16/3404
摘要： An improved over-erased bit correction structure is provided for performing a correction operation on over-erased memory cells in an array of flash EEPROM memory cells after erase operation so as to render high endurance. Sensing circuitry (20) is used to detect column leakage current indicative of an over-erased bit during an APDE mode of operation and for generating a logic signal representative of data stored in the memory cell. A data input buffer circuit (26) is used to compare the logic signal and a data signal representative of data programmed in the memory cell so as to generate a bit match signal. A pulse counter (30) is coupled to the data input buffer circuit for counting a plurality of programming pulses applied thereto. The data input buffer circuit selectively connects only certain ones of the columns of bit lines to the pulse counter in which the bit match signal is at a high logic level so as to program back over-erased memory cells connected to only the certain ones of the columns of bit lines.
摘要翻译：提供了一种改进的过擦除位校正结构，用于对擦除操作之后的快闪EEPROM存储单元阵列中的擦除过的存储器单元执行校正操作，以使其具有高耐久性。感测电路（20）用于在APDE操作模式期间检测指示过擦除位的列泄漏电流，并用于产生表示存储在存储单元中的数据的逻辑信号。数据输入缓冲电路（26）用于比较逻辑信号和表示在存储器单元中编程的数据的数据信号，以产生位匹配信号。脉冲计数器（30）耦合到数据输入缓冲器电路，用于对施加到其上的多个编程脉冲进行计数。数据输入缓冲器电路仅选择性地将位线列中的某些列连接到脉冲计数器，其中比特匹配信号处于高逻辑电平，以便编程回只连接到仅某些位列列。

8. 发明授权

US5365484A Independent array grounds for flash EEPROM array with paged erase architechture 失效
标题翻译：具有分页擦除架构的闪存EEPROM阵列的独立阵列接地
公开(公告)号：US5365484A
公开(公告)日：1994-11-15
申请号：US109887
申请日：1993-08-23
申请人： Lee E. Cleveland , Michael A. Van Buskirk , Johhny C. Chen , Chung K. Chang
发明人： Lee E. Cleveland , Michael A. Van Buskirk , Johhny C. Chen , Chung K. Chang
IPC分类号： G11C17/00 , G11C16/06 , G11C16/16 , G11C16/30 , G11C13/00
CPC分类号： G11C16/16 , G11C16/30
摘要： An improved architecture for an array of flash EEPROM cells with paged erase is provided. The array is formed of a plurality of half-sectors. In each sector, the sources of the memory cell transistors are connected to a separate individual ground line. A ground line circuit is provided for generating a half-sector ground line signal. The separate individual ground line is connected to the ground line circuit for receiving the half-sector ground line signal which is at a predetermined positive potential during erase.
摘要翻译：提供了一种用于具有分页擦除的快闪EEPROM单元阵列的改进的架构。阵列由多个半扇区形成。在每个扇区中，存储单元晶体管的源极连接到单独的单独接地线。提供用于产生半扇区接地线信号的接地线电路。单独的单独地线连接到接地线电路，用于接收在擦除期间处于预定正电位的半扇区接地线信号。

9. 发明授权

US5973979A Low supply voltage negative charge pump 失效
标题翻译：低电源负电荷泵
公开(公告)号：US5973979A
公开(公告)日：1999-10-26
申请号：US774307
申请日：1996-12-26
申请人： Chung K. Chang , Johnny C. Chen , Lee E. Cleveland
发明人： Chung K. Chang , Johnny C. Chen , Lee E. Cleveland
IPC分类号： G11C5/14 , G11C16/30 , H02M3/07 , G11C13/00
CPC分类号： G11C16/30 , G11C5/145 , H02M3/073 , H02M2003/071 , H02M2003/075
摘要： A low supply voltage negative charge pump for generating a relatively high negative voltage to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure includes charge pump means (210) formed of a plurality of charge pump stages (201-206) and coupling capacitor means (C201-C212) for delivering clock signals to the plurality of charge pump stages. Each of the plurality of charge pump stages is formed of an N-channel intrinsic pass transistor (N1-N6), an N-channel intrinsic initialization transistor (MD1-MD6), and an N-channel intrinsic precharge transistor (MX3-MX7, MX1) which are disposed in separate p-wells so as to reduce body effect. As a result, the negative charge pump is operable using a supply voltage of +3 volts or lower.
摘要翻译：用于在闪速擦除期间通过闪存EEPROM存储器单元阵列中的字线产生相对高的负电压以控制所选择的存储器单元的栅极的低电源负电荷泵包括由多个电荷泵级形成的电荷泵装置（210） 201-206）和用于将时钟信号传送到多个电荷泵级的耦合电容器装置（C201-C212）。多个电荷泵级中的每一个由N沟道本征通过晶体管（N1-N6），N沟道本征初始化晶体管（MD1-MD6）和N沟道本征预充电晶体管（MX3-MX7， MX1），其设置在单独的p阱中，以减少身体效应。结果，负电荷泵可以使用+ 3伏或更低的电源电压工作。

10. 发明授权

US5612921A Low supply voltage negative charge pump 失效
标题翻译：低电源负电荷泵
公开(公告)号：US5612921A
公开(公告)日：1997-03-18
申请号：US559705
申请日：1996-02-15
申请人： Chung K. Chang , Johnny C. Chen , Lee E. Cleveland
发明人： Chung K. Chang , Johnny C. Chen , Lee E. Cleveland
IPC分类号： G11C5/14 , G11C16/30 , H02M3/07 , G11C13/00
CPC分类号： G11C16/30 , G11C5/145 , H02M3/073 , H02M2003/071 , H02M2003/075
摘要： A low supply voltage negative charge pump for generating a relatively high negative voltage to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure includes charge pump means (210) formed of a plurality of charge pump stages (201-206) and coupling capacitor means (C201-C212) for delivering clock signals to the plurality of charge pump stages. Each of the plurality of charge pump stages is formed of an N-channel intrinsic pass transistor (N1-N6), an N-channel intrinsic initialization transistor (MD1-MD6), and an N-channel intrinsic precharge transistor (MX3-MX7, MX1) which are disposed in separate p-wells so as to reduce body effect. As a result, the negative charge pump is operable using a supply voltage of +3 volts or lower.
摘要翻译：用于在闪速擦除期间通过闪存EEPROM存储器单元阵列中的字线产生相对高的负电压以控制所选择的存储器单元的栅极的低电源负电荷泵包括由多个电荷泵级形成的电荷泵装置（210） 201-206）和用于将时钟信号传送到多个电荷泵级的耦合电容器装置（C201-C212）。多个电荷泵级中的每一个由N沟道本征通过晶体管（N1-N6），N沟道本征初始化晶体管（MD1-MD6）和N沟道本征预充电晶体管（MX3-MX7， MX1），其设置在单独的p阱中，以减少身体效应。结果，负电荷泵可以使用+ 3伏或更低的电源电压工作。

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