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1. 发明授权

US5185875A Method and apparatus for reducing memory read latency in a shared memory system with multiple processors 失效
标题翻译：用于在具有多个处理器的共享存储器系统中减少存储器读取延迟的方法和装置
公开(公告)号：US5185875A
公开(公告)日：1993-02-09
申请号：US302839
申请日：1989-01-27
申请人： Kumar Chinnaswamy , Michael A. Gagliardo , John J. Lynch , James E. Tessari
发明人： Kumar Chinnaswamy , Michael A. Gagliardo , John J. Lynch , James E. Tessari
IPC分类号： G06F12/08 , G06F15/16
CPC分类号： G06F12/0817
摘要： Methods and apparatus for reducing memory read latency for selected data requested by one central processing unit (CPU) and retrieved from another CPU through a system control unit (SCU) with special data transfer cycles. The special data transfer cycles include a first dual operation mode which confirms that the transferred data is the most current and then concurrently writes the CPU transferred data into the SCU main memory while transferring it directly to the requesting CPU, and a second dual operation mode which confirms that only a portion of the transferred data is the most current and then concurrently writes the portion of the transferred data that is most current in the SCU memory and reads the written data that is most current in the SCU memory and reads the written data for transfer to the requesting CPU.

2. 发明授权

US5008886A Read-modify-write operation 失效
标题翻译：读 - 修改 - 写操作
公开(公告)号：US5008886A
公开(公告)日：1991-04-16
申请号：US303621
申请日：1989-01-27
申请人： Kumar Chinnaswamy , Michael A. Gagliardo , Paul M. Goodwin , John J. Lynch , James E. Tessari
发明人： Kumar Chinnaswamy , Michael A. Gagliardo , Paul M. Goodwin , John J. Lynch , James E. Tessari
IPC分类号： G06F12/16 , G06F7/24 , G06F11/10
CPC分类号： G06F11/1056
摘要： A method and apparatus for a read-modify-write operation in a digital computer memory system which reduces memory data path buffer storage requirements with a procedure which includes latching new write data and associated mask fields into a data output buffer and then merging read data with the new data in the output buffer according to the latched mask fields.

3. 发明授权

US5255381A Mode switching for a memory system with diagnostic scan 失效
标题翻译：具有诊断扫描功能的存储系统的模式切换
公开(公告)号：US5255381A
公开(公告)日：1993-10-19
申请号：US582476
申请日：1990-09-14
申请人： Kumar Chinnaswamy , Hansel A. Collins , Michael B. Evans , Timothy P. Fissette , Michael A. Gagliardo , John J. Lynch , James E. Tessari
发明人： Kumar Chinnaswamy , Hansel A. Collins , Michael B. Evans , Timothy P. Fissette , Michael A. Gagliardo , John J. Lynch , James E. Tessari
IPC分类号： G06F11/22 , G01R31/317 , G06F11/273 , G06F12/16 , G11C11/4076 , G06F12/00 , G11C7/00
CPC分类号： G11C11/4076 , G01R31/31701 , G06F11/2736
摘要： Methods and apparatus for immunizing dynamic random access memory (DRAM) modules in the data processing system against data loss from transitions that occur with memory mode switching during the scan operation and permitting normal operations to be performed on the memory modules regardless of the state of the system clocks.

4. 发明授权

US5371874A Write-read/write-pass memory subsystem cycle 失效
标题翻译：写/读 - 写存储器子系统循环
公开(公告)号：US5371874A
公开(公告)日：1994-12-06
申请号：US105101
申请日：1993-08-09
申请人： Kumar Chinnaswamy , Michael A. Gagliardo , John J. Lynch , James E. Tessari
发明人： Kumar Chinnaswamy , Michael A. Gagliardo , John J. Lynch , James E. Tessari
IPC分类号： G06F12/08 , G06F15/16
CPC分类号： G06F12/0817
摘要： Methods and apparatus for reducing memory read latency for selected data requested by one central processing unit (CPU) and retrieved from another CPU through a system control unit (SCU) with special data transfer cycles. The special data transfer cycles include a first dual operation mode which confirms that the transferred data is the most current and then concurrently write the CPU transferred data into the SCU main memory while transferring it directly to the requesting CPU, and a second dual operation mode which confirms that only a portion of the transferred data is the most current and then concurrently write the portion of the transferred data that is most current in the SCU memory and read the written data for transfer to the requesting CPU.
摘要翻译：用于减少由一个中央处理单元（CPU）请求的选定数据的内存读取延迟并通过具有特殊数据传输周期的系统控制单元（SCU）从另一个CPU检索的存储器读取等待时间的方法和装置。特殊数据传输周期包括第一双重操作模式，其确认传送的数据是最新的，然后在将CPU传送的数据直接传送到请求的CPU的同时将CPU传送的数据同时写入SCU主存储器中，并且将第二双重操作模式确认只有一部分传输的数据是最新的，然后同时写入SCU存储器中最新的传送数据的部分，并读取写入的数据以传送到请求CPU。

5. 发明授权

US5408641A Programmable data transfer timing 失效
标题翻译：可编程数据传输时序
公开(公告)号：US5408641A
公开(公告)日：1995-04-18
申请号：US221663
申请日：1994-04-01
申请人： Michael A. Gagliardo , John J. Lynch , James E. Tessari
发明人： Michael A. Gagliardo , John J. Lynch , James E. Tessari
IPC分类号： G06F12/00 , G06F1/04 , G06F1/08 , G06F1/12 , G06F13/16 , G06F13/42 , G06F13/00
CPC分类号： G06F13/4243 , G06F1/04
摘要： A method and apparatus for providing asynchronous communication between at least one central processing unit (CPU) and at least one associated memory unit with specially programmed timing signals to latch, select and transmit data between them.
摘要翻译：一种用于在至少一个中央处理单元（CPU）和至少一个相关联的存储器单元之间提供异步通信的方法和装置，其具有专门编程的定时信号，以在它们之间锁存，选择和传输数据。

6. 发明授权

US5335337A Programmable data transfer timing 失效
标题翻译：可编程数据传输时序
公开(公告)号：US5335337A
公开(公告)日：1994-08-02
申请号：US303624
申请日：1989-01-27
申请人： Michael A. Gagliardo , John J. Lynch , James E. Tessari
发明人： Michael A. Gagliardo , John J. Lynch , James E. Tessari
IPC分类号： G06F12/00 , G06F1/04 , G06F1/08 , G06F1/12 , G06F13/16 , G06F13/42 , G06F13/00
CPC分类号： G06F13/4243 , G06F1/04
摘要： A method and apparatus for providing asynchronous communication between at least one central processing unit (CPU) and at least one associated memory unit with specially programmed timing signals to latch, select and transmit data between them.
摘要翻译：一种用于在至少一个中央处理单元（CPU）和至少一个相关联的存储器单元之间提供异步通信的方法和装置，其具有专门编程的定时信号，以在它们之间锁存，选择和传输数据。

7. 发明授权

US5313623A Method and apparatus for performing diagnosis scanning of a memory unit regardless of the state of the system clock and without affecting the store data 失效
标题翻译：无论系统时钟的状态如何而不影响存储数据，执行存储器单元的诊断扫描的方法和装置
公开(公告)号：US5313623A
公开(公告)日：1994-05-17
申请号：US547656
申请日：1990-07-03
申请人： Kumar Chinnaswamy , Hansel A. Collins , Michael B. Evans , Timothy P. Fissette , Michael A. Gagliardo , John J. Lynch , James E. Tessari
发明人： Kumar Chinnaswamy , Hansel A. Collins , Michael B. Evans , Timothy P. Fissette , Michael A. Gagliardo , John J. Lynch , James E. Tessari
IPC分类号： G01R31/317 , G06F11/273 , G11C11/4076 , G06F11/22
CPC分类号： G01R31/31701 , G11C11/4076 , G06F11/2736
摘要： Methods and apparatus for immunizing dynamic random access memory (DRAM) modules in the data processing system against data loss from transitions that occur with memory mode switching during the scan operation and permitting normal operations to be performed on the memory modules regardless of the state of the system clocks.
摘要翻译：用于免疫数据处理系统中的动态随机存取存储器（DRAM）模块的方法和装置，以防止在扫描操作期间随着存储器模式切换而发生的转换的数据丢失，并允许对存储器模块执行正常操作，而不管系统时钟。

8. 发明授权

US5235693A Method and apparatus for reducing buffer storage in a read-modify-write operation 失效
标题翻译：用于在读 - 修改 - 写操作中减少缓冲存储的方法和装置
公开(公告)号：US5235693A
公开(公告)日：1993-08-10
申请号：US582475
申请日：1990-09-14
申请人： Kumar Chinnaswamy , Michael A. Gagliardo , Paul M. Goodwin , John J. Lynch , James E. Tessari
发明人： Kumar Chinnaswamy , Michael A. Gagliardo , Paul M. Goodwin , John J. Lynch , James E. Tessari
IPC分类号： G06F12/16 , G06F11/10
CPC分类号： G06F11/1056
摘要： A method and apparatus for a read-modify-write operation in a digital computer memory system that reduces memory data path buffer storage requirements. The method latches new write data and associated mask fields into a data output buffer and then uses the latched mask fields to merge read data with the new data in the output buffer. The mask fields determine which portion of the read data is to be replaced with new data. Appropriate check bits for an error correction code (ECC) are generated and added to the modified data in the output buffer to produce a new data output which is released from the output buffer into the memory at the selected address.
摘要翻译：一种用于在数字计算机存储器系统中进行读 - 修改 - 写入操作的方法和装置，其减少了存储器数据路径缓冲器存储要求。该方法将新的写入数据和相关的掩码字段锁存到数据输出缓冲区中，然后使用锁存的掩码字段将读取的数据与输出缓冲区中的新数据进行合并。掩码字段确定要用新数据替换读取数据的哪一部分。生成用于纠错码（ECC）的适当的校验位并将其添加到输出缓冲器中的修改数据，以产生从输出缓冲器释放到选定地址的存储器中的新数据输出。

9. 发明授权

US07490471B2 Swirler assembly 有权
标题翻译：旋流器总成
公开(公告)号：US07490471B2
公开(公告)日：2009-02-17
申请号：US11164861
申请日：2005-12-08
申请人： John J. Lynch , Kevin McMahan , Mark Pinson
发明人： John J. Lynch , Kevin McMahan , Mark Pinson
IPC分类号： F02C1/00
CPC分类号： F23R3/14 , F23C7/004 , F23C2900/07001 , F23D11/383 , F23D2900/14021 , F23R3/286
摘要： A swirler assembly. The swirler assembly may include a hub, a vane positioned on the hub, and a fuel supply passageway extending from the hub through the vane. The fuel supply passageway may include a substantially triangular shape.
摘要翻译：旋流器组件。旋流器组件可以包括轮毂，定位在轮毂上的叶片和从轮毂延伸穿过叶片的燃料供给通道。燃料供应通道可以包括大致三角形的形状。

10. 发明授权

US07946383B2 Acoustic load mitigator 有权
标题翻译：声负载减速器
公开(公告)号：US07946383B2
公开(公告)日：2011-05-24
申请号：US11940436
申请日：2007-11-15
申请人： John J. Lynch
发明人： John J. Lynch
IPC分类号： F01N1/00 , F01N1/02 , F01N1/06 , F01N5/00 , F01N13/08 , F01N13/18 , F02K1/08 , F02M35/10 , G10K11/16
CPC分类号： F16L55/033 , F16L55/041 , G21C1/084 , G21C19/00
摘要： A system for reducing an acoustic load of a fluid flow includes a first pipe. The first pipe includes a first end and a second end and a first aperture and a second aperture, the first and second apertures being intermediate the first and second ends. A second pipe includes a first end and a second end and a third aperture intermediate the first and second ends. The second pipe is connected at its first end to the first pipe at the first aperture. A bypass pipe includes a first end connected to the second aperture of the first pipe and a second end connected to the third aperture of the second pipe. A method of reducing an acoustic load of a flow in a standpipe connected to a first pipe configured to carry a main flow includes providing a bypass flow from the first pipe to the standpipe.
摘要翻译：用于降低流体流的声学负载的系统包括第一管。第一管包括第一端和第二端以及第一孔和第二孔，第一和第二孔位于第一端和第二端之间。第二管包括第一端和第二端以及位于第一端和第二端之间的第三孔。第二管在其第一端处连接到第一孔处的第一管。旁通管包括连接到第一管的第二孔的第一端和连接到第二管的第三孔的第二端。降低连接到构造成承载主流的第一管的立管中的流的声学负载的方法包括提供从第一管到立管的旁路流。

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