会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 4. 发明申请
    • HARDWARE ACCELERATOR WITH A SINGLE PARATITION FOR LATCHES AND COMBINATIONAL LOGIC
    • 硬件加速器,具有单个配件,用于锁定和组合逻辑
    • US20070294071A1
    • 2007-12-20
    • US11848489
    • 2007-08-31
    • Gernot GuentherViktor GyurisHarrell HoffmanKevin PasnikJohn Westerman
    • Gernot GuentherViktor GyurisHarrell HoffmanKevin PasnikJohn Westerman
    • G06F17/50
    • G06F17/5022
    • A hardware accelerator includes hardware support for a combinational only cycle and a latch only cycle in a simulation model with a single partition of latches and combinational logic. Preferred embodiments use a special 4-input 1-output function unit in the hardware accelerator in place of the normal latch function that write back the old latch value for combinational only cycles. Other embodiments include hardware support for separate array write disables for arrays and transparent latches depending on whether the cycle is a combinational only cycle and a latch only cycle. A conditional array write disable dependent on the occurrence of a hardware breakpoint is also included that supports switching from a latch plus combinational cycle to a latch only cycle, to give control to the user before evaluating the combinational logic if a breakpoint occurs on a latch.
    • 硬件加速器包括仅组合的周期的硬件支持,并且锁存器仅在具有锁存器和组合逻辑的单个分区的仿真模型中循环。 优选实施例在硬件加速器中使用特殊的4输入1输出功能单元来代替正常的锁存功能,该功能将仅存储组合的周期的旧锁存值回写。 其他实施例包括针对阵列和透明锁存器的单独阵列写禁止的硬件支持,取决于该周期是仅组合周期和仅锁存周期。 还包括依赖于硬件断点的发生的条件阵列写禁用,其支持从锁存器加组合周期切换到仅锁存周期,以在对锁存器发生断点时评估组合逻辑之前给予用户控制。