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1. 发明申请

US20070294071A1 HARDWARE ACCELERATOR WITH A SINGLE PARATITION FOR LATCHES AND COMBINATIONAL LOGIC 失效
标题翻译：硬件加速器，具有单个配件，用于锁定和组合逻辑
公开(公告)号：US20070294071A1
公开(公告)日：2007-12-20
申请号：US11848489
申请日：2007-08-31
申请人： Gernot Guenther , Viktor Gyuris , Harrell Hoffman , Kevin Pasnik , John Westerman
发明人： Gernot Guenther , Viktor Gyuris , Harrell Hoffman , Kevin Pasnik , John Westerman
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A hardware accelerator includes hardware support for a combinational only cycle and a latch only cycle in a simulation model with a single partition of latches and combinational logic. Preferred embodiments use a special 4-input 1-output function unit in the hardware accelerator in place of the normal latch function that write back the old latch value for combinational only cycles. Other embodiments include hardware support for separate array write disables for arrays and transparent latches depending on whether the cycle is a combinational only cycle and a latch only cycle. A conditional array write disable dependent on the occurrence of a hardware breakpoint is also included that supports switching from a latch plus combinational cycle to a latch only cycle, to give control to the user before evaluating the combinational logic if a breakpoint occurs on a latch.
摘要翻译：硬件加速器包括仅组合的周期的硬件支持，并且锁存器仅在具有锁存器和组合逻辑的单个分区的仿真模型中循环。优选实施例在硬件加速器中使用特殊的4输入1输出功能单元来代替正常的锁存功能，该功能将仅存储组合的周期的旧锁存值回写。其他实施例包括针对阵列和透明锁存器的单独阵列写禁止的硬件支持，取决于该周期是仅组合周期和仅锁存周期。还包括依赖于硬件断点的发生的条件阵列写禁用，其支持从锁存器加组合周期切换到仅锁存周期，以在对锁存器发生断点时评估组合逻辑之前给予用户控制。

2. 发明申请

US20060190232A1 Hardware accelerator with a single partition for latches and combinational logic 失效
标题翻译：具有单个分区的硬件加速器，用于锁存器和组合逻辑
公开(公告)号：US20060190232A1
公开(公告)日：2006-08-24
申请号：US11064727
申请日：2005-02-24
申请人： Gernot Guenther , Viktor Gyuris , Harrell Hoffman , Kevin Pasnik , John Westermann
发明人： Gernot Guenther , Viktor Gyuris , Harrell Hoffman , Kevin Pasnik , John Westermann
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A hardware accelerator includes hardware support for a combinational only cycle and a latch only cycle in a simulation model with a single partition of latches and combinational logic. Preferred embodiments use a special 4-input 1-output function unit in the hardware accelerator in place of the normal latch function that write back the old latch value for combinational only cycles. Other embodiments include hardware support for separate array write disables for arrays and transparent latches depending on whether the cycle is a combinational only cycle and a latch only cycle. A conditional array write disable dependent on the occurrence of a hardware breakpoint is also included that supports switching from a latch plus combinational cycle to a latch only cycle, to give control to the user before evaluating the combinational logic if a breakpoint occurs on a latch.
摘要翻译：硬件加速器包括仅组合的周期的硬件支持，并且锁存器仅在具有锁存器和组合逻辑的单个分区的仿真模型中循环。优选实施例在硬件加速器中使用特殊的4输入1输出功能单元来代替正常的锁存功能，该功能将仅存储组合的周期的旧锁存值回写。其他实施例包括针对阵列和透明锁存器的单独阵列写禁止的硬件支持，取决于该周期是仅组合周期和仅锁存周期。还包括依赖于硬件断点的发生的条件阵列写禁用，其支持从锁存器加组合周期切换到仅锁存周期，以在对锁存器发生断点时评估组合逻辑之前给予用户控制。

3. 发明授权

US07290228B2 Hardware accelerator with a single partition for latches and combinational logic 失效
标题翻译：具有单个分区的硬件加速器，用于锁存器和组合逻辑
公开(公告)号：US07290228B2
公开(公告)日：2007-10-30
申请号：US11064727
申请日：2005-02-24
申请人： Gernot E. Guenther , Viktor Gyuris , Harrell Hoffman , Kevin Anthony Pasnik , John Henry Westermann, Jr.
发明人： Gernot E. Guenther , Viktor Gyuris , Harrell Hoffman , Kevin Anthony Pasnik , John Henry Westermann, Jr.
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5022
摘要： A hardware accelerator includes hardware support for a combinational only cycle and a latch only cycle in a simulation model with a single partition of latches and combinational logic. Preferred embodiments use a special 4-input 1-output function unit in the hardware accelerator in place of the normal latch function that write back the old latch value for combinational only cycles. Other embodiments include hardware support for separate array write disables for arrays and transparent latches depending on whether the cycle is a combinational only cycle and a latch only cycle. A conditional array write disable dependent on the occurrence of a hardware breakpoint is also included that supports switching from a latch plus combinational cycle to a latch only cycle, to give control to the user before evaluating the combinational logic if a breakpoint occurs on a latch.
摘要翻译：硬件加速器包括仅组合的周期的硬件支持，并且锁存器仅在具有锁存器和组合逻辑的单个分区的仿真模型中循环。优选实施例在硬件加速器中使用特殊的4输入1输出功能单元来代替正常的锁存功能，该功能将仅存储组合的周期的旧锁存值回写。其他实施例包括针对阵列和透明锁存器的单独阵列写禁止的硬件支持，取决于该周期是仅组合周期和仅锁存周期。还包括依赖于硬件断点的发生的条件阵列写禁用，其支持从锁存器加组合周期切换到仅锁存周期，以在对锁存器发生断点时评估组合逻辑之前给予用户控制。

4. 发明授权

US07945433B2 Hardware simulation accelerator design and method that exploits a parallel structure of user models to support a larger user model size 有权
标题翻译：硬件仿真加速器设计和方法利用用户模型的并行结构来支持更大的用户模型大小
公开(公告)号：US07945433B2
公开(公告)日：2011-05-17
申请号：US11742100
申请日：2007-04-30
申请人： Daniel R. Crouse, II , Gernot E. Guenther , Viktor Gyuris , Harrell Hoffman , Kevin A. Pasnik , Thomas J. Tryt , John H. Westermann, Jr.
发明人： Daniel R. Crouse, II , Gernot E. Guenther , Viktor Gyuris , Harrell Hoffman , Kevin A. Pasnik , Thomas J. Tryt , John H. Westermann, Jr.
IPC分类号： G06F9/445 , G06F9/30
CPC分类号： G06F17/5022
摘要： A system and method for design verification and, more particularly, a hardware simulation accelerator design and method that exploits a parallel structure of user models to support a large user model size. The method includes a computer including N number of logic evaluation units (LEUs) that share a common pool of instruction memory (IM). The computer infrastructure is operable to: partition a number of parallel operations in a netlist; and send a same instruction stream of the partitioned number of parallel operations to N number of LEUs from a single IM. The system is a hardware simulation accelerator having a computer infrastructure operable to provide a stream of instructions to multiple LEUs from a single IM. The multiple LEUs are clustered together with multiple IMs such that each LEU is configured to use instructions from any of the multiple IMs thereby allowing a same instruction stream to drive the multiple LEUs.
摘要翻译：一种用于设计验证的系统和方法，更具体地说，一种利用用户模型的并行结构来支持大型用户模型大小的硬件仿真加速器设计和方法。该方法包括计算机，其包括共享公共指令存储器池（IM）的N个逻辑评估单元（LEU）。计算机基础设施可操作地：在网表中划分多个并行操作; 并且从单个IM向N个LEU发送分区数量的并行操作的相同指令流。该系统是具有计算机基础设施的硬件模拟加速器，其可操作以从单个IM向多个LEU提供指令流。多个LEU与多个IM集成在一起，使得每个LEU被配置为使用来自多个IM中的任何一个的指令，从而允许相同的指令流来驱动多个LEU。

5. 发明申请

US20070162270A1 Concealment of external array accesses in a hardware simulation accelerator 失效
标题翻译：在硬件仿真加速器中隐藏外部数组访问
公开(公告)号：US20070162270A1
公开(公告)日：2007-07-12
申请号：US11330685
申请日：2006-01-12
申请人： Gernot Guenther , Viktor Gyuris , John Westermann , Thomas Tryt
发明人： Gernot Guenther , Viktor Gyuris , John Westermann , Thomas Tryt
IPC分类号： G06F9/45
CPC分类号： G06F17/5027
摘要： A circuit arrangement and method detect external requests to access a memory array in a hardware simulation accelerator during performance of a simulation on a simulation model and access the memory array without halting the simulation in response to detecting the external request. Such functionality may be provided, for example, by detecting such external requests in response to processing a predetermined instruction in an instruction stream associated with the simulation model, where the predetermined instruction is configured to ensure a predetermined period of inactivity for the memory array. By doing so, the memory array can be accessed from outside of the hardware simulation accelerator during the processing of a simulation, and without requiring that the simulation be halted, thus reducing overhead and improving simulation efficiency.
摘要翻译：电路布置和方法在执行模拟模拟的仿真期间检测在硬件仿真加速器中访问存储器阵列的外部请求，并且在不停止响应于检测外部请求的仿真的情况下访问存储器阵列。可以例如通过响应于处理与仿真模型相关联的指令流中的预定指令来检测这样的外部请求来提供这样的功能，其中预定指令被配置为确保存储器阵列的预定的不活动时间段。通过这样做，可以在模拟处理期间从硬件仿真加速器的外部访问存储器阵列，并且不需要停止仿真，从而减少开销并提高仿真效率。

6. 发明授权

US07769577B2 Hardware accelerator with a single partition for latches and combinational logic 失效
标题翻译：具有单个分区的硬件加速器，用于锁存器和组合逻辑
公开(公告)号：US07769577B2
公开(公告)日：2010-08-03
申请号：US11848489
申请日：2007-08-31
申请人： Gernot E. Guenther , Viktor Gyuris , Harrell Hoffman , Kevin Anthony Pasnik , John Henry Westerman, Jr.
发明人： Gernot E. Guenther , Viktor Gyuris , Harrell Hoffman , Kevin Anthony Pasnik , John Henry Westerman, Jr.
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5022
摘要： A hardware accelerator includes hardware support for a combinational only cycle and a latch only cycle in a simulation model with a single partition of latches and combinational logic. Preferred embodiments use a special 4-input 1-output function unit in the hardware accelerator in place of the normal latch function that write back the old latch value for combinational only cycles. Other embodiments include hardware support for separate array write disables for arrays and transparent latches depending on whether the cycle is a combinational only cycle and a latch only cycle. A conditional array write disable dependent on the occurrence of a hardware breakpoint is also included that supports switching from a latch plus combinational cycle to a latch only cycle, to give control to the user before evaluating the combinational logic if a breakpoint occurs on a latch.
摘要翻译：硬件加速器包括仅组合的周期的硬件支持，并且锁存器仅在具有锁存器和组合逻辑的单个分区的仿真模型中循环。优选实施例在硬件加速器中使用特殊的4输入1输出功能单元来代替正常的锁存功能，该功能将仅存储组合的周期的旧锁存值回写。其他实施例包括针对阵列和透明锁存器的单独阵列写禁止的硬件支持，取决于该周期是仅组合周期和仅锁存周期。还包括依赖于硬件断点的发生的条件阵列写禁用，其支持从锁存器加组合周期切换到仅锁存周期，以在对锁存器发生断点时评估组合逻辑之前给予用户控制。

7. 发明授权

US07865346B2 Instruction encoding in a hardware simulation accelerator 有权
标题翻译：硬件仿真加速器中的指令编码
公开(公告)号：US07865346B2
公开(公告)日：2011-01-04
申请号：US11694940
申请日：2007-03-30
申请人： Gernot E. Günther , Viktor Gyuris , Kevin Anthony Pasnik , Thomas John Tryt , John H. Westermann, Jr.
发明人： Gernot E. Günther , Viktor Gyuris , Kevin Anthony Pasnik , Thomas John Tryt , John H. Westermann, Jr.
IPC分类号： G06F17/50 , G06G7/62 , H03K19/00
CPC分类号： G06F17/5022 , G06F11/261 , G06F17/5027
摘要： A hardware simulation accelerator to simulate logic designs, a method to encode instructions for use in the hardware simulation accelerator, and a computer program product having code of the method by which the hardware simulation accelerator can read encoded instructions to simulate the logic design, and computer program product of the encoded instructions to simulate a logic design in a hardware accelerator. Each instruction has one of a plurality of opcodes, the opcodes select which of the hardware resources of the hardware simulation accelerator will implement and use the values set forth in other programmable bits of the encoded instruction. The encoded instruction may be a routing and/or a gate evaluation instruction.
摘要翻译：用于模拟逻辑设计的硬件仿真加速器，用于编码在硬件仿真加速器中使用的指令的方法，以及具有硬件仿真加速器可以读取编码指令以模拟逻辑设计的方法的代码的计算机程序产品，以及计算机编码指令的程序产品来模拟硬件加速器中的逻辑设计。每个指令具有多个操作码之一，操作码选择硬件模拟加速器的硬件资源中的哪一个将实现，并使用编码指令的其他可编程位中阐述的值。编码指令可以是路由和/或门评估指令。

8. 发明授权

US09449169B2 Block storage virtualization on commodity secure digital cards 有权
标题翻译：在商品安全数字卡上阻止存储虚拟化
公开(公告)号：US09449169B2
公开(公告)日：2016-09-20
申请号：US13430175
申请日：2012-03-26
申请人： Cyprien Laplace , Harvey Tuch , Kenneth Charles Barr , Craig Farley Newell , Bi Wu , Viktor Gyuris
发明人： Cyprien Laplace , Harvey Tuch , Kenneth Charles Barr , Craig Farley Newell , Bi Wu , Viktor Gyuris
IPC分类号： G06F12/02 , G06F11/14 , G06F21/53 , G06F9/455 , G06F21/64 , G06F17/30
CPC分类号： G06F21/53 , G06F9/45533 , G06F11/1435 , G06F12/0246 , G06F17/30185 , G06F17/30218 , G06F17/30233 , G06F21/64 , G06F2212/7207 , G06F2221/2151
摘要： One embodiment of the present invention provides a system that facilitates storing an image file of a virtual machine on a potentially unprotected flash storage exhibiting sub-optimal non-sequential write performance on a mobile phone. During operation, the system stores in the flash storage data in a log-structured format and in a protected storage meta-data associated with the data stored in the flash storage. The system also checks integrity of the data stored in the flash storage using the meta-data in the protected storage.
摘要翻译：本发明的一个实施例提供一种便于将虚拟机的图像文件存储在移动电话上呈现次优的非顺序写入性能的潜在的不受保护的闪存存储器的系统。在操作期间，系统以闪存存储数据以日志结构格式和与存储在闪存存储器中的数据相关联的保护存储元数据中存储数据。系统还使用受保护存储器中的元数据来检查存储在闪存存储器中的数据的完整性。

9. 发明申请

US20080243462A1 INSTRUCTION ENCODING IN A HARDWARE SIMULATION ACCELERATOR 有权
标题翻译：硬件仿真加速器中的指令编码
公开(公告)号：US20080243462A1
公开(公告)日：2008-10-02
申请号：US11694940
申请日：2007-03-30
申请人： Gernot E. Guenther , Viktor Gyuris , Kevin Anthony Pasnik , Thomas John Tryt , John H. Westermann
发明人： Gernot E. Guenther , Viktor Gyuris , Kevin Anthony Pasnik , Thomas John Tryt , John H. Westermann
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F11/261 , G06F17/5027
摘要： A hardware simulation accelerator to simulate logic designs, a method to encode instructions for use in the hardware simulation accelerator, and a computer program product having code of the method by which the hardware simulation accelerator can read encoded instructions to simulate the logic design, and computer program product of the encoded instructions to simulate a logic design in a hardware accelerator. Each instruction has one of a plurality of opcodes, the opcodes select which of the hardware resources of the hardware simulation accelerator will implement and use the values set forth in other programmable bits of the encoded instruction. The encoded instruction may be a routing and/or a gate evaluation instruction.
摘要翻译：用于模拟逻辑设计的硬件仿真加速器，用于编码在硬件仿真加速器中使用的指令的方法，以及具有硬件仿真加速器可以读取编码指令以模拟逻辑设计的方法的代码的计算机程序产品，以及计算机编码指令的程序产品来模拟硬件加速器中的逻辑设计。每个指令具有多个操作码之一，操作码选择硬件模拟加速器的硬件资源中的哪一个将实现，并使用编码指令的其他可编程位中阐述的值。编码指令可以是路由和/或门评估指令。

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